arch/alpha/kernel/core_tsunami.c

   1 /*
   2  *      linux/arch/alpha/kernel/core_tsunami.c
   3  *
   4  * Based on code written by David A. Rusling (david.rusling@reo.mts.dec.com).
   5  *
   6  * Code common to all TSUNAMI core logic chips.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/sched.h>
  13 #include <linux/init.h>
  14
  15 #include <asm/ptrace.h>
  16 #include <asm/system.h>
  17 #include <asm/pci.h>
  18 #include <asm/smp.h>
  19
  20 #define __EXTERN_INLINE inline
  21 #include <asm/io.h>
  22 #include <asm/core_tsunami.h>
  23 #undef __EXTERN_INLINE
  24
  25 #include "proto.h"
  26 #include "pci_impl.h"
  27
  28 int TSUNAMI_bootcpu;
  29
  30 /*
  31  * NOTE: Herein lie back-to-back mb instructions.  They are magic.
  32  * One plausible explanation is that the I/O controller does not properly
  33  * handle the system transaction.  Another involves timing.  Ho hum.
  34  */
  35
  36 /*
  37  * BIOS32-style PCI interface:
  38  */
  39
  40 #define DEBUG_MCHECK 0          /* 0 = minimal, 1 = debug, 2 = debug+dump.  */
  41 #define DEBUG_CONFIG 0
  42
  43 #if DEBUG_CONFIG
  44 # define DBG_CFG(args)  printk args
  45 #else
  46 # define DBG_CFG(args)
  47 #endif
  48
  49
  50 /*
  51  * Given a bus, device, and function number, compute resulting
  52  * configuration space address
  53  * accordingly.  It is therefore not safe to have concurrent
  54  * invocations to configuration space access routines, but there
  55  * really shouldn't be any need for this.
  56  *
  57  * Note that all config space accesses use Type 1 address format.
  58  *
  59  * Note also that type 1 is determined by non-zero bus number.
  60  *
  61  * Type 1:
  62  *
  63  *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  64  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  65  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  66  * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
  67  * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  68  *
  69  *      31:24   reserved
  70  *      23:16   bus number (8 bits = 128 possible buses)
  71  *      15:11   Device number (5 bits)
  72  *      10:8    function number
  73  *       7:2    register number
  74  *
  75  * Notes:
  76  *      The function number selects which function of a multi-function device
  77  *      (e.g., SCSI and Ethernet).
  78  *
  79  *      The register selects a DWORD (32 bit) register offset.  Hence it
  80  *      doesn't get shifted by 2 bits as we want to "drop" the bottom two
  81  *      bits.
  82  */
  83
  84 static int
  85 mk_conf_addr(struct pci_dev *dev, int where, unsigned long *pci_addr,
  86              unsigned char *type1)
  87 {
  88         struct pci_controler *hose = dev->sysdata ? : probing_hose;
  89         unsigned long addr;
  90         u8 bus = dev->bus->number;
  91         u8 device_fn = dev->devfn;
  92
  93         DBG_CFG(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x, "
  94                  "pci_addr=0x%p, type1=0x%p)\n",
  95                  bus, device_fn, where, pci_addr, type1));
  96
  97         if (hose->first_busno == dev->bus->number)
  98                 bus = 0;
  99         *type1 = (bus != 0);
 100
 101         addr = (bus << 16) | (device_fn << 8) | where;
 102         addr |= hose->config_space;
 103
 104         *pci_addr = addr;
 105         DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
 106         return 0;
 107 }
 108
 109 static int
 110 tsunami_read_config_byte(struct pci_dev *dev, int where, u8 *value)
 111 {
 112         unsigned long addr;
 113         unsigned char type1;
 114
 115         if (mk_conf_addr(dev, where, &addr, &type1))
 116                 return PCIBIOS_DEVICE_NOT_FOUND;
 117
 118         *value = __kernel_ldbu(*(vucp)addr);
 119         return PCIBIOS_SUCCESSFUL;
 120 }
 121
 122 static int
 123 tsunami_read_config_word(struct pci_dev *dev, int where, u16 *value)
 124 {
 125         unsigned long addr;
 126         unsigned char type1;
 127
 128         if (mk_conf_addr(dev, where, &addr, &type1))
 129                 return PCIBIOS_DEVICE_NOT_FOUND;
 130
 131         *value = __kernel_ldwu(*(vusp)addr);
 132         return PCIBIOS_SUCCESSFUL;
 133 }
 134
 135 static int
 136 tsunami_read_config_dword(struct pci_dev *dev, int where, u32 *value)
 137 {
 138         unsigned long addr;
 139         unsigned char type1;
 140
 141         if (mk_conf_addr(dev, where, &addr, &type1))
 142                 return PCIBIOS_DEVICE_NOT_FOUND;
 143
 144         *value = *(vuip)addr;
 145         return PCIBIOS_SUCCESSFUL;
 146 }
 147
 148 static int
 149 tsunami_write_config_byte(struct pci_dev *dev, int where, u8 value)
 150 {
 151         unsigned long addr;
 152         unsigned char type1;
 153
 154         if (mk_conf_addr(dev, where, &addr, &type1))
 155                 return PCIBIOS_DEVICE_NOT_FOUND;
 156
 157         __kernel_stb(value, *(vucp)addr);
 158         return PCIBIOS_SUCCESSFUL;
 159 }
 160
 161 static int
 162 tsunami_write_config_word(struct pci_dev *dev, int where, u16 value)
 163 {
 164         unsigned long addr;
 165         unsigned char type1;
 166
 167         if (mk_conf_addr(dev, where, &addr, &type1))
 168                 return PCIBIOS_DEVICE_NOT_FOUND;
 169
 170         __kernel_stw(value, *(vusp)addr);
 171         return PCIBIOS_SUCCESSFUL;
 172 }
 173
 174 static int
 175 tsunami_write_config_dword(struct pci_dev *dev, int where, u32 value)
 176 {
 177         unsigned long addr;
 178         unsigned char type1;
 179
 180         if (mk_conf_addr(dev, where, &addr, &type1))
 181                 return PCIBIOS_DEVICE_NOT_FOUND;
 182
 183         *(vuip)addr = value;
 184         return PCIBIOS_SUCCESSFUL;
 185 }
 186
 187 struct pci_ops tsunami_pci_ops =
 188 {
 189         read_byte:      tsunami_read_config_byte,
 190         read_word:      tsunami_read_config_word,
 191         read_dword:     tsunami_read_config_dword,
 192         write_byte:     tsunami_write_config_byte,
 193         write_word:     tsunami_write_config_word,
 194         write_dword:    tsunami_write_config_dword
 195 };
 196 \f
 197 #ifdef NXM_MACHINE_CHECKS_ON_TSUNAMI
 198 static long
 199 tsunami_probe_read(volatile unsigned long *vaddr)
 200 {
 201         long dont_care, probe_result;
 202         int cpu = smp_processor_id();
 203         int s = swpipl(6);      /* Block everything but machine checks. */
 204
 205         mcheck_taken(cpu) = 0;
 206         mcheck_expected(cpu) = 1;
 207         mb();
 208         dont_care = *vaddr;
 209         draina();
 210         mcheck_expected(cpu) = 0;
 211         probe_result = !mcheck_taken(cpu);
 212         mcheck_taken(cpu) = 0;
 213         setipl(s);
 214
 215         printk("dont_care == 0x%lx\n", dont_care);
 216
 217         return probe_result;
 218 }
 219
 220 static long
 221 tsunami_probe_write(volatile unsigned long *vaddr)
 222 {
 223         long true_contents, probe_result = 1;
 224
 225         TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */
 226         true_contents = *vaddr;
 227         *vaddr = 0;
 228         draina();
 229         if (TSUNAMI_cchip->misc.csr & (1L << 28)) {
 230                 int source = (TSUNAMI_cchip->misc.csr >> 29) & 7;
 231                 TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */
 232                 probe_result = 0;
 233                 printk("tsunami_probe_write: unit %d at 0x%016lx\n", source,
 234                        (unsigned long)vaddr);
 235         }
 236         if (probe_result)
 237                 *vaddr = true_contents;
 238         return probe_result;
 239 }
 240 #else
 241 #define tsunami_probe_read(ADDR) 1
 242 #endif /* NXM_MACHINE_CHECKS_ON_TSUNAMI */
 243
 244 #define FN __FUNCTION__
 245
 246 static void __init
 247 tsunami_init_one_pchip(tsunami_pchip *pchip, int index,
 248                        unsigned long *mem_start)
 249 {
 250         struct pci_controler *hose;
 251
 252         if (tsunami_probe_read(&pchip->pctl.csr) == 0)
 253                 return;
 254
 255         hose = alloc_pci_controler(mem_start);
 256         hose->io_space = alloc_resource(mem_start);
 257         hose->mem_space = alloc_resource(mem_start);
 258
 259         hose->config_space = TSUNAMI_CONF(index);
 260         hose->index = index;
 261
 262         hose->io_space->start = TSUNAMI_IO(index) - TSUNAMI_IO_BIAS;
 263         hose->io_space->end = hose->io_space->start + 0xffff;
 264         hose->io_space->name = pci_io_names[index];
 265
 266         hose->mem_space->start = TSUNAMI_MEM(index) - TSUNAMI_MEM_BIAS;
 267         hose->mem_space->end = hose->mem_space->start + 0xffffffff;
 268         hose->mem_space->name = pci_mem_names[index];
 269
 270         request_resource(&ioport_resource, hose->io_space);
 271         request_resource(&iomem_resource, hose->mem_space);
 272
 273         /*
 274          * Set up the PCI->physical memory translation windows.
 275          * For now, windows 1,2 and 3 are disabled.  In the future,
 276          * we may want to use them to do scatter/gather DMA.
 277          *
 278          * Window 0 goes at 1 GB and is 1 GB large, mapping to 0.
 279          * Window 1 goes at 2 GB and is 1 GB large, mapping to 1GB.
 280          */
 281
 282         pchip->wsba[0].csr = TSUNAMI_DMA_WIN0_BASE_DEFAULT | 1UL;
 283         pchip->wsm[0].csr  = (TSUNAMI_DMA_WIN0_SIZE_DEFAULT - 1) &
 284                              0xfff00000UL;
 285         pchip->tba[0].csr  = TSUNAMI_DMA_WIN0_TRAN_DEFAULT;
 286
 287         pchip->wsba[1].csr = TSUNAMI_DMA_WIN1_BASE_DEFAULT | 1UL;
 288         pchip->wsm[1].csr  = (TSUNAMI_DMA_WIN1_SIZE_DEFAULT - 1) &
 289                              0xfff00000UL;
 290         pchip->tba[1].csr  = TSUNAMI_DMA_WIN1_TRAN_DEFAULT;
 291
 292         pchip->wsba[2].csr = 0;
 293         pchip->wsba[3].csr = 0;
 294         mb();
 295 }
 296
 297 void __init
 298 tsunami_init_arch(unsigned long *mem_start, unsigned long *mem_end)
 299 {
 300 #ifdef NXM_MACHINE_CHECKS_ON_TSUNAMI
 301         extern asmlinkage void entInt(void);
 302         unsigned long tmp;
 303
 304         /* Ho hum.. init_arch is called before init_IRQ, but we need to be
 305            able to handle machine checks.  So install the handler now.  */
 306         wrent(entInt, 0);
 307
 308         /* NXMs just don't matter to Tsunami--unless they make it
 309            choke completely. */
 310         tmp = (unsigned long)(TSUNAMI_cchip - 1);
 311         printk("%s: probing bogus address:  0x%016lx\n", FN, bogus_addr);
 312         printk("\tprobe %s\n",
 313                tsunami_probe_write((unsigned long *)bogus_addr)
 314                ? "succeeded" : "failed");
 315 #endif /* NXM_MACHINE_CHECKS_ON_TSUNAMI */
 316
 317 #if 0
 318         printk("%s: CChip registers:\n", FN);
 319         printk("%s: CSR_CSC 0x%lx\n", FN, TSUNAMI_cchip->csc.csr);
 320         printk("%s: CSR_MTR 0x%lx\n", FN, TSUNAMI_cchip.mtr.csr);
 321         printk("%s: CSR_MISC 0x%lx\n", FN, TSUNAMI_cchip->misc.csr);
 322         printk("%s: CSR_DIM0 0x%lx\n", FN, TSUNAMI_cchip->dim0.csr);
 323         printk("%s: CSR_DIM1 0x%lx\n", FN, TSUNAMI_cchip->dim1.csr);
 324         printk("%s: CSR_DIR0 0x%lx\n", FN, TSUNAMI_cchip->dir0.csr);
 325         printk("%s: CSR_DIR1 0x%lx\n", FN, TSUNAMI_cchip->dir1.csr);
 326         printk("%s: CSR_DRIR 0x%lx\n", FN, TSUNAMI_cchip->drir.csr);
 327
 328         printk("%s: DChip registers:\n");
 329         printk("%s: CSR_DSC 0x%lx\n", FN, TSUNAMI_dchip->dsc.csr);
 330         printk("%s: CSR_STR 0x%lx\n", FN, TSUNAMI_dchip->str.csr);
 331         printk("%s: CSR_DREV 0x%lx\n", FN, TSUNAMI_dchip->drev.csr);
 332 #endif
 333         TSUNAMI_bootcpu = __hard_smp_processor_id();
 334
 335         /* With multiple PCI busses, we play with I/O as physical addrs.  */
 336         ioport_resource.end = ~0UL;
 337         iomem_resource.end = ~0UL;
 338
 339         /* Find how many hoses we have, and initialize them.  TSUNAMI
 340            and TYPHOON can have 2, but might only have 1 (DS10).  */
 341
 342         tsunami_init_one_pchip(TSUNAMI_pchip0, 0, mem_start);
 343         if (TSUNAMI_cchip->csc.csr & 1L<<14)
 344                 tsunami_init_one_pchip(TSUNAMI_pchip1, 1, mem_start);
 345 }
 346
 347 static inline void
 348 tsunami_pci_clr_err_1(tsunami_pchip *pchip)
 349 {
 350         unsigned int jd;
 351
 352         jd = pchip->perror.csr;
 353         pchip->perror.csr = 0x040;
 354         mb();
 355         jd = pchip->perror.csr;
 356 }
 357
 358 static inline void
 359 tsunami_pci_clr_err(void)
 360 {
 361         tsunami_pci_clr_err_1(TSUNAMI_pchip0);
 362
 363         /* TSUNAMI and TYPHOON can have 2, but might only have 1 (DS10) */
 364         if (TSUNAMI_cchip->csc.csr & 1L<<14)
 365             tsunami_pci_clr_err_1(TSUNAMI_pchip1);
 366 }
 367
 368 void
 369 tsunami_machine_check(unsigned long vector, unsigned long la_ptr,
 370                       struct pt_regs * regs)
 371 {
 372         /* Clear error before any reporting.  */
 373         mb();
 374         mb();  /* magic */
 375         draina();
 376         tsunami_pci_clr_err();
 377         wrmces(0x7);
 378         mb();
 379
 380         process_mcheck_info(vector, la_ptr, regs, "TSUNAMI",
 381                             mcheck_expected(smp_processor_id()));
 382 }