2 * linux/openpic.h -- OpenPIC definitions
4 * Copyright (C) 1997 Geert Uytterhoeven
6 * This file is based on the following documentation:
8 * The Open Programmable Interrupt Controller (PIC)
9 * Register Interface Specification Revision 1.2
11 * Issue Date: October 1995
13 * Issued jointly by Advanced Micro Devices and Cyrix Corporation
15 * AMD is a registered trademark of Advanced Micro Devices, Inc.
16 * Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc.
17 * All Rights Reserved.
19 * To receive a copy of this documentation, send an email to openpic@amd.com.
21 * This file is subject to the terms and conditions of the GNU General Public
22 * License. See the file COPYING in the main directory of this archive
26 #ifndef _LINUX_OPENPIC_H
27 #define _LINUX_OPENPIC_H
29 #if !defined(__powerpc__) && !defined(__i386__)
30 #error Unsupported OpenPIC platform
37 * OpenPIC supports up to 2048 interrupt sources and up to 32 processors
40 #define OPENPIC_MAX_SOURCES 2048
41 #define OPENPIC_MAX_PROCESSORS 32
43 #define OPENPIC_NUM_TIMERS 4
44 #define OPENPIC_NUM_IPI 4
45 #define OPENPIC_NUM_PRI 16
46 #define OPENPIC_NUM_VECTORS 256
53 #define OPENPIC_VEC_SOURCE 0x10 /* and up */
54 #define OPENPIC_VEC_TIMER 0x40 /* and up */
55 #define OPENPIC_VEC_IPI 0x50 /* and up */
56 #define OPENPIC_VEC_SPURIOUS 99
60 * OpenPIC Registers are 32 bits and aligned on 128 bit boundaries
63 typedef struct _OpenPIC_Reg
{
64 u_int Reg
; /* Little endian! */
70 * Per Processor Registers
73 typedef struct _OpenPIC_Processor
{
75 * Private Shadow Registers (for SLiC backwards compatibility)
77 u_int IPI0_Dispatch_Shadow
; /* Write Only */
79 u_int IPI0_Vector_Priority_Shadow
; /* Read/Write */
82 * Interprocessor Interrupt Command Ports
84 OpenPIC_Reg _IPI_Dispatch
[OPENPIC_NUM_IPI
]; /* Write Only */
86 * Current Task Priority Register
88 OpenPIC_Reg _Current_Task_Priority
; /* Read/Write */
93 OpenPIC_Reg _Who_Am_I
; /* Read Only */
99 * Interrupt Acknowledge Register
101 OpenPIC_Reg _Interrupt_Acknowledge
; /* Read Only */
106 * End of Interrupt (EOI) Register
108 OpenPIC_Reg _EOI
; /* Read/Write */
117 typedef struct _OpenPIC_Timer
{
118 OpenPIC_Reg _Current_Count
; /* Read Only */
119 OpenPIC_Reg _Base_Count
; /* Read/Write */
120 OpenPIC_Reg _Vector_Priority
; /* Read/Write */
121 OpenPIC_Reg _Destination
; /* Read/Write */
129 typedef struct _OpenPIC_Global
{
131 * Feature Reporting Registers
133 OpenPIC_Reg _Feature_Reporting0
; /* Read Only */
134 OpenPIC_Reg _Feature_Reporting1
; /* Future Expansion */
136 * Global Configuration Registers
138 OpenPIC_Reg _Global_Configuration0
; /* Read/Write */
139 OpenPIC_Reg _Global_Configuration1
; /* Future Expansion */
141 * Vendor Specific Registers
143 OpenPIC_Reg _Vendor_Specific
[4];
145 * Vendor Identification Register
147 OpenPIC_Reg _Vendor_Identification
; /* Read Only */
149 * Processor Initialization Register
151 OpenPIC_Reg _Processor_Initialization
; /* Read/Write */
153 * IPI Vector/Priority Registers
155 OpenPIC_Reg _IPI_Vector_Priority
[OPENPIC_NUM_IPI
]; /* Read/Write */
157 * Spurious Vector Register
159 OpenPIC_Reg _Spurious_Vector
; /* Read/Write */
161 * Global Timer Registers
163 OpenPIC_Reg _Timer_Frequency
; /* Read/Write */
164 OpenPIC_Timer Timer
[OPENPIC_NUM_TIMERS
];
170 * Interrupt Source Registers
173 typedef struct _OpenPIC_Source
{
174 OpenPIC_Reg _Vector_Priority
; /* Read/Write */
175 OpenPIC_Reg _Destination
; /* Read/Write */
180 * OpenPIC Register Map
186 * Per Processor Registers --- Private Access
188 OpenPIC_Processor Private
;
195 OpenPIC_Global Global
;
197 * Interrupt Source Configuration Registers
199 OpenPIC_Source Source
[OPENPIC_MAX_SOURCES
];
201 * Per Processor Registers
203 OpenPIC_Processor Processor
[OPENPIC_MAX_PROCESSORS
];
206 extern volatile struct OpenPIC
*OpenPIC
;
207 extern u_int OpenPIC_NumInitSenses
;
208 extern u_char
*OpenPIC_InitSenses
;
212 * Current Task Priority Register
215 #define OPENPIC_CURRENT_TASK_PRIORITY_MASK 0x0000000f
221 #define OPENPIC_WHO_AM_I_ID_MASK 0x0000001f
224 * Feature Reporting Register 0
227 #define OPENPIC_FEATURE_LAST_SOURCE_MASK 0x07ff0000
228 #define OPENPIC_FEATURE_LAST_SOURCE_SHIFT 16
229 #define OPENPIC_FEATURE_LAST_PROCESSOR_MASK 0x00001f00
230 #define OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT 8
231 #define OPENPIC_FEATURE_VERSION_MASK 0x000000ff
234 * Global Configuration Register 0
237 #define OPENPIC_CONFIG_RESET 0x80000000
238 #define OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE 0x20000000
239 #define OPENPIC_CONFIG_BASE_MASK 0x000fffff
242 * Vendor Identification Register
245 #define OPENPIC_VENDOR_ID_STEPPING_MASK 0x00ff0000
246 #define OPENPIC_VENDOR_ID_STEPPING_SHIFT 16
247 #define OPENPIC_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
248 #define OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT 8
249 #define OPENPIC_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
252 * Vector/Priority Registers
255 #define OPENPIC_MASK 0x80000000
256 #define OPENPIC_ACTIVITY 0x40000000 /* Read Only */
257 #define OPENPIC_PRIORITY_MASK 0x000f0000
258 #define OPENPIC_PRIORITY_SHIFT 16
259 #define OPENPIC_VECTOR_MASK 0x000000ff
263 * Interrupt Source Registers
266 #define OPENPIC_SENSE_POLARITY 0x00800000 /* Undoc'd */
267 #define OPENPIC_SENSE_LEVEL 0x00400000
274 #define OPENPIC_COUNT_MASK 0x7fffffff
275 #define OPENPIC_TIMER_TOGGLE 0x80000000
276 #define OPENPIC_TIMER_COUNT_INHIBIT 0x80000000
280 * Aliases to make life simpler
283 /* Per Processor Registers */
284 #define IPI_Dispatch(i) _IPI_Dispatch[i].Reg
285 #define Current_Task_Priority _Current_Task_Priority.Reg
287 #define Who_Am_I _Who_Am_I.Reg
290 #define Interrupt_Acknowledge _Interrupt_Acknowledge.Reg
294 /* Global Registers */
295 #define Feature_Reporting0 _Feature_Reporting0.Reg
296 #define Feature_Reporting1 _Feature_Reporting1.Reg
297 #define Global_Configuration0 _Global_Configuration0.Reg
298 #define Global_Configuration1 _Global_Configuration1.Reg
299 #define Vendor_Specific(i) _Vendor_Specific[i].Reg
300 #define Vendor_Identification _Vendor_Identification.Reg
301 #define Processor_Initialization _Processor_Initialization.Reg
302 #define IPI_Vector_Priority(i) _IPI_Vector_Priority[i].Reg
303 #define Spurious_Vector _Spurious_Vector.Reg
304 #define Timer_Frequency _Timer_Frequency.Reg
306 /* Timer Registers */
307 #define Current_Count _Current_Count.Reg
308 #define Base_Count _Base_Count.Reg
309 #define Vector_Priority _Vector_Priority.Reg
310 #define Destination _Destination.Reg
312 /* Interrupt Source Registers */
313 #define Vector_Priority _Vector_Priority.Reg
314 #define Destination _Destination.Reg
320 /* Global Operations */
321 extern void openpic_init(int);
322 extern void openpic_reset(void);
323 extern void openpic_enable_8259_pass_through(void);
324 extern void openpic_disable_8259_pass_through(void);
326 extern u_int
openpic_irq(u_int cpu
);
329 extern void openpic_eoi(void);
330 extern u_int
openpic_get_priority(void);
331 extern void openpic_set_priority(u_int pri
);
333 extern void openpic_eoi(u_int cpu
);
334 extern u_int
openpic_get_priority(u_int cpu
);
335 extern void openpic_set_priority(u_int cpu
, u_int pri
);
337 extern u_int
openpic_get_spurious(void);
338 extern void openpic_set_spurious(u_int vector
);
339 extern void openpic_init_processor(u_int cpumask
);
341 /* Interprocessor Interrupts */
342 extern void openpic_initipi(u_int ipi
, u_int pri
, u_int vector
);
344 extern void openpic_cause_IPI(u_int ipi
, u_int cpumask
);
346 extern void openpic_cause_IPI(u_int cpu
, u_int ipi
, u_int cpumask
);
349 /* Timer Interrupts */
350 extern void openpic_inittimer(u_int timer
, u_int pri
, u_int vector
);
351 extern void openpic_maptimer(u_int timer
, u_int cpumask
);
353 /* Interrupt Sources */
354 extern void openpic_enable_irq(u_int irq
);
355 extern void openpic_disable_irq(u_int irq
);
356 extern void openpic_initirq(u_int irq
, u_int pri
, u_int vector
, int polarity
,
358 extern void openpic_mapirq(u_int irq
, u_int cpumask
);
359 extern void openpic_set_sense(u_int irq
, int sense
);
361 #endif /* __KERNEL__ */
363 #endif /* _LINUX_OPENPIC_H */