drivers/usb/ohci.h

   1 #ifndef __LINUX_OHCI_H
   2 #define __LINUX_OHCI_H
   3
   4 /*
   5  * Open Host Controller Interface data structures and defines.
   6  *
   7  * (C) Copyright 1999 Gregory P. Smith <greg@electricrain.com>
   8  *
   9  * $Id: ohci.h,v 1.40 1999/09/05 07:26:46 greg Exp $
  10  */
  11
  12 #include <linux/list.h>
  13 #include <asm/io.h>
  14
  15 #include "usb.h"
  16
  17 struct ohci_ed;
  18
  19 /*
  20  * Each TD must be aligned on a 16-byte boundary.  From the OHCI v1.0 spec
  21  * it does not state that TDs must be contiguious in memory (due to the
  22  * use of the next_td field).  This gives us extra room at the end of a
  23  * TD for our own driver specific data.
  24  *
  25  * This structure's size must be a multiple of 16 bytes. ?? no way, I
  26  * don't see why.  Alignment should be all that matters.
  27  */
  28 struct ohci_td {
  29         /* OHCI Hardware fields */
  30         __u32 info;             /* TD status & type flags */
  31         __u32 cur_buf;          /* Current Buffer Pointer (bus address) */
  32         __u32 next_td;          /* Next TD Pointer (bus address) */
  33         __u32 buf_end;          /* Memory Buffer End Pointer (bus address) */
  34
  35         /* Driver specific fields */
  36         struct ohci_ed *ed;             /* address of the ED this TD is on */
  37         struct ohci_td *next_dl_td;     /* used during donelist processing */
  38         void *data;                     /* virt. address of the the buffer */
  39         usb_device_irq completed;       /* Completion handler routine */
  40         int hcd_flags;                  /* Flags for the HCD: */
  41                 /* bit0: Is this TD allocated? */
  42                 /* bit1: Is this a dummy (end of list) TD? */
  43                 /* bit2: do NOT automatically free this TD on completion */
  44                 /* bit3: this is the last TD in a contiguious TD chain */
  45
  46         struct usb_device *usb_dev;     /* the owning device */
  47
  48         void *dev_id;   /* user defined pointer passed to irq handler */
  49 } __attribute((aligned(32)));
  50
  51 #define OHCI_TD_ROUND   (1 << 18)       /* buffer rounding bit */
  52 #define OHCI_TD_D       (3 << 19)       /* direction of xfer: */
  53 #define OHCI_TD_D_IN    (2 << 19)
  54 #define OHCI_TD_D_OUT   (1 << 19)
  55 #define OHCI_TD_D_SETUP (0 << 19)
  56 #define td_set_dir_in(d)        ((d) ? OHCI_TD_D_IN : OHCI_TD_D_OUT )
  57 #define td_set_dir_out(d)       ((d) ? OHCI_TD_D_OUT : OHCI_TD_D_IN )
  58 #define OHCI_TD_IOC_DELAY (7 << 21)     /* frame delay allowed before int. */
  59 #define OHCI_TD_IOC_OFF (OHCI_TD_IOC_DELAY)     /* no interrupt on complete */
  60 #define td_set_ioc_delay(frames)        (((frames) & 7) << 21)
  61 #define OHCI_TD_DT      (3 << 24)       /* data toggle bits */
  62 #define TOGGLE_AUTO     (0 << 24)       /* automatic (from the ED) */
  63 #define TOGGLE_DATA0    (2 << 24)       /* force Data0 */
  64 #define TOGGLE_DATA1    (3 << 24)       /* force Data1 */
  65 #define td_force_toggle(b)      (((b) | 2) << 24)
  66 #define OHCI_TD_ERRCNT  (3 << 26)       /* error count */
  67 #define td_errorcount(td)       ((le32_to_cpup(&(td).info) >> 26) & 3)
  68 #define clear_td_errorcount(td) ((td)->info &= cpu_to_le32(~(__u32)OHCI_TD_ERRCNT))
  69 #define OHCI_TD_CC      (0xf << 28)     /* condition code */
  70 #define OHCI_TD_CC_GET(td_i) (((td_i) >> 28) & 0xf)
  71 #define OHCI_TD_CC_NEW  (OHCI_TD_CC)    /* set this on all unaccessed TDs! */
  72 #define td_cc_notaccessed(td)   ((le32_to_cpup(&(td).info) >> 29) == 7)
  73 #define td_cc_accessed(td)      ((le32_to_cpup(&(td).info) >> 29) != 7)
  74 #define td_cc_noerror(td)       (((le32_to_cpup(&(td).info)) & OHCI_TD_CC) == 0)
  75 #define td_done(td)     (td_cc_noerror((td)) || (td_errorcount((td)) == 3))
  76
  77 /*
  78  * Macros to use the td->hcd_flags field.
  79  */
  80 #define td_allocated(td)        ((td).hcd_flags & 1)
  81 #define allocate_td(td)         ((td)->hcd_flags |= 1)
  82 #define ohci_free_td(td)        ((td)->hcd_flags &= ~(__u32)1)
  83
  84 #define td_dummy(td)            ((td).hcd_flags & 2)
  85 #define make_dumb_td(td)        ((td)->hcd_flags |= 2)
  86 #define clear_dumb_td(td)       ((td)->hcd_flags &= ~(__u32)2)
  87
  88 #define td_endofchain(td)       ((td).hcd_flags & (1 << 3))
  89 #define clear_td_endofchain(td) ((td)->hcd_flags &= ~(1 << 3))
  90 #define set_td_endofchain(td)   ((td)->hcd_flags |= (1 << 3))
  91
  92 /*
  93  * These control if the IRQ will call ohci_free_td after taking the TDs
  94  * off of the donelist (assuming the completion function does not ask
  95  * for the TD to be requeued).
  96  */
  97 #define can_auto_free(td)       (!((td).hcd_flags & 4))
  98 #define noauto_free_td(td)      ((td)->hcd_flags |= 4)
  99 #define auto_free_td(td)        ((td)->hcd_flags &= ~(__u32)4)
 100
 101
 102 /*
 103  * The endpoint descriptors also requires 16-byte alignment
 104  */
 105 struct ohci_ed {
 106         /* OHCI hardware fields */
 107         __u32 status;
 108         __u32 tail_td;  /* TD Queue tail pointer */
 109         __u32 _head_td; /* TD Queue head pointer, toggle carry & halted bits */
 110         __u32 next_ed;  /* Next ED */
 111
 112         /* driver fields */
 113         struct ohci_device *ohci_dev;
 114         struct ohci_ed  *ed_chain;
 115 } __attribute((aligned(16)));
 116
 117 /* get the head_td */
 118 #define ed_head_td(ed)  (le32_to_cpup(&(ed)->_head_td) & 0xfffffff0)
 119 #define ed_tail_td(ed)  (le32_to_cpup(&(ed)->tail_td))
 120
 121 /* save the carry & halted flag while setting the head_td */
 122 #define set_ed_head_td(ed, td)  ((ed)->_head_td = cpu_to_le32((td)) \
 123                                  | ((ed)->_head_td & cpu_to_le32(3)))
 124
 125 /* Control the ED's halted and carry flags */
 126 #define ohci_halt_ed(ed)        ((ed)->_head_td |= cpu_to_le32(1))
 127 #define ohci_unhalt_ed(ed)      ((ed)->_head_td &= cpu_to_le32(~(__u32)1))
 128 #define ohci_ed_halted(ed)      ((ed)->_head_td & cpu_to_le32(1))
 129 #define ohci_ed_set_carry(ed)   ((ed)->_head_td |= cpu_to_le32(2))
 130 #define ohci_ed_clr_carry(ed)   ((ed)->_head_td &= ~cpu_to_le32(2))
 131 #define ohci_ed_carry(ed)       ((le32_to_cpup(&(ed)->_head_td) >> 1) & 1)
 132
 133 #define OHCI_ED_SKIP    (1 << 14)
 134 #define OHCI_ED_MPS     (0x7ff << 16)
 135 /* FIXME: should cap at the USB max packet size [0x4ff] */
 136 #define ed_set_maxpacket(s)     (((s) << 16) & OHCI_ED_MPS)
 137 #define OHCI_ED_F_NORM  (0)
 138 #define OHCI_ED_F_ISOC  (1 << 15)
 139 #define ed_set_type_isoc(i)     ((i) ? OHCI_ED_F_ISOC : OHCI_ED_F_NORM)
 140 #define OHCI_ED_S_LOW   (1 << 13)
 141 #define OHCI_ED_S_HIGH  (0)
 142 #define ed_set_speed(s)         ((s) ? OHCI_ED_S_LOW : OHCI_ED_S_HIGH)
 143 #define OHCI_ED_D       (3 << 11)
 144 #define OHCI_ED_D_IN    (2 << 11)
 145 #define OHCI_ED_D_OUT   (1 << 11)
 146 #define ed_set_dir_in(d)        ((d) ? OHCI_ED_D_IN : OHCI_ED_D_OUT)
 147 #define ed_set_dir_out(d)       ((d) ? OHCI_ED_D_OUT : OHCI_ED_D_IN)
 148 #define OHCI_ED_EN      (0xf << 7)
 149 #define OHCI_ED_FA      (0x7f)
 150
 151
 152 #define ed_get_en(ed)   ((le32_to_cpup(&(ed)->status) & OHCI_ED_EN) >> 7)
 153 #define ed_get_fa(ed)   (le32_to_cpup(&(ed)->status) & OHCI_ED_FA)
 154
 155 /* NOTE: bits 27-31 of the status dword are reserved for the HCD */
 156 #define OHCI_ED_HCD_MASK        (0x1f << 27)
 157 /*
 158  * We'll use this status flag for to mark if an ED is in use by the
 159  * driver or not.  If the bit is set, it is being used.  (bit 31)
 160  */
 161 #define ED_ALLOCATED    (1 << 31)
 162 #define ed_allocated(ed)        (le32_to_cpup(&(ed).status) & ED_ALLOCATED)
 163 #define allocate_ed(ed)         ((ed)->status |= cpu_to_le32(ED_ALLOCATED))
 164
 165 /*
 166  * These store the endpoint transfer type for this ED in the status
 167  * field.  (bits 27 and 28)
 168  *   Bit 28:
 169  *     0 = Periodic ED
 170  *       Bit 27:
 171  *         0 = Isochronous
 172  *         1 = Interrupt
 173  *     1 = Normal ED
 174  *       Bit 27:
 175  *         0 = Control
 176  *         1 = Bulk
 177  */
 178 #define HCD_ED_NORMAL   (1 << 28)  /* (2 << 27) */
 179 #define HCD_ED_ISOC     (0)
 180 #define HCD_ED_INT      (1 << 27)
 181 #define HCD_ED_CONTROL  (2 << 27)
 182 #define HCD_ED_BULK     (3 << 27)
 183 #define HCD_ED_MASK     (3 << 27)
 184
 185 #define ohci_ed_hcdtype(ed)     (le32_to_cpup(&(ed)->status) & HCD_ED_MASK)
 186 #define ohci_ed_set_hcdtype(ed, t)      ( (ed)->status = ((ed)->status & ~cpu_to_le32(HCD_ED_MASK)) | cpu_to_le32((t) & HCD_ED_MASK) )
 187
 188
 189 /*
 190  * The HCCA (Host Controller Communications Area) is a 256 byte
 191  * structure defined in the OHCI spec. that the host controller is
 192  * told the base address of.  It must be 256-byte aligned.
 193  */
 194 #define NUM_INTS 32     /* part of the OHCI standard */
 195 struct ohci_hcca {
 196         __u32   int_table[NUM_INTS];    /* Interrupt ED table */
 197         __u16   frame_no;               /* current frame number */
 198         __u16   pad1;                   /* set to 0 on each frame_no change */
 199         __u32   donehead;               /* info returned for an interrupt */
 200         u8      reserved_for_hc[116];
 201 } __attribute((aligned(256)));
 202
 203 /*
 204  * The TD entries here are pre-allocated as Linus did with his simple
 205  * UHCI implementation.  With the current state of this driver that
 206  * shouldn't be a problem.  However if someone ever connects 127
 207  * supported devices to this driver and tries to use them all at once:
 208  *      a)  They're insane!
 209  *      b)  They should code in dynamic allocation
 210  */
 211 struct ohci;
 212
 213 /*
 214  *  Warning: These constants must not be so large as to cause the
 215  *  ohci_device structure to exceed one 4096 byte page.  Or "weird
 216  *  things will happen" as the alloc_ohci() function assumes that
 217  *  its less than one page.  (FIXME)
 218  */
 219 #define NUM_TDS 32              /* num of preallocated transfer descriptors */
 220 #define DATA_BUF_LEN 16         /* num of unsigned long's for the data buf */
 221
 222 /*
 223  * For this "simple" driver we only support a single ED for each
 224  * polling rate.
 225  *
 226  * Later on this driver should be extended to use a full tree of EDs
 227  * so that there can be 32 different 32ms polling frames, etc.
 228  * Individual devices shouldn't need as many as the root hub in that
 229  * case; complicating how things are done at the moment.
 230  *
 231  * Bulk and Control transfers hang off of their own ED lists.
 232  */
 233 #define NUM_EDS 16              /* num of preallocated endpoint descriptors */
 234
 235 #define ohci_to_usb(ohci)       ((ohci)->usb)
 236 #define usb_to_ohci(usb)        ((struct ohci_device *)(usb)->hcpriv)
 237
 238 /* The usb_device must be first! */
 239 struct ohci_device {
 240         struct usb_device       *usb;
 241
 242         struct ohci             *ohci;
 243         struct ohci_hcca        *hcca;          /* OHCI mem. mapped IO area */
 244
 245         struct ohci_ed          ed[NUM_EDS];    /* Endpoint Descriptors */
 246         struct ohci_td          td[NUM_TDS];    /* Transfer Descriptors */
 247
 248         unsigned long           data[DATA_BUF_LEN];
 249 } __attribute((aligned(32)));
 250
 251 /* .... */
 252
 253 /*
 254  * These are the index of the placeholder EDs for the root hub to
 255  * build the interrupt transfer ED tree out of.
 256  */
 257 #define ED_INT_1        0
 258 #define ED_INT_2        1
 259 #define ED_INT_4        2
 260 #define ED_INT_8        3
 261 #define ED_INT_16       4
 262 #define ED_INT_32       5
 263 #define ED_ISO          ED_INT_1        /* same as 1ms interrupt queue */
 264
 265 /*
 266  * Given a period p in ms, convert it to the closest endpoint
 267  * interrupt frequency; rounding down.  This is a gross macro.
 268  * Feel free to toss it for actual code. (gasp!)
 269  */
 270 #define ms_to_ed_int(p) \
 271         ((p >= 32) ? ED_INT_32 : \
 272          ((p & 16) ? ED_INT_16 : \
 273           ((p & 8) ? ED_INT_8 : \
 274            ((p & 4) ? ED_INT_4 : \
 275             ((p & 2) ? ED_INT_2 : \
 276              ED_INT_1)))))  /* hmm.. scheme or lisp anyone? */
 277
 278 /*
 279  * This is the maximum number of root hub ports.  I don't think we'll
 280  * ever see more than two as that's the space available on an ATX
 281  * motherboard's case, but it could happen.  The OHCI spec allows for
 282  * up to 15... (which is insane given that they each need to supply up
 283  * to 500ma; that would be 7.5 amps!).  I have seen a PCI card with 4
 284  * downstream ports on it.
 285  *
 286  * Although I suppose several "ports" could be connected directly to
 287  * internal laptop devices such as a keyboard, mouse, camera and
 288  * serial/parallel ports.  hmm...  That'd be neat.
 289  */
 290 #define MAX_ROOT_PORTS  15      /* maximum OHCI root hub ports */
 291
 292 /*
 293  * This is the structure of the OHCI controller's memory mapped I/O
 294  * region.  This is Memory Mapped I/O.  You must use the readl() and
 295  * writel() macros defined in asm/io.h to access these!!
 296  */
 297 struct ohci_regs {
 298         /* control and status registers */
 299         __u32   revision;
 300         __u32   control;
 301         __u32   cmdstatus;
 302         __u32   intrstatus;
 303         __u32   intrenable;
 304         __u32   intrdisable;
 305         /* memory pointers */
 306         __u32   hcca;
 307         __u32   ed_periodcurrent;
 308         __u32   ed_controlhead;
 309         __u32   ed_controlcurrent;
 310         __u32   ed_bulkhead;
 311         __u32   ed_bulkcurrent;
 312         __u32   current_donehead; /* The driver should get this from the HCCA */
 313         /* frame counters */
 314         __u32   fminterval;
 315         __u32   fmremaining;
 316         __u32   fmnumber;
 317         __u32   periodicstart;
 318         __u32   lsthresh;
 319         /* Root hub ports */
 320         struct  ohci_roothub_regs {
 321                 __u32   a;
 322                 __u32   b;
 323                 __u32   status;
 324                 __u32   portstatus[MAX_ROOT_PORTS];
 325         } roothub;
 326 } __attribute((aligned(32)));
 327
 328 /*
 329  * Read a MMIO register and re-write it after ANDing with (m)
 330  */
 331 #define writel_mask(m, a) writel( (readl((unsigned long)(a))) & (__u32)(m), (unsigned long)(a) )
 332
 333 /*
 334  * Read a MMIO register and re-write it after ORing with (b)
 335  */
 336 #define writel_set(b, a) writel( (readl((unsigned long)(a))) | (__u32)(b), (unsigned long)(a) )
 337
 338
 339 #define PORT_CCS        (1)             /* port current connect status */
 340 #define PORT_PES        (1 << 1)        /* port enable status */
 341 #define PORT_PSS        (1 << 2)        /* port suspend status */
 342 #define PORT_POCI       (1 << 3)        /* port overcurrent indicator */
 343 #define PORT_PRS        (1 << 4)        /* port reset status */
 344 #define PORT_PPS        (1 << 8)        /* port power status */
 345 #define PORT_LSDA       (1 << 9)        /* port low speed dev. attached */
 346 #define PORT_CSC        (1 << 16)       /* port connect status change */
 347 #define PORT_PESC       (1 << 17)       /* port enable status change */
 348 #define PORT_PSSC       (1 << 18)       /* port suspend status change */
 349 #define PORT_OCIC       (1 << 19)       /* port over current indicator chg */
 350 #define PORT_PRSC       (1 << 20)       /* port reset status change */
 351
 352 /*
 353  * Root Hub status register masks
 354  */
 355 #define OHCI_ROOT_LPS   (1)             /* turn off root hub ports power */
 356 #define OHCI_ROOT_OCI   (1 << 1)        /* Overcurrent Indicator */
 357 #define OHCI_ROOT_DRWE  (1 << 15)       /* Device remote wakeup enable */
 358 #define OHCI_ROOT_LPSC  (1 << 16)       /* turn on root hub ports power */
 359 #define OHCI_ROOT_OCIC  (1 << 17)       /* Overcurrent indicator change */
 360 #define OHCI_ROOT_CRWE  (1 << 31)       /* Clear RemoteWakeupEnable */
 361
 362 /*
 363  * Root hub A register masks
 364  */
 365 #define OHCI_ROOT_A_NPS (1 << 9)
 366 #define OHCI_ROOT_A_PSM (1 << 8)
 367
 368 /*
 369  * Root hub B register masks
 370  */
 371
 372 /*
 373  * Interrupt register masks
 374  */
 375 #define OHCI_INTR_SO    (1)
 376 #define OHCI_INTR_WDH   (1 << 1)
 377 #define OHCI_INTR_SF    (1 << 2)
 378 #define OHCI_INTR_RD    (1 << 3)
 379 #define OHCI_INTR_UE    (1 << 4)
 380 #define OHCI_INTR_FNO   (1 << 5)
 381 #define OHCI_INTR_RHSC  (1 << 6)
 382 #define OHCI_INTR_OC    (1 << 30)
 383 #define OHCI_INTR_MIE   (1 << 31)
 384
 385 /*
 386  * Control register masks
 387  */
 388 #define OHCI_USB_RESUME         (1 << 6)
 389 #define OHCI_USB_OPER           (2 << 6)
 390 #define OHCI_USB_SUSPEND        (3 << 6)
 391 #define OHCI_USB_PLE            (1 << 2)  /* Periodic (interrupt) list enable */
 392 #define OHCI_USB_IE             (1 << 3)  /* Isochronous list enable */
 393 #define OHCI_USB_CLE            (1 << 4)  /* Control list enable */
 394 #define OHCI_USB_BLE            (1 << 5)  /* Bulk list enable */
 395 #define OHCI_USB_IR             (1 << 8)  /* Int. Routing, HCD ownership */
 396 #define OHCI_USB_RWC            (1 << 9)  /* Remote Wakeup Connected */
 397 #define OHCI_USB_RWE            (1 << 10) /* Remote Wakeup Enable */
 398
 399 /*
 400  * Command status register masks
 401  */
 402 #define OHCI_CMDSTAT_HCR        (1)
 403 #define OHCI_CMDSTAT_CLF        (1 << 1)
 404 #define OHCI_CMDSTAT_BLF        (1 << 2)
 405 #define OHCI_CMDSTAT_OCR        (1 << 3)
 406 #define OHCI_CMDSTAT_SOC        (3 << 16)
 407
 408 /*
 409  * This is the full ohci controller description
 410  *
 411  * Note how the "proper" USB information is just
 412  * a subset of what the full implementation needs. (Linus)
 413  */
 414 struct ohci {
 415         int irq;
 416         struct ohci_regs *regs;                 /* OHCI controller's memory */
 417         struct usb_bus *bus;
 418         struct ohci_device *root_hub;           /* Root hub & controller */
 419         struct list_head interrupt_list;        /* List of interrupt active TDs for this OHCI */
 420 };
 421
 422 #define OHCI_TIMER              /* enable the OHCI timer */
 423 #define OHCI_TIMER_FREQ (234)   /* ms between each root hub status check */
 424
 425 #undef OHCI_RHSC_INT            /* Don't use root hub status interrupts! */
 426
 427 /* Debugging code [ohci-debug.c] */
 428 void show_ohci_ed(struct ohci_ed *ed);
 429 void show_ohci_td(struct ohci_td *td);
 430 void show_ohci_td_chain(struct ohci_td *td);
 431 void show_ohci_status(struct ohci *ohci);
 432 void show_ohci_device(struct ohci_device *dev);
 433 void show_ohci_hcca(struct ohci_hcca *hcca);
 434
 435 #endif
 436 /* vim:sw=8
 437  */