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Import 2.3.25pre1
[davej-history.git] / drivers / block / ide-pci.c
blob73ffa67ea7b1f85c7a1e0da538ffb34e6903817c
1 /*
2 * linux/drivers/block/ide-pci.c Version 1.04 July 27, 1999
3 *
4 * Copyright (c) 1998-1999 Andre Hedrick
5 *
6 * Copyright (c) 1995-1998 Mark Lord
7 * May be copied or modified under the terms of the GNU General Public License
8 */
9
10 /*
11 * This module provides support for automatic detection and
12 * configuration of all PCI IDE interfaces present in a system.
13 */
14
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/timer.h>
19 #include <linux/mm.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/ide.h>
24
25 #include <asm/io.h>
26 #include <asm/irq.h>
27
28 #define DEVID_PIIXa ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0})
29 #define DEVID_PIIXb ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1})
30 #define DEVID_PIIX3 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1})
31 #define DEVID_PIIX4 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB})
32 #define DEVID_VIA_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561})
33 #define DEVID_VP_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1})
34 #define DEVID_PDC20246 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246})
35 #define DEVID_PDC20262 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262})
36 #define DEVID_RZ1000 ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1000})
37 #define DEVID_RZ1001 ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1001})
38 #define DEVID_SAMURAI ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE})
39 #define DEVID_CMD640 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_640})
40 #define DEVID_CMD643 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643})
41 #define DEVID_CMD646 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646})
42 #define DEVID_SIS5513 ((ide_pci_devid_t){PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513})
43 #define DEVID_OPTI621 ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C621})
44 #define DEVID_OPTI621V ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558})
45 #define DEVID_OPTI621X ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C825})
46 #define DEVID_TRM290 ((ide_pci_devid_t){PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290})
47 #define DEVID_NS87410 ((ide_pci_devid_t){PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87410})
48 #define DEVID_NS87415 ((ide_pci_devid_t){PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415})
49 #define DEVID_HT6565 ((ide_pci_devid_t){PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565})
50 #define DEVID_AEC6210 ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF})
51 #define DEVID_W82C105 ((ide_pci_devid_t){PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105})
52 #define DEVID_UM8886A ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A})
53 #define DEVID_UM8886BF ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF})
54 #define DEVID_HPT34X ((ide_pci_devid_t){PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343})
55 #define DEVID_HPT366 ((ide_pci_devid_t){PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366})
56 #define DEVID_ALI15X3 ((ide_pci_devid_t){PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229})
57 #define DEVID_CY82C693 ((ide_pci_devid_t){PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693})
58 #define DEVID_HINT ((ide_pci_devid_t){0x3388, 0x8013})
59 #define DEVID_CX5530 ((ide_pci_devid_t){PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE})
60 #define DEVID_AMD7409 ((ide_pci_devid_t){PCI_VENDOR_ID_AMD, 0x7409})
61
62 #define IDE_IGNORE ((void *)-1)
63
64 #ifdef CONFIG_BLK_DEV_TRM290
65 extern void ide_init_trm290(ide_hwif_t *);
66 #define INIT_TRM290 &ide_init_trm290
67 #else
68 #define INIT_TRM290 IDE_IGNORE
69 #endif
70
71 #ifdef CONFIG_BLK_DEV_OPTI621
72 extern void ide_init_opti621(ide_hwif_t *);
73 #define INIT_OPTI621 &ide_init_opti621
74 #else
75 #define INIT_OPTI621 NULL
76 #endif
77
78 #ifdef CONFIG_BLK_DEV_NS87415
79 extern void ide_init_ns87415(ide_hwif_t *);
80 #define INIT_NS87415 &ide_init_ns87415
81 #else
82 #define INIT_NS87415 IDE_IGNORE
83 #endif
84
85 #ifdef CONFIG_BLK_DEV_CMD646
86 extern void ide_init_cmd646(ide_hwif_t *);
87 #define INIT_CMD646 &ide_init_cmd646
88 #else
89 #ifdef __sparc_v9__
90 #define INIT_CMD646 IDE_IGNORE
91 #else
92 #define INIT_CMD646 NULL
93 #endif
94 #endif
95
96 #ifdef CONFIG_BLK_DEV_SL82C105
97 extern void ide_init_sl82c105(ide_hwif_t *);
98 #define INIT_W82C105 &ide_init_sl82c105
99 #else
100 #define INIT_W82C105 IDE_IGNORE
101 #endif
102
103 #ifdef CONFIG_BLK_DEV_RZ1000
104 extern void ide_init_rz1000(ide_hwif_t *);
105 #define INIT_RZ1000 &ide_init_rz1000
106 #else
107 #define INIT_RZ1000 IDE_IGNORE
108 #endif
109
110 #ifdef CONFIG_BLK_DEV_VIA82CXXX
111 extern unsigned int pci_init_via82cxxx(struct pci_dev *, const char *);
112 extern unsigned int ata66_via82cxxx(ide_hwif_t *);
113 extern void ide_init_via82cxxx(ide_hwif_t *);
114 extern void ide_dmacapable_via82cxxx(ide_hwif_t *, unsigned long);
115 #define PCI_VIA82CXXX &pci_init_via82cxxx
116 #define ATA66_VIA82CXXX &ata66_via82cxxx
117 #define INIT_VIA82CXXX &ide_init_via82cxxx
118 #define DMA_VIA82CXXX &ide_dmacapable_via82cxxx
119 #else
120 #define PCI_VIA82CXXX NULL
121 #define ATA66_VIA82CXXX NULL
122 #define INIT_VIA82CXXX NULL
123 #define DMA_VIA82CXXX NULL
124 #endif
125
126 #ifdef CONFIG_BLK_DEV_ALI15X3
127 extern unsigned int pci_init_ali15x3(struct pci_dev *, const char *);
128 extern unsigned int ata66_ali15x3(ide_hwif_t *);
129 extern void ide_init_ali15x3(ide_hwif_t *);
130 extern void ide_dmacapable_ali15x3(ide_hwif_t *, unsigned long);
131 #define PCI_ALI15X3 &pci_init_ali15x3
132 #define ATA66_ALI15X3 &ata66_ali15x3
133 #define INIT_ALI15X3 &ide_init_ali15x3
134 #define DMA_ALI15X3 &ide_dmacapable_ali15x3
135 #else
136 #define PCI_ALI15X3 NULL
137 #define ATA66_ALI15X3 NULL
138 #define INIT_ALI15X3 NULL
139 #define DMA_ALI15X3 NULL
140 #endif
141
142 #ifdef CONFIG_BLK_DEV_CY82C693
143 extern unsigned int pci_init_cy82c693(struct pci_dev *, const char *);
144 extern void ide_init_cy82c693(ide_hwif_t *);
145 #define PCI_CY82C693 &pci_init_cy82c693
146 #define INIT_CY82C693 &ide_init_cy82c693
147 #else
148 #define PCI_CY82C693 NULL
149 #define INIT_CY82C693 NULL
150 #endif
151
152 #ifdef CONFIG_BLK_DEV_PDC202XX
153 extern unsigned int pci_init_pdc202xx(struct pci_dev *, const char *);
154 extern unsigned int ata66_pdc202xx(ide_hwif_t *);
155 extern void ide_init_pdc202xx(ide_hwif_t *);
156 #define PCI_PDC202XX &pci_init_pdc202xx
157 #define ATA66_PDC202XX &ata66_pdc202xx
158 #define INIT_PDC202XX &ide_init_pdc202xx
159 #else
160 #define PCI_PDC202XX NULL
161 #define ATA66_PDC202XX NULL
162 #define INIT_PDC202XX NULL
163 #endif
164
165 #ifdef CONFIG_BLK_DEV_PIIX
166 extern void ide_init_piix(ide_hwif_t *);
167 #define INIT_PIIX &ide_init_piix
168 #else
169 #define INIT_PIIX NULL
170 #endif
171
172 #ifdef CONFIG_BLK_DEV_AEC6210
173 extern unsigned int pci_init_aec6210(struct pci_dev *, const char *);
174 #define PCI_AEC6210 &pci_init_aec6210
175 #else
176 #define PCI_AEC6210 NULL
177 #endif
178
179 #ifdef CONFIG_BLK_DEV_HPT34X
180 extern unsigned int pci_init_hpt34x(struct pci_dev *, const char *);
181 extern void ide_init_hpt34x(ide_hwif_t *);
182 #define PCI_HPT34X &pci_init_hpt34x
183 #define INIT_HPT34X &ide_init_hpt34x
184 #else
185 #define PCI_HPT34X NULL
186 #define INIT_HPT34X NULL
187 #endif
188
189 #ifdef CONFIG_BLK_DEV_HPT366
190 extern byte hpt363_shared_irq;
191 extern unsigned int pci_init_hpt366(struct pci_dev *, const char *);
192 extern unsigned int ata66_hpt366(ide_hwif_t *);
193 extern void ide_init_hpt366(ide_hwif_t *);
194 extern void ide_dmacapable_hpt366(ide_hwif_t *, unsigned long);
195 #define PCI_HPT366 &pci_init_hpt366
196 #define ATA66_HPT366 &ata66_hpt366
197 #define INIT_HPT366 &ide_init_hpt366
198 #define DMA_HPT366 &ide_dmacapable_hpt366
199 #else
200 static byte hpt363_shared_irq = 0;
201 #define PCI_HPT366 NULL
202 #define ATA66_HPT366 NULL
203 #define INIT_HPT366 NULL
204 #define DMA_HPT366 NULL
205 #endif
206
207 #ifdef CONFIG_BLK_DEV_SIS5513
208 extern unsigned int pci_init_sis5513(struct pci_dev *, const char *);
209 extern unsigned int ata66_sis5513(ide_hwif_t *);
210 extern void ide_init_sis5513(ide_hwif_t *);
211 #define PCI_SIS5513 &pci_init_sis5513
212 #define ATA66_SIS5513 &ata66_sis5513
213 #define INIT_SIS5513 &ide_init_sis5513
214 #else
215 #define PCI_SIS5513 NULL
216 #define ATA66_SIS5513 NULL
217 #define INIT_SIS5513 NULL
218 #endif
219
220 #define INIT_SAMURAI NULL
221 #define INIT_CX5530 NULL
222
223 typedef struct ide_pci_enablebit_s {
224 byte reg; /* byte pci reg holding the enable-bit */
225 byte mask; /* mask to isolate the enable-bit */
226 byte val; /* value of masked reg when "enabled" */
227 } ide_pci_enablebit_t;
228
229 typedef struct ide_pci_device_s {
230 ide_pci_devid_t devid;
231 const char *name;
232 unsigned int (*init_chipset)(struct pci_dev *dev, const char *name);
233 unsigned int (*ata66_check)(ide_hwif_t *hwif);
234 void (*init_hwif)(ide_hwif_t *hwif);
235 void (*dma_init)(ide_hwif_t *hwif, unsigned long dmabase);
236 ide_pci_enablebit_t enablebits[2];
237 byte bootable;
238 unsigned int extra;
239 } ide_pci_device_t;
240
241 static ide_pci_device_t ide_pci_chipsets[] __initdata = {
242 {DEVID_PIIXa, "PIIX", NULL, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
243 {DEVID_PIIXb, "PIIX", NULL, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
244 {DEVID_PIIX3, "PIIX3", NULL, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
245 {DEVID_PIIX4, "PIIX4", NULL, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
246 {DEVID_VIA_IDE, "VIA_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
247 {DEVID_VP_IDE, "VP_IDE", PCI_VIA82CXXX, ATA66_VIA82CXXX,INIT_VIA82CXXX, DMA_VIA82CXXX, {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, ON_BOARD, 0 },
248 {DEVID_PDC20246,"PDC20246", PCI_PDC202XX, NULL, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 16 },
249 {DEVID_PDC20262,"PDC20262", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48 },
250 {DEVID_RZ1000, "RZ1000", NULL, NULL, INIT_RZ1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
251 {DEVID_RZ1001, "RZ1001", NULL, NULL, INIT_RZ1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
252 {DEVID_SAMURAI, "SAMURAI", NULL, NULL, INIT_SAMURAI, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
253 {DEVID_CMD640, "CMD640", NULL, NULL, IDE_IGNORE, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
254 {DEVID_NS87410, "NS87410", NULL, NULL, NULL, NULL, {{0x43,0x08,0x08}, {0x47,0x08,0x08}}, ON_BOARD, 0 },
255 {DEVID_SIS5513, "SIS5513", PCI_SIS5513, ATA66_SIS5513, INIT_SIS5513, NULL, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, ON_BOARD, 0 },
256 {DEVID_CMD643, "CMD643", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
257 {DEVID_CMD646, "CMD646", NULL, NULL, INIT_CMD646, NULL, {{0x00,0x00,0x00}, {0x51,0x80,0x80}}, ON_BOARD, 0 },
258 {DEVID_HT6565, "HT6565", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
259 {DEVID_OPTI621, "OPTI621", NULL, NULL, INIT_OPTI621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0 },
260 {DEVID_OPTI621X,"OPTI621X", NULL, NULL, INIT_OPTI621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0 },
261 {DEVID_TRM290, "TRM290", NULL, NULL, INIT_TRM290, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
262 {DEVID_NS87415, "NS87415", NULL, NULL, INIT_NS87415, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
263 {DEVID_AEC6210, "AEC6210", PCI_AEC6210, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 },
264 {DEVID_W82C105, "W82C105", NULL, NULL, INIT_W82C105, NULL, {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, ON_BOARD, 0 },
265 {DEVID_UM8886A, "UM8886A", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
266 {DEVID_UM8886BF,"UM8886BF", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
267 {DEVID_HPT34X, "HPT34X", PCI_HPT34X, NULL, INIT_HPT34X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, NEVER_BOARD, 16 },
268 {DEVID_HPT366, "HPT366", PCI_HPT366, ATA66_HPT366, INIT_HPT366, DMA_HPT366, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 256 },
269 {DEVID_ALI15X3, "ALI15X3", PCI_ALI15X3, ATA66_ALI15X3, INIT_ALI15X3, DMA_ALI15X3, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
270 {DEVID_CY82C693,"CY82C693", PCI_CY82C693, NULL, INIT_CY82C693, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
271 {DEVID_HINT, "HINT_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
272 {DEVID_CX5530, "CX5530", NULL, NULL, INIT_CX5530, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
273 {DEVID_AMD7409, "AMD7409", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
274 {IDE_PCI_DEVID_NULL, "PCI_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }};
275
276 /*
277 * This allows offboard ide-pci cards the enable a BIOS, verify interrupt
278 * settings of split-mirror pci-config space, place chipset into init-mode,
279 * and/or preserve an interrupt if the card is not native ide support.
280 */
281 static unsigned int __init ide_special_settings (struct pci_dev *dev, const char *name)
282 {
283 switch(dev->device) {
284 case PCI_DEVICE_ID_TTI_HPT343:
285 {
286 int i;
287 unsigned long hpt34xIoBase = dev->resource[4].start;
288 unsigned short pcicmd = 0;
289
290 pci_write_config_byte(dev, 0x80, 0x00);
291 pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
292 if (!(pcicmd & PCI_COMMAND_MEMORY)) {
293 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
294 } else {
295 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
296 }
297
298 dev->resource[0].start = (hpt34xIoBase + 0x20);
299 dev->resource[1].start = (hpt34xIoBase + 0x34);
300 dev->resource[2].start = (hpt34xIoBase + 0x28);
301 dev->resource[3].start = (hpt34xIoBase + 0x3c);
302 for(i=0; i<4; i++)
303 dev->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
304 }
305 case PCI_DEVICE_ID_TTI_HPT366:
306 case PCI_DEVICE_ID_PROMISE_20246:
307 case PCI_DEVICE_ID_PROMISE_20262:
308 case PCI_DEVICE_ID_ARTOP_ATP850UF:
309 return dev->irq;
310 default:
311 break;
312 }
313 return 0;
314 }
315
316 /*
317 * Match a PCI IDE port against an entry in ide_hwifs[],
318 * based on io_base port if possible.
319 */
320 static ide_hwif_t __init *ide_match_hwif (unsigned long io_base, byte bootable, const char *name)
321 {
322 int h;
323 ide_hwif_t *hwif;
324
325 /*
326 * Look for a hwif with matching io_base specified using
327 * parameters to ide_setup().
328 */
329 for (h = 0; h < MAX_HWIFS; ++h) {
330 hwif = &ide_hwifs[h];
331 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
332 if (hwif->chipset == ide_generic)
333 return hwif; /* a perfect match */
334 }
335 }
336 /*
337 * Look for a hwif with matching io_base default value.
338 * If chipset is "ide_unknown", then claim that hwif slot.
339 * Otherwise, some other chipset has already claimed it.. :(
340 */
341 for (h = 0; h < MAX_HWIFS; ++h) {
342 hwif = &ide_hwifs[h];
343 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
344 if (hwif->chipset == ide_unknown)
345 return hwif; /* match */
346 printk("%s: port 0x%04lx already claimed by %s\n", name, io_base, hwif->name);
347 return NULL; /* already claimed */
348 }
349 }
350 /*
351 * Okay, there is no hwif matching our io_base,
352 * so we'll just claim an unassigned slot.
353 * Give preference to claiming other slots before claiming ide0/ide1,
354 * just in case there's another interface yet-to-be-scanned
355 * which uses ports 1f0/170 (the ide0/ide1 defaults).
356 *
357 * Unless there is a bootable card that does not use the standard
358 * ports 1f0/170 (the ide0/ide1 defaults). The (bootable) flag.
359 */
360 if (bootable) {
361 for (h = 0; h < MAX_HWIFS; ++h) {
362 hwif = &ide_hwifs[h];
363 if (hwif->chipset == ide_unknown)
364 return hwif; /* pick an unused entry */
365 }
366 } else {
367 for (h = 2; h < MAX_HWIFS; ++h) {
368 hwif = ide_hwifs + h;
369 if (hwif->chipset == ide_unknown)
370 return hwif; /* pick an unused entry */
371 }
372 }
373 for (h = 0; h < 2; ++h) {
374 hwif = ide_hwifs + h;
375 if (hwif->chipset == ide_unknown)
376 return hwif; /* pick an unused entry */
377 }
378 printk("%s: too many IDE interfaces, no room in table\n", name);
379 return NULL;
380 }
381
382 static int __init ide_setup_pci_baseregs (struct pci_dev *dev, const char *name)
383 {
384 byte reg, progif = 0;
385
386 /*
387 * Place both IDE interfaces into PCI "native" mode:
388 */
389 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) {
390 if ((progif & 0xa) != 0xa) {
391 printk("%s: device not capable of full native PCI mode\n", name);
392 return 1;
393 }
394 printk("%s: placing both ports into native PCI mode\n", name);
395 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
396 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) {
397 printk("%s: rewrite of PROGIF failed, wanted 0x%04x, got 0x%04x\n", name, progif|5, progif);
398 return 1;
399 }
400 }
401 /*
402 * Setup base registers for IDE command/control spaces for each interface:
403 */
404 for (reg = 0; reg < 4; reg++) {
405 struct resource *res = dev->resource + reg;
406 if (!(res->flags & PCI_BASE_ADDRESS_SPACE_IO))
407 continue;
408 if (!res->start) {
409 printk("%s: Missing I/O address #%d\n", name, reg);
410 return 1;
411 }
412 }
413 return 0;
414 }
415
416 /*
417 * ide_setup_pci_device() looks at the primary/secondary interfaces
418 * on a PCI IDE device and, if they are enabled, prepares the IDE driver
419 * for use with them. This generic code works for most PCI chipsets.
420 *
421 * One thing that is not standardized is the location of the
422 * primary/secondary interface "enable/disable" bits. For chipsets that
423 * we "know" about, this information is in the ide_pci_device_t struct;
424 * for all other chipsets, we just assume both interfaces are enabled.
425 */
426 static void __init ide_setup_pci_device (struct pci_dev *dev, ide_pci_device_t *d)
427 {
428 unsigned int port, at_least_one_hwif_enabled = 0, autodma = 0, pciirq = 0;
429 unsigned short pcicmd = 0, tried_config = 0;
430 byte tmp = 0;
431 ide_hwif_t *hwif, *mate = NULL;
432
433 #ifdef CONFIG_IDEDMA_AUTO
434 autodma = 1;
435 #endif
436 check_if_enabled:
437 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) {
438 printk("%s: error accessing PCI regs\n", d->name);
439 return;
440 }
441 if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */
442 /*
443 * PnP BIOS was *supposed* to have set this device up for us,
444 * but we can do it ourselves, so long as the BIOS has assigned an IRQ
445 * (or possibly the device is using a "legacy header" for IRQs).
446 * Maybe the user deliberately *disabled* the device,
447 * but we'll eventually ignore it again if no drives respond.
448 */
449 if (tried_config++
450 || ide_setup_pci_baseregs(dev, d->name)
451 || pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) {
452 printk("%s: device disabled (BIOS)\n", d->name);
453 return;
454 }
455 autodma = 0; /* default DMA off if we had to configure it here */
456 goto check_if_enabled;
457 }
458 if (tried_config)
459 printk("%s: device enabled (Linux)\n", d->name);
460 /*
461 * Can we trust the reported IRQ?
462 */
463 pciirq = dev->irq;
464 if ((dev->class & ~(0xfa)) != ((PCI_CLASS_STORAGE_IDE << 8) | 5)) {
465 printk("%s: not 100%% native mode: will probe irqs later\n", d->name);
466 /*
467 * This allows offboard ide-pci cards the enable a BIOS,
468 * verify interrupt settings of split-mirror pci-config
469 * space, place chipset into init-mode, and/or preserve
470 * an interrupt if the card is not native ide support.
471 */
472 pciirq = (d->init_chipset) ? d->init_chipset(dev, d->name) : ide_special_settings(dev, d->name);
473 } else if (tried_config) {
474 printk("%s: will probe irqs later\n", d->name);
475 pciirq = 0;
476 } else if (!pciirq) {
477 printk("%s: bad irq (%d): will probe later\n", d->name, pciirq);
478 pciirq = 0;
479 } else {
480 #ifdef __sparc__
481 printk("%s: 100%% native mode on irq %s\n",
482 d->name, __irq_itoa(pciirq));
483 #else
484 printk("%s: 100%% native mode on irq %d\n", d->name, pciirq);
485 #endif
486 }
487 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X)) {
488 /*
489 * Since there are two cards that report almost identically,
490 * the only discernable difference is the values
491 * reported in pcicmd.
492 * Booting-BIOS card or HPT363 :: pcicmd == 0x07
493 * Non-bootable card or HPT343 :: pcicmd == 0x05
494 */
495 if (pcicmd & PCI_COMMAND_MEMORY) {
496 printk("%s: is IDE Express HPT363.\n", d->name);
497 d->bootable = OFF_BOARD;
498 }
499 }
500 /*
501 * Set up the IDE ports
502 */
503 for (port = 0; port <= 1; ++port) {
504 unsigned long base = 0, ctl = 0;
505 ide_pci_enablebit_t *e = &(d->enablebits[port]);
506 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || (tmp & e->mask) != e->val))
507 continue; /* port not enabled */
508 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) && (port))
509 return;
510 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE || (dev->class & (port ? 4 : 1)) != 0) {
511 ctl = dev->resource[(2*port)+1].start;
512 base = dev->resource[2*port].start;
513 if (!(ctl & PCI_BASE_ADDRESS_IO_MASK) ||
514 !(base & PCI_BASE_ADDRESS_IO_MASK)) {
515 printk("%s: IO baseregs (BIOS) are reported as MEM, report to <andre@suse.com>.\n", d->name);
516 #if 0
517 /* FIXME! This really should check that it really gets the IO/MEM part right! */
518 continue;
519 #endif
520 }
521 }
522 if ((ctl && !base) || (base && !ctl)) {
523 printk("%s: inconsistent baseregs (BIOS) for port %d, skipping\n", d->name, port);
524 continue;
525 }
526 if (!ctl)
527 ctl = port ? 0x374 : 0x3f4; /* use default value */
528 if (!base)
529 base = port ? 0x170 : 0x1f0; /* use default value */
530 if ((hwif = ide_match_hwif(base, d->bootable, d->name)) == NULL)
531 continue; /* no room in ide_hwifs[] */
532 if (hwif->io_ports[IDE_DATA_OFFSET] != base) {
533 ide_init_hwif_ports(&hwif->hw, base, (ctl | 2), NULL);
534 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
535 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
536 }
537 hwif->chipset = ide_pci;
538 hwif->pci_dev = dev;
539 hwif->pci_devid = d->devid;
540 hwif->channel = port;
541 if (!hwif->irq)
542 hwif->irq = pciirq;
543 if (mate) {
544 hwif->mate = mate;
545 mate->mate = hwif;
546 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210)) {
547 hwif->serialized = 1;
548 mate->serialized = 1;
549 }
550 }
551 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) ||
552 IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886BF)) {
553 hwif->irq = hwif->channel ? 15 : 14;
554 goto bypass_umc_dma;
555 }
556 hwif->udma_four = (d->ata66_check) ? d->ata66_check(hwif) : 0;
557 #ifdef CONFIG_BLK_DEV_IDEDMA
558 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_SIS5513) ||
559 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X))
560 autodma = 0;
561 if (autodma)
562 hwif->autodma = 1;
563 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20246) ||
564 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20262) ||
565 IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210) ||
566 #ifdef CONFIG_BLK_DEV_HPT34X
567 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X) ||
568 #endif /* CONFIG_BLK_DEV_HPT34X */
569 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) ||
570 IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) ||
571 ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 0x80))) {
572 unsigned long dma_base = ide_get_or_set_dma_base(hwif, (!mate && d->extra) ? d->extra : 0, d->name);
573 if (dma_base && !(pcicmd & PCI_COMMAND_MASTER)) {
574 /*
575 * Set up BM-DMA capability (PnP BIOS should have done this)
576 */
577 hwif->autodma = 0; /* default DMA off if we had to configure it here */
578 (void) pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_MASTER);
579 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || !(pcicmd & PCI_COMMAND_MASTER)) {
580 printk("%s: %s error updating PCICMD\n", hwif->name, d->name);
581 dma_base = 0;
582 }
583 }
584 if (dma_base) {
585 if (d->dma_init) {
586 d->dma_init(hwif, dma_base);
587 } else {
588 ide_setup_dma(hwif, dma_base, 8);
589 }
590 } else {
591 printk("%s: %s Bus-Master DMA disabled (BIOS)\n", hwif->name, d->name);
592 }
593 }
594 #endif /* CONFIG_BLK_DEV_IDEDMA */
595 bypass_umc_dma:
596 if (d->init_hwif) /* Call chipset-specific routine for each enabled hwif */
597 d->init_hwif(hwif);
598 mate = hwif;
599 at_least_one_hwif_enabled = 1;
600 }
601 if (!at_least_one_hwif_enabled)
602 printk("%s: neither IDE port enabled (BIOS)\n", d->name);
603 }
604
605 static void __init hpt366_device_order_fixup (struct pci_dev *dev, ide_pci_device_t *d)
606 {
607 struct pci_dev *dev2 = NULL, *findev;
608 ide_pci_device_t *d2;
609 unsigned char pin1 = 0, pin2 = 0;
610
611 if (PCI_FUNC(dev->devfn) & 1)
612 return;
613 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
614 for (findev=pci_devices; findev; findev=findev->next) {
615 if ((findev->vendor == dev->vendor) &&
616 (findev->device == dev->device) &&
617 ((findev->devfn - dev->devfn) == 1) &&
618 (PCI_FUNC(findev->devfn) & 1)) {
619 dev2 = findev;
620 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
621 hpt363_shared_irq = (pin1 != pin2) ? 1 : 0;
622 if (hpt363_shared_irq) {
623 d->bootable = ON_BOARD;
624 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n", d->name, pin1, pin2);
625 }
626 break;
627 }
628 }
629 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d->name, dev->bus->number, dev->devfn);
630 ide_setup_pci_device(dev, d);
631 if (!dev2)
632 return;
633 d2 = d;
634 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d2->name, dev2->bus->number, dev2->devfn);
635 ide_setup_pci_device(dev2, d2);
636 }
637
638 /*
639 * ide_scan_pcibus() gets invoked at boot time from ide.c.
640 * It finds all PCI IDE controllers and calls ide_setup_pci_device for them.
641 */
642 void __init ide_scan_pcibus (void)
643 {
644 struct pci_dev *dev;
645 ide_pci_devid_t devid;
646 ide_pci_device_t *d;
647
648 if (!pci_present())
649 return;
650 for(dev = pci_devices; dev; dev=dev->next) {
651 devid.vid = dev->vendor;
652 devid.did = dev->device;
653 for (d = ide_pci_chipsets; d->devid.vid && !IDE_PCI_DEVID_EQ(d->devid, devid); ++d);
654 if (d->init_hwif == IDE_IGNORE)
655 printk("%s: ignored by ide_scan_pci_device() (uses own driver)\n", d->name);
656 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_OPTI621V) && !(PCI_FUNC(dev->devfn) & 1))
657 continue; /* OPTI Viper-M uses same devid for functions 0 and 1 */
658 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) && (!(PCI_FUNC(dev->devfn) & 1) || !((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)))
659 continue; /* CY82C693 is more than only a IDE controller */
660 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) && !(PCI_FUNC(dev->devfn) & 1))
661 continue; /* UM8886A/BF pair */
662 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366))
663 hpt366_device_order_fixup(dev, d);
664 else if (!IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL) || (dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
665 if (IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL))
666 printk("%s: unknown IDE controller on PCI bus %02x device %02x, VID=%04x, DID=%04x\n",
667 d->name, dev->bus->number, dev->devfn, devid.vid, devid.did);
668 else
669 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d->name, dev->bus->number, dev->devfn);
670 ide_setup_pci_device(dev, d);
671 }
672 }
673 }
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