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Import 2.3.25pre1
[davej-history.git] / drivers / block / alim15x3.c
blob5453610523a9e58723b4f017368b65182fa91056
1 /*
2 * linux/drivers/block/alim15x3.c Version 0.06 Sept. 3, 1999
3 *
4 * Copyright (C) 1998-99 Michel Aubry, Maintainer
5 * Copyright (C) 1998-99 Andrzej Krzysztofowicz, Maintainer
6 *
7 * Copyright (C) 1998-99 Andre Hedrick (andre@suse.com)
8 * May be copied or modified under the terms of the GNU General Public License
9 *
10 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
11 *
12 * version: 1.0 beta2 (Sep. 2, 1999)
13 * e-mail your problems to cjtsai@ali.com.tw
14 *
15 **********************************************************************
16 * 9/7/99 --Parts from the above author are included and need to be
17 * converted into standard interface, once I finish the thought.
18 */
19
20 #include <linux/config.h>
21 #include <linux/types.h>
22 #include <linux/kernel.h>
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <linux/hdreg.h>
26 #include <linux/ide.h>
27
28 #include <asm/io.h>
29
30 #include "ide_modes.h"
31
32 #define DISPLAY_ALI_TIMINGS
33
34 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
35 #include <linux/stat.h>
36 #include <linux/proc_fs.h>
37
38 static int ali_get_info(char *buffer, char **addr, off_t offset, int count, int dummy);
39 extern int (*ali_display_info)(char *, char **, off_t, int, int); /* ide-proc.c */
40 struct pci_dev *bmide_dev;
41
42 char *fifo[4] = {
43 "FIFO Off",
44 "FIFO On ",
45 "DMA mode",
46 "PIO mode" };
47
48 char *udmaT[8] = {
49 "1.5T",
50 " 2T",
51 "2.5T",
52 " 3T",
53 "3.5T",
54 " 4T",
55 " 6T",
56 " 8T"
57 };
58
59 char *channel_status[8] = {
60 "OK ",
61 "busy ",
62 "DRQ ",
63 "DRQ busy ",
64 "error ",
65 "error busy ",
66 "error DRQ ",
67 "error DRQ busy"
68 };
69
70 static int ali_get_info(char *buffer, char **addr, off_t offset, int count, int dummy)
71 {
72 byte reg53h, reg5xh, reg5yh, reg5xh1, reg5yh1;
73 unsigned int bibma;
74 byte c0, c1;
75 byte rev, tmp;
76 char *p = buffer;
77 char *q;
78
79 /* fetch rev. */
80 pci_read_config_byte(bmide_dev, 0x08, &rev);
81 if (rev >= 0xc1) /* M1543C or newer */
82 udmaT[7] = " ???";
83 else
84 fifo[3] = " ??? ";
85
86 /* first fetch bibma: */
87 pci_read_config_dword(bmide_dev, 0x20, &bibma);
88 bibma = (bibma & 0xfff0) ;
89 /*
90 * at that point bibma+0x2 et bibma+0xa are byte
91 * registers to investigate:
92 */
93 c0 = inb((unsigned short)bibma + 0x02);
94 c1 = inb((unsigned short)bibma + 0x0a);
95
96 p += sprintf(p,
97 "\n Ali M15x3 Chipset.\n");
98 p += sprintf(p,
99 " ------------------\n");
100 pci_read_config_byte(bmide_dev, 0x78, &reg53h);
101 p += sprintf(p, "PCI Clock: %d.\n", reg53h);
102
103 pci_read_config_byte(bmide_dev, 0x53, &reg53h);
104 p += sprintf(p,
105 "CD_ROM FIFO:%s, CD_ROM DMA:%s\n",
106 (reg53h & 0x02) ? "Yes" : "No ",
107 (reg53h & 0x01) ? "Yes" : "No " );
108 pci_read_config_byte(bmide_dev, 0x74, &reg53h);
109 p += sprintf(p,
110 "FIFO Status: contains %d Words, runs%s%s\n\n",
111 (reg53h & 0x3f),
112 (reg53h & 0x40) ? " OVERWR" : "",
113 (reg53h & 0x80) ? " OVERRD." : "." );
114
115 p += sprintf(p,
116 "-------------------primary channel-------------------secondary channel---------\n\n");
117
118 pci_read_config_byte(bmide_dev, 0x09, &reg53h);
119 p += sprintf(p,
120 "channel status: %s %s\n",
121 (reg53h & 0x20) ? "On " : "Off",
122 (reg53h & 0x10) ? "On " : "Off" );
123
124 p += sprintf(p,
125 "both channels togth: %s %s\n",
126 (c0&0x80) ? "No " : "Yes",
127 (c1&0x80) ? "No " : "Yes" );
128
129 pci_read_config_byte(bmide_dev, 0x76, &reg53h);
130 p += sprintf(p,
131 "Channel state: %s %s\n",
132 channel_status[reg53h & 0x07],
133 channel_status[(reg53h & 0x70) >> 4] );
134
135 pci_read_config_byte(bmide_dev, 0x58, &reg5xh);
136 pci_read_config_byte(bmide_dev, 0x5c, &reg5yh);
137 p += sprintf(p,
138 "Add. Setup Timing: %dT %dT\n",
139 (reg5xh & 0x07) ? (reg5xh & 0x07) : 8,
140 (reg5yh & 0x07) ? (reg5yh & 0x07) : 8 );
141
142 pci_read_config_byte(bmide_dev, 0x59, &reg5xh);
143 pci_read_config_byte(bmide_dev, 0x5d, &reg5yh);
144 p += sprintf(p,
145 "Command Act. Count: %dT %dT\n"
146 "Command Rec. Count: %dT %dT\n\n",
147 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
148 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
149 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
150 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16 );
151
152 p += sprintf(p,
153 "----------------drive0-----------drive1------------drive0-----------drive1------\n\n");
154 p += sprintf(p,
155 "DMA enabled: %s %s %s %s\n",
156 (c0&0x20) ? "Yes" : "No ",
157 (c0&0x40) ? "Yes" : "No ",
158 (c1&0x20) ? "Yes" : "No ",
159 (c1&0x40) ? "Yes" : "No " );
160
161 pci_read_config_byte(bmide_dev, 0x54, &reg5xh);
162 pci_read_config_byte(bmide_dev, 0x55, &reg5yh);
163 q = "FIFO threshold: %2d Words %2d Words %2d Words %2d Words\n";
164 if (rev < 0xc1) {
165 if ((rev == 0x20) && (pci_read_config_byte(bmide_dev, 0x4f, &tmp), (tmp &= 0x20))) {
166 p += sprintf(p, q, 8, 8, 8, 8);
167 } else {
168 p += sprintf(p, q,
169 (reg5xh & 0x03) + 12,
170 ((reg5xh & 0x30)>>4) + 12,
171 (reg5yh & 0x03) + 12,
172 ((reg5yh & 0x30)>>4) + 12 );
173 }
174 } else {
175 p += sprintf(p, q,
176 (tmp = (reg5xh & 0x03)) ? (tmp << 3) : 4,
177 (tmp = ((reg5xh & 0x30)>>4)) ? (tmp << 3) : 4,
178 (tmp = (reg5yh & 0x03)) ? (tmp << 3) : 4,
179 (tmp = ((reg5yh & 0x30)>>4)) ? (tmp << 3) : 4 );
180 }
181
182 #if 0
183 p += sprintf(p,
184 "FIFO threshold: %2d Words %2d Words %2d Words %2d Words\n",
185 (reg5xh & 0x03) + 12,
186 ((reg5xh & 0x30)>>4) + 12,
187 (reg5yh & 0x03) + 12,
188 ((reg5yh & 0x30)>>4) + 12 );
189 #endif
190
191 p += sprintf(p,
192 "FIFO mode: %s %s %s %s\n",
193 fifo[((reg5xh & 0x0c) >> 2)],
194 fifo[((reg5xh & 0xc0) >> 6)],
195 fifo[((reg5yh & 0x0c) >> 2)],
196 fifo[((reg5yh & 0xc0) >> 6)] );
197
198 pci_read_config_byte(bmide_dev, 0x5a, &reg5xh);
199 pci_read_config_byte(bmide_dev, 0x5b, &reg5xh1);
200 pci_read_config_byte(bmide_dev, 0x5e, &reg5yh);
201 pci_read_config_byte(bmide_dev, 0x5f, &reg5yh1);
202
203 p += sprintf(p,/*
204 "------------------drive0-----------drive1------------drive0-----------drive1------\n")*/
205 "Dt RW act. Cnt %2dT %2dT %2dT %2dT\n"
206 "Dt RW rec. Cnt %2dT %2dT %2dT %2dT\n\n",
207 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
208 (reg5xh1 & 0x70) ? ((reg5xh1 & 0x70) >> 4) : 8,
209 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
210 (reg5yh1 & 0x70) ? ((reg5yh1 & 0x70) >> 4) : 8,
211 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
212 (reg5xh1 & 0x0f) ? (reg5xh1 & 0x0f) : 16,
213 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16,
214 (reg5yh1 & 0x0f) ? (reg5yh1 & 0x0f) : 16 );
215
216 p += sprintf(p,
217 "-----------------------------------UDMA Timings--------------------------------\n\n");
218
219 pci_read_config_byte(bmide_dev, 0x56, &reg5xh);
220 pci_read_config_byte(bmide_dev, 0x57, &reg5yh);
221 p += sprintf(p,
222 "UDMA: %s %s %s %s\n"
223 "UDMA timings: %s %s %s %s\n\n",
224 (reg5xh & 0x08) ? "OK" : "No",
225 (reg5xh & 0x80) ? "OK" : "No",
226 (reg5yh & 0x08) ? "OK" : "No",
227 (reg5yh & 0x80) ? "OK" : "No",
228 udmaT[(reg5xh & 0x07)],
229 udmaT[(reg5xh & 0x70) >> 4],
230 udmaT[reg5yh & 0x07],
231 udmaT[(reg5yh & 0x70) >> 4] );
232
233 return p-buffer; /* => must be less than 4k! */
234 }
235 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
236
237 static byte m5229_revision = 0;
238 static byte chip_is_1543c_e = 0;
239 static byte cable_80_pin[2] = { 0, 0 };
240
241 byte ali_proc = 0;
242 static struct pci_dev *isa_dev;
243
244 static void ali15x3_tune_drive (ide_drive_t *drive, byte pio)
245 {
246 ide_pio_data_t d;
247 ide_hwif_t *hwif = HWIF(drive);
248 struct pci_dev *dev = hwif->pci_dev;
249 int s_time, a_time, c_time;
250 byte s_clc, a_clc, r_clc;
251 unsigned long flags;
252 int bus_speed = ide_system_bus_speed();
253 int port = hwif->index ? 0x5c : 0x58;
254
255 pio = ide_get_best_pio_mode(drive, pio, 5, &d);
256 s_time = ide_pio_timings[pio].setup_time;
257 a_time = ide_pio_timings[pio].active_time;
258 if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8)
259 s_clc = 0;
260 if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8)
261 a_clc = 0;
262 c_time = ide_pio_timings[pio].cycle_time;
263
264 #if 0
265 if ((r_clc = ((c_time - s_time - a_time) * bus_speed + 999) / 1000) >= 16)
266 r_clc = 0;
267 #endif
268
269 if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) {
270 r_clc = 1;
271 } else {
272 if (r_clc >= 16)
273 r_clc = 0;
274 }
275 save_flags(flags);
276 cli();
277 pci_write_config_byte(dev, port, s_clc);
278 pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc);
279 restore_flags(flags);
280
281 /*
282 * setup active rec
283 * { 70, 165, 365 }, PIO Mode 0
284 * { 50, 125, 208 }, PIO Mode 1
285 * { 30, 100, 110 }, PIO Mode 2
286 * { 30, 80, 70 }, PIO Mode 3 with IORDY
287 * { 25, 70, 25 }, PIO Mode 4 with IORDY ns
288 * { 20, 50, 30 } PIO Mode 5 with IORDY (nonstandard)
289 */
290
291 }
292
293 static __inline__ unsigned char dma2_bits_to_command(unsigned char bits)
294 {
295 if (bits & 0x04)
296 return XFER_MW_DMA_2;
297 if (bits & 0x02)
298 return XFER_MW_DMA_1;
299 return XFER_MW_DMA_0;
300 }
301
302 static __inline__ unsigned char udma2_bits_to_command(unsigned char bits)
303 {
304 if (bits & 0x10)
305 return XFER_UDMA_4;
306 if (bits & 0x08)
307 return XFER_UDMA_3;
308 if (bits & 0x04)
309 return XFER_UDMA_2;
310 if (bits & 0x02)
311 return XFER_UDMA_1;
312 return XFER_UDMA_0;
313 }
314
315 static __inline__ int wait_for_ready(ide_drive_t *drive)
316 {
317 int timeout = 20000; /* (old value: 100) */
318 byte stat;
319
320 while (--timeout) {
321 stat = GET_STAT();
322 /*
323 * printk("STAT(%2x) ", stat);
324 */
325 if (!(stat & BUSY_STAT)) {
326 if ((stat & READY_STAT) || (stat & ERR_STAT)) {
327 break;
328 }
329 }
330 /*
331 * (old value: 100)
332 */
333 udelay(150);
334 }
335 if ((stat & ERR_STAT) || timeout <= 0)
336 return 1;
337 return 0;
338 }
339
340 static void ali15x3_do_setfeature(ide_drive_t *drive, byte command)
341 {
342 unsigned long flags;
343 byte old_select;
344
345 save_flags(flags);
346 cli();
347
348 /* save old selected device */
349 old_select = IN_BYTE(IDE_SELECT_REG);
350 /* "SELECT " */
351 OUT_BYTE(drive->select.all, IDE_SELECT_REG);
352 /* "SETXFER " */
353 OUT_BYTE(SETFEATURES_XFER, IDE_FEATURE_REG);
354 /* "CMND " */
355 OUT_BYTE(command, IDE_NSECTOR_REG);
356
357 if(wait_for_ready(drive)) /* "wait " */
358 goto out;
359
360 /* "SETFEATURE " */
361 OUT_BYTE(WIN_SETFEATURES, IDE_COMMAND_REG);
362 /* "wait " */
363 (void) wait_for_ready(drive);
364
365 out:
366 /*
367 * restore to old "selected device"
368 */
369 OUT_BYTE(old_select, IDE_SELECT_REG);
370 restore_flags(flags);
371 }
372
373 static void ali15x3_dma2_enable(ide_drive_t *drive, unsigned long dma_base)
374 {
375 byte unit = (drive->select.b.unit & 0x01);
376 byte bits = (drive->id->dma_mword | drive->id->dma_1word) & 0x07;
377 byte tmpbyte;
378 ide_hwif_t *hwif = HWIF(drive);
379 unsigned long flags;
380 int m5229_udma_setting_index = hwif->channel? 0x57 : 0x56;
381
382 ali15x3_do_setfeature(drive, dma2_bits_to_command(bits));
383
384 /*
385 * clear "ultra enable" bit
386 */
387 pci_read_config_byte(hwif->pci_dev, m5229_udma_setting_index, &tmpbyte);
388 if (unit) {
389 tmpbyte &= 0x7f;
390 } else {
391 tmpbyte &= 0xf7;
392 }
393 save_flags(flags);
394 cli();
395 pci_write_config_byte(hwif->pci_dev, m5229_udma_setting_index, tmpbyte);
396 restore_flags(flags);
397 drive->id->dma_ultra = 0x00;
398
399 /*
400 * Enable DMA
401 */
402 outb(inb(dma_base+2)|(1<<(5+unit)), dma_base+2);
403 printk("ALI15X3: MultiWord DMA enabled\n");
404 }
405
406 static void ali15x3_udma_enable(ide_drive_t *drive, unsigned long dma_base)
407 {
408 byte unit = (drive->select.b.unit & 0x01);
409 byte bits = drive->id->dma_ultra & 0x1f;
410 byte tmpbyte;
411 ide_hwif_t *hwif = HWIF(drive);
412 unsigned long flags;
413 unsigned char udma_mode = 0;
414 int m5229_udma_setting_index = hwif->channel? 0x57 : 0x56;
415
416 if (bits & 0x18) {
417 /*
418 * 00011000, disk: ultra66
419 */
420 if (m5229_revision < 0xc2) {
421 /*
422 * controller: ultra33
423 */
424 bits = 0x04;
425 /*
426 * 00000100, use ultra33, mode 2
427 */
428 drive->id->dma_ultra &= ~0xFF00;
429 drive->id->dma_ultra |= 0x0004;
430 } else {
431 /*
432 * controller: ultra66
433 *
434 * Try to detect word93 bit13 and
435 * 80-pin cable (from host view)
436 */
437 if (!((drive->id->word93 & 0x2000) &&
438 cable_80_pin[hwif->channel])) {
439 bits = 0x04;
440 /*
441 * 00000100, use ultra33, mode 2
442 */
443 drive->id->dma_ultra &= ~0xFF00;
444 drive->id->dma_ultra |= 0x0004;
445 }
446 }
447 }
448
449 /*
450 * set feature regardless
451 */
452 ali15x3_do_setfeature(drive, udma_mode = udma2_bits_to_command(bits));
453 udma_mode &= 0x0f; /* get UDMA mode */
454
455 /*
456 * Enable DMA and UltraDMA
457 */
458 outb(inb(dma_base+2)|(1<<(5+unit)), dma_base+2);
459 /*
460 * m5229 ultra
461 */
462 pci_read_config_byte(hwif->pci_dev, m5229_udma_setting_index, &tmpbyte);
463 /*
464 * clear bit0~3 or bit 4~7
465 */
466 tmpbyte &= (0x0f << ((1-unit) << 2));
467 /*
468 * enable ultra dma and set timing
469 */
470 tmpbyte |= ((0x08 | (4-udma_mode)) << (unit << 2));
471 /*
472 * set to m5229
473 */
474 save_flags(flags);
475 cli();
476 pci_write_config_byte(hwif->pci_dev, m5229_udma_setting_index, tmpbyte);
477 restore_flags(flags);
478
479 if (udma_mode >= 3) {
480 /*
481 * ultra 66
482 */
483 pci_read_config_byte(hwif->pci_dev, 0x4b, &tmpbyte);
484 tmpbyte |= 1;
485 save_flags(flags);
486 cli();
487 pci_write_config_byte(hwif->pci_dev, 0x4b, tmpbyte);
488 restore_flags(flags);
489 }
490
491 printk("ALI15X3: Ultra DMA enabled\n");
492 }
493
494 static int ali15x3_dma_onoff(ide_drive_t *drive, int enable)
495 {
496 if (enable) {
497 ide_hwif_t *hwif = HWIF(drive);
498 unsigned long dma_base = hwif->dma_base;
499 struct hd_driveid *id = drive->id;
500
501 if ((id->field_valid & 0x0004) &&
502 (id->dma_ultra & 0x001f)) {
503 /*
504 * 1543C_E, in ultra mode, WDC "harddisk"
505 * will cause "CRC" errors (even if no CRC problem),
506 * so we try to use "DMA" here
507 */
508 if (m5229_revision <= 0x20) {
509 /*
510 * Normal MultiWord DMA modes.
511 */
512 ali15x3_dma2_enable(drive, dma_base);
513 } else if ((m5229_revision < 0xC2) &&
514 ((drive->media!=ide_disk) ||
515 (chip_is_1543c_e &&
516 strstr(id->model, "WDC ")))) {
517 /*
518 * Normal MultiWord DMA modes.
519 */
520 ali15x3_dma2_enable(drive, dma_base);
521 } else {
522 /*
523 * m5229_revision >= 0xC2 for UltraDMA modes.
524 */
525 ali15x3_udma_enable(drive, dma_base);
526 }
527 } else {
528 /*
529 * Normal MultiWord DMA modes.
530 */
531 ali15x3_dma2_enable(drive, dma_base);
532 }
533 }
534
535 drive->using_dma = enable; /* on, off */
536 return 0;
537 }
538
539 static int ali15x3_config_drive_for_dma(ide_drive_t *drive)
540 {
541 struct hd_driveid *id = drive->id;
542 ide_hwif_t *hwif = HWIF(drive);
543
544 if ((m5229_revision<=0x20) && (drive->media!=ide_disk))
545 return hwif->dmaproc(ide_dma_off_quietly, drive);
546 /*
547 * Even if the drive is not _currently_ in a DMA
548 * mode, we succeed, and we'll enable it manually
549 * below in alim15x3_dma_onoff
550 */
551 if ((id != NULL) && (id->capability & 1) && hwif->autodma) {
552 if (id->field_valid & 0x0004) {
553 if (id->dma_ultra & 0x001F)
554 return hwif->dmaproc(ide_dma_on, drive);
555 }
556 if (id->field_valid & 0x0002) {
557 if ((id->dma_mword & 0x0007) || (id->dma_1word & 0x0007))
558 return hwif->dmaproc(ide_dma_on, drive);
559 }
560 }
561 return hwif->dmaproc(ide_dma_off_quietly, drive);
562 }
563
564 static int ali15x3_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
565 {
566 switch(func) {
567 case ide_dma_check:
568 return ali15x3_config_drive_for_dma(drive);
569 case ide_dma_on:
570 case ide_dma_off:
571 case ide_dma_off_quietly:
572 return ali15x3_dma_onoff(drive, (func == ide_dma_on));
573 case ide_dma_write:
574 if ((m5229_revision < 0xC2) && (drive->media != ide_disk))
575 return 1; /* try PIO instead of DMA */
576 break;
577 default:
578 break;
579 }
580
581 return ide_dmaproc(func, drive); /* use standard DMA stuff */
582 }
583
584 unsigned int __init pci_init_ali15x3 (struct pci_dev *dev, const char *name)
585 {
586 struct pci_dev *isa;
587 unsigned long fixdma_base = dev->resource[4].start;
588 byte tmpbyte;
589
590 pci_read_config_byte(dev, PCI_REVISION_ID, &m5229_revision);
591
592 for (isa = pci_devices; isa; isa=isa->next) {
593 /*
594 * look for ISA bridge
595 */
596 if (isa->vendor == PCI_VENDOR_ID_AL &&
597 isa->device == PCI_DEVICE_ID_AL_M1533) {
598 isa_dev = isa;
599 break;
600 }
601 }
602
603 if (!fixdma_base || fixdma_base == PCI_BASE_ADDRESS_IO_MASK) {
604 /*
605 *
606 */
607 } else {
608 /*
609 * enable DMA capable bit, and "not" simplex only
610 */
611 outb(inb(fixdma_base+2) & 0x60, fixdma_base+2);
612
613 if (inb(fixdma_base+2) & 0x80)
614 printk("%s: simplex device: DMA will fail!!\n", name);
615 }
616
617 /*
618 * FIXME !!! This detection needs to be in "ata66_ali15x3()"
619 * below as a standard detection return.
620 */
621
622 if (m5229_revision >= 0xC2) {
623 unsigned long flags;
624 /*
625 * 1543C-B?, 1535, 1535D, 1553
626 * Note 1: not all "motherboard" support this detection
627 * Note 2: if no udma 66 device, the detection may "error".
628 * but in this case, we will not set the device to
629 * ultra 66, the detection result is not important
630 */
631 save_flags(flags);
632 cli();
633
634 /*
635 * enable "Cable Detection", m5229, 0x4b, bit3
636 */
637 pci_read_config_byte(dev, 0x4b, &tmpbyte);
638 pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
639
640 /*
641 * set south-bridge's enable bit, m1533, 0x79
642 */
643 pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
644 if (m5229_revision == 0xC2) {
645 /*
646 * 1543C-B0 (m1533, 0x79, bit 2)
647 */
648 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
649 } else if (m5229_revision == 0xC3) {
650 /*
651 * 1553/1535 (m1533, 0x79, bit 1)
652 */
653 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
654 }
655 restore_flags(flags);
656 /*
657 * Ultra66 cable detection (from Host View)
658 * m5229, 0x4a, bit0: primary, bit1: secondary 80 pin
659 */
660 pci_read_config_byte(dev, 0x4a, &tmpbyte);
661 /*
662 * 0x4a, bit0 is 0 => primary channel
663 * has 80-pin (from host view)
664 */
665 if (!(tmpbyte & 0x01))
666 cable_80_pin[0] = 1;
667 /*
668 * 0x4a, bit1 is 0 => secondary channel
669 * has 80-pin (from host view)
670 */
671 if (!(tmpbyte & 0x02))
672 cable_80_pin[1] = 1;
673 } else {
674 unsigned long flags;
675 /*
676 * revision 0x20 (1543-E, 1543-F)
677 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
678 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
679 */
680 pci_read_config_byte(dev, 0x4b, &tmpbyte);
681 save_flags(flags);
682 cli();
683 /*
684 * clear bit 7
685 */
686 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
687 restore_flags(flags);
688
689 /*
690 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
691 */
692 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
693 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
694 }
695
696 return 0;
697 }
698
699 unsigned int __init ata66_ali15x3 (ide_hwif_t *hwif)
700 {
701 /*
702 * FIXME !!!!
703 * {0x4a,0x01,0x01}, {0x4a,0x02,0x02}
704 */
705 return 0;
706 }
707
708 void __init ide_init_ali15x3 (ide_hwif_t *hwif)
709 {
710 byte ideic, inmir;
711 byte irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
712 1, 11, 0, 12, 0, 14, 0, 15 };
713
714 hwif->irq = hwif->channel ? 15 : 14;
715
716 if (isa_dev) {
717 /*
718 * read IDE interface control
719 */
720 pci_read_config_byte(isa_dev, 0x58, &ideic);
721
722 /* bit0, bit1 */
723 ideic = ideic & 0x03;
724
725 /* get IRQ for IDE Controller */
726 if ((hwif->channel && ideic == 0x03) ||
727 (!hwif->channel && !ideic)) {
728 /*
729 * get SIRQ1 routing table
730 */
731 pci_read_config_byte(isa_dev, 0x44, &inmir);
732 inmir = inmir & 0x0f;
733 hwif->irq = irq_routing_table[inmir];
734 } else if (hwif->channel && !(ideic & 0x01)) {
735 /*
736 * get SIRQ2 routing table
737 */
738 pci_read_config_byte(isa_dev, 0x75, &inmir);
739 inmir = inmir & 0x0f;
740 hwif->irq = irq_routing_table[inmir];
741 }
742 }
743
744 hwif->tuneproc = &ali15x3_tune_drive;
745 if ((hwif->dma_base) && (m5229_revision >= 0xC1)) {
746 /*
747 * M1543C or newer for DMAing
748 */
749 hwif->dmaproc = &ali15x3_dmaproc;
750 hwif->autodma = 1;
751 } else {
752 hwif->autodma = 0;
753 hwif->drives[0].autotune = 1;
754 hwif->drives[1].autotune = 1;
755 }
756
757 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
758 ali_proc = 1;
759 bmide_dev = hwif->pci_dev;
760 ali_display_info = &ali_get_info;
761 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
762
763 return;
764 }
765
766 void ide_dmacapable_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase)
767 {
768 if ((dmabase) && (m5229_revision < 0x20)) {
769 return;
770 }
771 ide_setup_dma(hwif, dmabase, 8);
772 }
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