include/asm-i386/io_apic.h

   1 #ifndef __ASM_IO_APIC_H
   2 #define __ASM_IO_APIC_H
   3
   4 #include <linux/config.h>
   5 #include <asm/types.h>
   6
   7 /*
   8  * Intel IO-APIC support for SMP and UP systems.
   9  *
  10  * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
  11  */
  12
  13 #ifdef CONFIG_X86_IO_APIC
  14
  15 #define IO_APIC_BASE(idx) \
  16                 ((volatile int *)__fix_to_virt(FIX_IO_APIC_BASE_0 + idx))
  17
  18 /*
  19  * The structure of the IO-APIC:
  20  */
  21 struct IO_APIC_reg_00 {
  22         __u32   __reserved_2    : 24,
  23                 ID              :  4,
  24                 __reserved_1    :  4;
  25 } __attribute__ ((packed));
  26
  27 struct IO_APIC_reg_01 {
  28         __u32   version         :  8,
  29                 __reserved_2    :  8,
  30                 entries         :  8,
  31                 __reserved_1    :  8;
  32 } __attribute__ ((packed));
  33
  34 struct IO_APIC_reg_02 {
  35         __u32   __reserved_2    : 24,
  36                 arbitration     :  4,
  37                 __reserved_1    :  4;
  38 } __attribute__ ((packed));
  39
  40 /*
  41  * # of IO-APICs and # of IRQ routing registers
  42  */
  43 extern int nr_ioapics;
  44 extern int nr_ioapic_registers[MAX_IO_APICS];
  45
  46 enum ioapic_irq_destination_types {
  47         dest_Fixed = 0,
  48         dest_LowestPrio = 1,
  49         dest_SMI = 2,
  50         dest__reserved_1 = 3,
  51         dest_NMI = 4,
  52         dest_INIT = 5,
  53         dest__reserved_2 = 6,
  54         dest_ExtINT = 7
  55 };
  56
  57 struct IO_APIC_route_entry {
  58         __u32   vector          :  8,
  59                 delivery_mode   :  3,   /* 000: FIXED
  60                                          * 001: lowest prio
  61                                          * 111: ExtINT
  62                                          */
  63                 dest_mode       :  1,   /* 0: physical, 1: logical */
  64                 delivery_status :  1,
  65                 polarity        :  1,
  66                 irr             :  1,
  67                 trigger         :  1,   /* 0: edge, 1: level */
  68                 mask            :  1,   /* 0: enabled, 1: disabled */
  69                 __reserved_2    : 15;
  70
  71         union {         struct { __u32
  72                                         __reserved_1    : 24,
  73                                         physical_dest   :  4,
  74                                         __reserved_2    :  4;
  75                         } physical;
  76
  77                         struct { __u32
  78                                         __reserved_1    : 24,
  79                                         logical_dest    :  8;
  80                         } logical;
  81         } dest;
  82
  83 } __attribute__ ((packed));
  84
  85 /*
  86  * MP-BIOS irq configuration table structures:
  87  */
  88
  89 /* I/O APIC entries */
  90 extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
  91
  92 /* # of MP IRQ source entries */
  93 extern int mp_irq_entries;
  94
  95 /* MP IRQ source entries */
  96 extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
  97
  98 /* non-0 if default (table-less) MP configuration */
  99 extern int mpc_default_type;
 100
 101 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 102 {
 103         *IO_APIC_BASE(apic) = reg;
 104         return *(IO_APIC_BASE(apic)+4);
 105 }
 106
 107 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 108 {
 109         *IO_APIC_BASE(apic) = reg;
 110         *(IO_APIC_BASE(apic)+4) = value;
 111 }
 112
 113 /*
 114  * Re-write a value: to be used for read-modify-write
 115  * cycles where the read already set up the index register.
 116  */
 117 static inline void io_apic_modify(unsigned int apic, unsigned int value)
 118 {
 119         *(IO_APIC_BASE(apic)+4) = value;
 120 }
 121
 122 /*
 123  * Synchronize the IO-APIC and the CPU by doing
 124  * a dummy read from the IO-APIC
 125  */
 126 static inline void io_apic_sync(unsigned int apic)
 127 {
 128         (void) *(IO_APIC_BASE(apic)+4);
 129 }
 130
 131 extern int nmi_watchdog;
 132 /* 1 if "noapic" boot option passed */
 133 extern int skip_ioapic_setup;
 134 extern void IO_APIC_init_uniprocessor (void);
 135
 136 /*
 137  * If we use the IO-APIC for IRQ routing, disable automatic
 138  * assignment of PCI IRQ's.
 139  */
 140 #define io_apic_assign_pci_irqs (mp_irq_entries && !skip_ioapic_setup)
 141
 142 #else  /* !CONFIG_X86_IO_APIC */
 143 #define io_apic_assign_pci_irqs 0
 144 #endif
 145
 146 #endif