2 * $Id: pci.c,v 1.64 1999/09/17 18:01:53 cort Exp $
3 * Common pmac/prep/chrp pci routines. -- Cort
6 #include <linux/kernel.h>
8 #include <linux/delay.h>
9 #include <linux/string.h>
10 #include <linux/init.h>
11 #include <linux/openpic.h>
12 #include <linux/capability.h>
13 #include <linux/sched.h>
14 #include <linux/errno.h>
16 #include <asm/processor.h>
19 #include <asm/pci-bridge.h>
20 #include <asm/residual.h>
21 #include <asm/byteorder.h>
24 #include <asm/uaccess.h>
31 #define DBG(x...) printk(x)
36 unsigned long isa_io_base
= 0;
37 unsigned long isa_mem_base
= 0;
38 unsigned long pci_dram_offset
= 0;
40 struct pci_fixup pcibios_fixups
[] = {
44 int generic_pcibios_read_byte(struct pci_dev
*dev
, int where
, u8
*val
)
46 return ppc_md
.pcibios_read_config_byte(dev
->bus
->number
,dev
->devfn
,where
,val
);
48 int generic_pcibios_read_word(struct pci_dev
*dev
, int where
, u16
*val
)
50 return ppc_md
.pcibios_read_config_word(dev
->bus
->number
,dev
->devfn
,where
,val
);
52 int generic_pcibios_read_dword(struct pci_dev
*dev
, int where
, u32
*val
)
54 return ppc_md
.pcibios_read_config_dword(dev
->bus
->number
,dev
->devfn
,where
,val
);
56 int generic_pcibios_write_byte(struct pci_dev
*dev
, int where
, u8 val
)
58 return ppc_md
.pcibios_write_config_byte(dev
->bus
->number
,dev
->devfn
,where
,val
);
60 int generic_pcibios_write_word(struct pci_dev
*dev
, int where
, u16 val
)
62 return ppc_md
.pcibios_write_config_word(dev
->bus
->number
,dev
->devfn
,where
,val
);
64 int generic_pcibios_write_dword(struct pci_dev
*dev
, int where
, u32 val
)
66 return ppc_md
.pcibios_write_config_dword(dev
->bus
->number
,dev
->devfn
,where
,val
);
69 struct pci_ops generic_pci_ops
=
71 generic_pcibios_read_byte
,
72 generic_pcibios_read_word
,
73 generic_pcibios_read_dword
,
74 generic_pcibios_write_byte
,
75 generic_pcibios_write_word
,
76 generic_pcibios_write_dword
81 void pcibios_update_resource(struct pci_dev
*dev
, struct resource
*root
,
82 struct resource
*res
, int resource
)
87 new = res
->start
| (res
->flags
& PCI_REGION_FLAG_MASK
);
89 reg
= PCI_BASE_ADDRESS_0
+ 4*resource
;
90 } else if (resource
== PCI_ROM_RESOURCE
) {
91 res
->flags
|= PCI_ROM_ADDRESS_ENABLE
;
92 reg
= dev
->rom_base_reg
;
94 /* Somebody might have asked allocation of a non-standard resource */
98 pci_write_config_dword(dev
, reg
, new);
99 pci_read_config_dword(dev
, reg
, &check
);
100 if ((new ^ check
) & ((new & PCI_BASE_ADDRESS_SPACE_IO
) ? PCI_BASE_ADDRESS_IO_MASK
: PCI_BASE_ADDRESS_MEM_MASK
)) {
101 printk(KERN_ERR
"PCI: Error while updating region "
102 "%s/%d (%08x != %08x)\n", dev
->slot_name
, resource
,
108 * We need to avoid collisions with `mirrored' VGA ports
109 * and other strange ISA hardware, so we always want the
110 * addresses to be allocated in the 0x000-0x0ff region
113 * Why? Because some silly external IO cards only decode
114 * the low 10 bits of the IO address. The 0x00-0xff region
115 * is reserved for motherboard devices that decode all 16
116 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
117 * but we want to try to avoid allocating at 0x2900-0x2bff
118 * which might have be mirrored at 0x0100-0x03ff..
121 pcibios_align_resource(void *data
, struct resource
*res
, unsigned long size
)
123 struct pci_dev
*dev
= data
;
125 if (res
->flags
& IORESOURCE_IO
) {
126 unsigned long start
= res
->start
;
129 printk(KERN_ERR
"PCI: I/O Region %s/%d too large"
130 " (%ld bytes)\n", dev
->slot_name
,
131 dev
->resource
- res
, size
);
135 start
= (start
+ 0x3ff) & ~0x3ff;
143 * Handle resources of PCI devices. If the world were perfect, we could
144 * just allocate all the resource regions and do nothing more. It isn't.
145 * On the other hand, we cannot just re-allocate all devices, as it would
146 * require us to know lots of host bridge internals. So we attempt to
147 * keep as much of the original configuration as possible, but tweak it
148 * when it's found to be wrong.
150 * Known BIOS problems we have to work around:
151 * - I/O or memory regions not configured
152 * - regions configured, but not enabled in the command register
153 * - bogus I/O addresses above 64K used
154 * - expansion ROMs left enabled (this may sound harmless, but given
155 * the fact the PCI specs explicitly allow address decoders to be
156 * shared between expansion ROMs and other resource regions, it's
157 * at least dangerous)
160 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
161 * This gives us fixed barriers on where we can allocate.
162 * (2) Allocate resources for all enabled devices. If there is
163 * a collision, just mark the resource as unallocated. Also
164 * disable expansion ROMs during this step.
165 * (3) Try to allocate resources for disabled devices. If the
166 * resources were assigned correctly, everything goes well,
167 * if they weren't, they won't disturb allocation of other
169 * (4) Assign new addresses to resources which were either
170 * not configured at all or misconfigured. If explicitly
171 * requested by the user, configure expansion ROM address
175 static void __init
pcibios_allocate_bus_resources(struct list_head
*bus_list
)
177 struct list_head
*ln
;
181 struct resource
*r
, *pr
;
183 /* Depth-First Search on bus tree */
184 for (ln
=bus_list
->next
; ln
!= bus_list
; ln
=ln
->next
) {
186 if ((dev
= bus
->self
)) {
187 for (idx
= PCI_BRIDGE_RESOURCES
; idx
< PCI_NUM_RESOURCES
; idx
++) {
188 r
= &dev
->resource
[idx
];
191 pr
= pci_find_parent_resource(dev
, r
);
192 if (!pr
|| request_resource(pr
, r
) < 0)
193 printk(KERN_ERR
"PCI: Cannot allocate resource region %d of bridge %s\n", idx
, dev
->slot_name
);
196 pcibios_allocate_bus_resources(&bus
->children
);
200 static void __init
pcibios_allocate_resources(int pass
)
205 struct resource
*r
, *pr
;
207 pci_for_each_dev(dev
) {
208 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
209 for(idx
= 0; idx
< 6; idx
++) {
210 r
= &dev
->resource
[idx
];
211 if (r
->parent
) /* Already allocated */
213 if (!r
->start
) /* Address not assigned at all */
215 if (r
->end
== 0xffffffff) {
216 /* LongTrail OF quirk: unassigned */
217 DBG("PCI: Resource %08lx-%08lx was unassigned\n", r
->start
, r
->end
);
223 if (r
->flags
& IORESOURCE_IO
)
224 disabled
= !(command
& PCI_COMMAND_IO
);
226 disabled
= !(command
& PCI_COMMAND_MEMORY
);
227 if (pass
== disabled
) {
228 DBG("PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n",
229 r
->start
, r
->end
, r
->flags
, disabled
, pass
);
230 pr
= pci_find_parent_resource(dev
, r
);
231 if (!pr
|| request_resource(pr
, r
) < 0) {
232 printk(KERN_ERR
"PCI: Cannot allocate resource region %d of device %s\n", idx
, dev
->slot_name
);
233 /* We'll assign a new address later */
240 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
241 if (r
->flags
& PCI_ROM_ADDRESS_ENABLE
) {
242 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
244 DBG("PCI: Switching off ROM of %s\n", dev
->slot_name
);
245 r
->flags
&= ~PCI_ROM_ADDRESS_ENABLE
;
246 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
247 pci_write_config_dword(dev
, dev
->rom_base_reg
, reg
& ~PCI_ROM_ADDRESS_ENABLE
);
253 static void __init
pcibios_assign_resources(void)
259 pci_for_each_dev(dev
) {
260 int class = dev
->class >> 8;
262 /* Don't touch classless devices and host bridges */
263 if (!class || class == PCI_CLASS_BRIDGE_HOST
)
266 for(idx
=0; idx
<6; idx
++) {
267 r
= &dev
->resource
[idx
];
270 * Don't touch IDE controllers and I/O ports of video cards!
272 if ((class == PCI_CLASS_STORAGE_IDE
&& idx
< 4) ||
273 (class == PCI_CLASS_DISPLAY_VGA
&& (r
->flags
& IORESOURCE_IO
)))
277 * We shall assign a new address to this resource, either because
278 * the BIOS forgot to do so or because we have decided the old
279 * address was unusable for some reason.
281 if (!r
->start
&& r
->end
)
282 pci_assign_resource(dev
, idx
);
285 if (0) { /* don't assign ROMs */
286 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
290 pci_assign_resource(dev
, PCI_ROM_RESOURCE
);
296 int pcibios_enable_resources(struct pci_dev
*dev
)
302 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
304 for(idx
=0; idx
<6; idx
++) {
305 r
= &dev
->resource
[idx
];
306 if (!r
->start
&& r
->end
) {
307 printk(KERN_ERR
"PCI: Device %s not available because of resource collisions\n", dev
->slot_name
);
310 if (r
->flags
& IORESOURCE_IO
)
311 cmd
|= PCI_COMMAND_IO
;
312 if (r
->flags
& IORESOURCE_MEM
)
313 cmd
|= PCI_COMMAND_MEMORY
;
315 if (dev
->resource
[PCI_ROM_RESOURCE
].start
)
316 cmd
|= PCI_COMMAND_MEMORY
;
317 if (cmd
!= old_cmd
) {
318 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev
->slot_name
, old_cmd
, cmd
);
319 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
326 void __init
pcibios_init(void)
328 printk("PCI: Probing PCI hardware\n");
329 pci_scan_bus(0, &generic_pci_ops
, NULL
);
330 if (ppc_md
.pcibios_fixup
)
331 ppc_md
.pcibios_fixup();
332 pcibios_allocate_bus_resources(&pci_root_buses
);
333 pcibios_allocate_resources(0);
334 pcibios_allocate_resources(1);
335 pcibios_assign_resources();
339 pcibios_fixup_pbus_ranges(struct pci_bus
* bus
, struct pbus_set_ranges_data
* ranges
)
341 ranges
->io_start
-= bus
->resource
[0]->start
;
342 ranges
->io_end
-= bus
->resource
[0]->start
;
343 ranges
->mem_start
-= bus
->resource
[1]->start
;
344 ranges
->mem_end
-= bus
->resource
[1]->start
;
348 void __init
pcibios_fixup_bus(struct pci_bus
*bus
)
350 if ( ppc_md
.pcibios_fixup_bus
)
351 ppc_md
.pcibios_fixup_bus(bus
);
354 char __init
*pcibios_setup(char *str
)
359 /* the next one is stolen from the alpha port... */
361 pcibios_update_irq(struct pci_dev
*dev
, int irq
)
363 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, irq
);
364 /* XXX FIXME - update OF device tree node interrupt property */
367 int pcibios_enable_device(struct pci_dev
*dev
)
373 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
375 for (idx
=0; idx
<6; idx
++) {
376 r
= &dev
->resource
[idx
];
377 if (!r
->start
&& r
->end
) {
378 printk(KERN_ERR
"PCI: Device %s not available because of resource collisions\n", dev
->slot_name
);
381 if (r
->flags
& IORESOURCE_IO
)
382 cmd
|= PCI_COMMAND_IO
;
383 if (r
->flags
& IORESOURCE_MEM
)
384 cmd
|= PCI_COMMAND_MEMORY
;
386 if (cmd
!= old_cmd
) {
387 printk("PCI: Enabling device %s (%04x -> %04x)\n",
388 dev
->slot_name
, old_cmd
, cmd
);
389 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
395 pci_dev_io_base(unsigned char bus
, unsigned char devfn
, int physical
)
397 if (!ppc_md
.pci_dev_io_base
) {
398 /* Please, someone fix this for non-pmac machines, we
399 * need either the virtual or physical PCI IO base
403 return ppc_md
.pci_dev_io_base(bus
, devfn
, physical
);
407 pci_dev_mem_base(unsigned char bus
, unsigned char devfn
)
409 /* Default memory base is 0 (1:1 mapping) */
410 if (!ppc_md
.pci_dev_mem_base
) {
411 /* Please, someone fix this for non-pmac machines.*/
414 return ppc_md
.pci_dev_mem_base(bus
, devfn
);
417 /* Returns the root-bridge number (Uni-N number) of a device */
419 pci_dev_root_bridge(unsigned char bus
, unsigned char devfn
)
422 if (!ppc_md
.pci_dev_root_bridge
)
424 return ppc_md
.pci_dev_root_bridge(bus
, devfn
);
427 /* Provide information on locations of various I/O regions in physical
428 * memory. Do this on a per-card basis so that we choose the right
430 * Note that the returned IO or memory base is a physical address
434 sys_pciconfig_iobase(long which
, unsigned long bus
, unsigned long devfn
)
436 long result
= -EOPNOTSUPP
;
439 case IOBASE_BRIDGE_NUMBER
:
440 return (long)pci_dev_root_bridge(bus
, devfn
);
442 return (long)pci_dev_mem_base(bus
, devfn
);
444 result
= (long)pci_dev_io_base(bus
, devfn
, 1);
446 result
= -EOPNOTSUPP
;