2 * Fast Ethernet Controller (FCC) driver for Motorola MPC8260.
3 * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
5 * This version of the driver is a combination of the 8xx fec and
6 * 8260 SCC Ethernet drivers. People seem to be choosing common I/O
7 * configurations, so this driver will work on the EST8260 boards and
8 * others yet to be announced.
10 * Right now, I am very watseful with the buffers. I allocate memory
11 * pages and then divide them into 2K frame buffers. This way I know I
12 * have buffers large enough to hold one frame within one buffer descriptor.
13 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
14 * will be much more memory efficient and will easily handle lots of
19 #include <linux/config.h>
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/string.h>
23 #include <linux/ptrace.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/malloc.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/delay.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/spinlock.h>
36 #include <asm/immap_8260.h>
37 #include <asm/pgtable.h>
38 #include <asm/mpc8260.h>
40 #include <asm/bitops.h>
41 #include <asm/uaccess.h>
42 #include <asm/cpm_8260.h>
44 /* The transmitter timeout
46 #define TX_TIMEOUT (2*HZ)
48 /* The number of Tx and Rx buffers. These are allocated from the page
49 * pool. The code may assume these are power of two, so it it best
50 * to keep them that size.
51 * We don't need to allocate pages for the transmitter. We just use
52 * the skbuffer directly.
54 #define FCC_ENET_RX_PAGES 16
55 #define FCC_ENET_RX_FRSIZE 2048
56 #define FCC_ENET_RX_FRPPG (PAGE_SIZE / FCC_ENET_RX_FRSIZE)
57 #define RX_RING_SIZE (FCC_ENET_RX_FRPPG * FCC_ENET_RX_PAGES)
58 #define TX_RING_SIZE 16 /* Must be power of two */
59 #define TX_RING_MOD_MASK 15 /* for this to work */
61 /* The FCC stores dest/src/type, data, and checksum for receive packets.
63 #define PKT_MAXBUF_SIZE 1518
64 #define PKT_MINBUF_SIZE 64
66 /* Maximum input DMA size. Must be a should(?) be a multiple of 4.
68 #define PKT_MAXDMA_SIZE 1520
70 /* Maximum input buffer size. Must be a multiple of 32.
72 #define PKT_MAXBLR_SIZE 1536
74 static int fcc_enet_open(struct net_device
*dev
);
75 static int fcc_enet_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
76 static int fcc_enet_rx(struct net_device
*dev
);
77 static void fcc_enet_mii(struct net_device
*dev
);
78 static void fcc_enet_interrupt(int irq
, void * dev_id
, struct pt_regs
* regs
);
79 static int fcc_enet_close(struct net_device
*dev
);
80 static struct net_device_stats
*fcc_enet_get_stats(struct net_device
*dev
);
81 static void set_multicast_list(struct net_device
*dev
);
82 static void restart_fcc(struct net_device
*dev
);
84 /* These will be configurable for the FCC choice.
85 * Multiple ports can be configured. There is little choice among the
86 * I/O pins to the PHY, except the clocks. We will need some board
87 * dependent clock selection.
88 * Why in the hell did I put these inside #ifdef's? I dunno, maybe to
89 * help show what pins are used for each device.
92 /* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
93 * but there is little variation among the choices.
95 #define PA1_COL ((uint)0x00000001)
96 #define PA1_CRS ((uint)0x00000002)
97 #define PA1_TXER ((uint)0x00000004)
98 #define PA1_TXEN ((uint)0x00000008)
99 #define PA1_RXDV ((uint)0x00000010)
100 #define PA1_RXER ((uint)0x00000020)
101 #define PA1_TXDAT ((uint)0x00003c00)
102 #define PA1_RXDAT ((uint)0x0003c000)
103 #define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
104 #define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
106 #define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
107 #define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
109 /* CLK12 is receive, CLK11 is transmit. These are board specific.
111 #define PC_F1RXCLK ((uint)0x00000800)
112 #define PC_F1TXCLK ((uint)0x00000400)
113 #define CMX1_CLK_ROUTE ((uint)0x3e000000)
114 #define CMX1_CLK_MASK ((uint)0xff000000)
116 /* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
117 * but there is little variation among the choices.
119 #define PB2_TXER ((uint)0x00000001)
120 #define PB2_RXDV ((uint)0x00000002)
121 #define PB2_TXEN ((uint)0x00000004)
122 #define PB2_RXER ((uint)0x00000008)
123 #define PB2_COL ((uint)0x00000010)
124 #define PB2_CRS ((uint)0x00000020)
125 #define PB2_TXDAT ((uint)0x000003c0)
126 #define PB2_RXDAT ((uint)0x00003c00)
127 #define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
128 PB2_RXER | PB2_RXDV | PB2_TXER)
129 #define PB2_PSORB1 (PB2_TXEN)
130 #define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
131 #define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
133 /* CLK13 is receive, CLK14 is transmit. These are board dependent.
135 #define PC_F2RXCLK ((uint)0x00001000)
136 #define PC_F2TXCLK ((uint)0x00002000)
137 #define CMX2_CLK_ROUTE ((uint)0x00250000)
138 #define CMX2_CLK_MASK ((uint)0x00ff0000)
140 /* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
141 * but there is little variation among the choices.
143 #define PB3_RXDV ((uint)0x00004000)
144 #define PB3_RXER ((uint)0x00008000)
145 #define PB3_TXER ((uint)0x00010000)
146 #define PB3_TXEN ((uint)0x00020000)
147 #define PB3_COL ((uint)0x00040000)
148 #define PB3_CRS ((uint)0x00080000)
149 #define PB3_TXDAT ((uint)0x0f000000)
150 #define PB3_RXDAT ((uint)0x00f00000)
151 #define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
152 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
153 #define PB3_PSORB1 (0)
154 #define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
155 #define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
157 /* CLK15 is receive, CLK16 is transmit. These are board dependent.
159 #define PC_F3RXCLK ((uint)0x00004000)
160 #define PC_F3TXCLK ((uint)0x00008000)
161 #define CMX3_CLK_ROUTE ((uint)0x00003700)
162 #define CMX3_CLK_MASK ((uint)0x0000ff00)
164 /* MII status/control serial interface.
166 #define PC_MDIO ((uint)0x00400000)
167 #define PC_MDCK ((uint)0x00200000)
169 /* A table of information for supporting FCCs. This does two things.
170 * First, we know how many FCCs we have and they are always externally
171 * numbered from zero. Second, it holds control register and I/O
172 * information that could be different among board designs.
174 typedef struct fcc_info
{
187 static fcc_info_t fcc_ports
[] = {
188 #ifdef CONFIG_FCC1_ENET
189 { 0, CPM_CR_FCC1_SBLOCK
, CPM_CR_FCC1_PAGE
, PROFF_FCC1
, SIU_INT_FCC1
,
190 (PC_F1RXCLK
| PC_F1TXCLK
), CMX1_CLK_ROUTE
, CMX1_CLK_MASK
,
193 #ifdef CONFIG_FCC2_ENET
194 { 1, CPM_CR_FCC2_SBLOCK
, CPM_CR_FCC2_PAGE
, PROFF_FCC2
, SIU_INT_FCC2
,
195 (PC_F2RXCLK
| PC_F2TXCLK
), CMX2_CLK_ROUTE
, CMX2_CLK_MASK
,
198 #ifdef CONFIG_FCC3_ENET
199 { 2, CPM_CR_FCC3_SBLOCK
, CPM_CR_FCC3_PAGE
, PROFF_FCC3
, SIU_INT_FCC3
,
200 (PC_F3RXCLK
| PC_F3TXCLK
), CMX3_CLK_ROUTE
, CMX3_CLK_MASK
,
205 /* The FCC buffer descriptors track the ring buffers. The rx_bd_base and
206 * tx_bd_base always point to the base of the buffer descriptors. The
207 * cur_rx and cur_tx point to the currently available buffer.
208 * The dirty_tx tracks the current buffer that is being sent by the
209 * controller. The cur_tx and dirty_tx are equal under both completely
210 * empty and completely full conditions. The empty/ready indicator in
211 * the buffer descriptor determines the actual condition.
213 struct fcc_enet_private
{
214 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
215 struct sk_buff
* tx_skbuff
[TX_RING_SIZE
];
219 /* CPM dual port RAM relative addresses.
221 cbd_t
*rx_bd_base
; /* Address of Rx and Tx buffers. */
223 cbd_t
*cur_rx
, *cur_tx
; /* The next free ring entry */
224 cbd_t
*dirty_tx
; /* The ring entries to be free()ed. */
225 volatile fcc_t
*fccp
;
226 volatile fcc_enet_t
*ep
;
227 struct net_device_stats stats
;
236 static void init_fcc_shutdown(fcc_info_t
*fip
, struct fcc_enet_private
*cep
,
237 volatile immap_t
*immap
);
238 static void init_fcc_startup(fcc_info_t
*fip
, struct net_device
*dev
);
239 static void init_fcc_ioports(fcc_info_t
*fip
, volatile iop8260_t
*io
,
240 volatile immap_t
*immap
);
241 static void init_fcc_param(fcc_info_t
*fip
, struct net_device
*dev
,
242 volatile immap_t
*immap
);
244 /* MII processing. We keep this as simple as possible. Requests are
245 * placed on the list (if there is room). When the request is finished
246 * by the MII, an optional function may be called.
248 typedef struct mii_list
{
250 void (*mii_func
)(uint val
, struct net_device
*dev
);
251 struct mii_list
*mii_next
;
255 mii_list_t mii_cmds
[NMII
];
256 mii_list_t
*mii_free
;
257 mii_list_t
*mii_head
;
258 mii_list_t
*mii_tail
;
263 static int mii_queue(int request
, void (*func
)(uint
, struct net_device
*));
264 static void mii_startup_cmds(void);
265 static uint
mii_send_receive(fcc_info_t
*fip
, uint cmd
);
267 /* Make MII read/write commands for the FCC.
270 #define mk_mii_phyaddr(ADDR) (0x60020000 | ((ADDR) << 23) | (2 << 18))
272 #define mk_mii_read(REG) (0x60020000 | ((phyaddr << 23) | \
275 #define mk_mii_write(REG, VAL) (0x50020000 | ((phyaddr << 23) | \
276 (REG & 0x1f) << 18) | \
281 fcc_enet_open(struct net_device
*dev
)
283 netif_start_queue(dev
);
284 return 0; /* Always succeed */
288 fcc_enet_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
290 struct fcc_enet_private
*cep
= (struct fcc_enet_private
*)dev
->priv
;
294 /* Fill in a Tx ring entry */
297 #ifndef final_version
298 if (bdp
->cbd_sc
& BD_ENET_TX_READY
) {
299 /* Ooops. All transmit buffers are full. Bail out.
300 * This should not happen, since cep->tx_full should be set.
302 printk("%s: tx queue full!.\n", dev
->name
);
307 /* Clear all of the status flags.
309 bdp
->cbd_sc
&= ~BD_ENET_TX_STATS
;
311 /* If the frame is short, tell CPM to pad it.
313 if (skb
->len
<= ETH_ZLEN
)
314 bdp
->cbd_sc
|= BD_ENET_TX_PAD
;
316 bdp
->cbd_sc
&= ~BD_ENET_TX_PAD
;
318 /* Set buffer length and buffer pointer.
320 bdp
->cbd_datlen
= skb
->len
;
321 bdp
->cbd_bufaddr
= __pa(skb
->data
);
325 cep
->tx_skbuff
[cep
->skb_cur
] = skb
;
327 cep
->stats
.tx_bytes
+= skb
->len
;
328 cep
->skb_cur
= (cep
->skb_cur
+1) & TX_RING_MOD_MASK
;
330 spin_lock_irq(&cep
->lock
);
332 /* Send it on its way. Tell CPM its ready, interrupt when done,
333 * its the last BD of the frame, and to put the CRC on the end.
335 bdp
->cbd_sc
|= (BD_ENET_TX_READY
| BD_ENET_TX_INTR
| BD_ENET_TX_LAST
| BD_ENET_TX_TC
);
338 /* Errata says don't do this.
340 cep
->fccp
->fcc_ftodr
= 0x8000;
342 dev
->trans_start
= jiffies
;
344 /* If this was the last BD in the ring, start at the beginning again.
346 if (bdp
->cbd_sc
& BD_ENET_TX_WRAP
)
347 bdp
= cep
->tx_bd_base
;
351 if (bdp
->cbd_sc
& BD_ENET_TX_READY
) {
352 netif_stop_queue(dev
);
356 cep
->cur_tx
= (cbd_t
*)bdp
;
358 spin_unlock_irq(&cep
->lock
);
365 fcc_enet_timeout(struct net_device
*dev
)
367 struct fcc_enet_private
*cep
= (struct fcc_enet_private
*)dev
->priv
;
369 printk("%s: transmit timed out.\n", dev
->name
);
370 cep
->stats
.tx_errors
++;
371 #ifndef final_version
375 printk(" Ring data dump: cur_tx %p%s cur_rx %p.\n",
376 cep
->cur_tx
, cep
->tx_full
? " (full)" : "",
378 bdp
= cep
->tx_bd_base
;
379 printk(" Tx @base %p :\n", bdp
);
380 for (i
= 0 ; i
< TX_RING_SIZE
; i
++, bdp
++)
381 printk("%04x %04x %08x\n",
385 bdp
= cep
->rx_bd_base
;
386 printk(" Rx @base %p :\n", bdp
);
387 for (i
= 0 ; i
< RX_RING_SIZE
; i
++, bdp
++)
388 printk("%04x %04x %08x\n",
395 netif_wake_queue(dev
);
398 /* The interrupt handler.
401 fcc_enet_interrupt(int irq
, void * dev_id
, struct pt_regs
* regs
)
403 struct net_device
*dev
= dev_id
;
404 volatile struct fcc_enet_private
*cep
;
409 cep
= (struct fcc_enet_private
*)dev
->priv
;
411 /* Get the interrupt events that caused us to be here.
413 int_events
= cep
->fccp
->fcc_fcce
;
414 cep
->fccp
->fcc_fcce
= int_events
;
417 /* Handle receive event in its own function.
419 if (int_events
& FCC_ENET_RXF
)
422 /* Check for a transmit error. The manual is a little unclear
423 * about this, so the debug code until I get it figured out. It
424 * appears that if TXE is set, then TXB is not set. However,
425 * if carrier sense is lost during frame transmission, the TXE
426 * bit is set, "and continues the buffer transmission normally."
427 * I don't know if "normally" implies TXB is set when the buffer
428 * descriptor is closed.....trial and error :-).
431 /* Transmit OK, or non-fatal error. Update the buffer descriptors.
433 if (int_events
& (FCC_ENET_TXE
| FCC_ENET_TXB
)) {
434 spin_lock(&cep
->lock
);
436 while ((bdp
->cbd_sc
&BD_ENET_TX_READY
)==0) {
437 if ((bdp
==cep
->cur_tx
) && (cep
->tx_full
== 0))
440 if (bdp
->cbd_sc
& BD_ENET_TX_HB
) /* No heartbeat */
441 cep
->stats
.tx_heartbeat_errors
++;
442 if (bdp
->cbd_sc
& BD_ENET_TX_LC
) /* Late collision */
443 cep
->stats
.tx_window_errors
++;
444 if (bdp
->cbd_sc
& BD_ENET_TX_RL
) /* Retrans limit */
445 cep
->stats
.tx_aborted_errors
++;
446 if (bdp
->cbd_sc
& BD_ENET_TX_UN
) /* Underrun */
447 cep
->stats
.tx_fifo_errors
++;
448 if (bdp
->cbd_sc
& BD_ENET_TX_CSL
) /* Carrier lost */
449 cep
->stats
.tx_carrier_errors
++;
452 /* No heartbeat or Lost carrier are not really bad errors.
453 * The others require a restart transmit command.
456 (BD_ENET_TX_LC
| BD_ENET_TX_RL
| BD_ENET_TX_UN
)) {
458 cep
->stats
.tx_errors
++;
461 cep
->stats
.tx_packets
++;
463 /* Deferred means some collisions occurred during transmit,
464 * but we eventually sent the packet OK.
466 if (bdp
->cbd_sc
& BD_ENET_TX_DEF
)
467 cep
->stats
.collisions
++;
469 /* Free the sk buffer associated with this last transmit.
471 dev_kfree_skb_irq(cep
->tx_skbuff
[cep
->skb_dirty
]);
472 cep
->skb_dirty
= (cep
->skb_dirty
+ 1) & TX_RING_MOD_MASK
;
474 /* Update pointer to next buffer descriptor to be transmitted.
476 if (bdp
->cbd_sc
& BD_ENET_TX_WRAP
)
477 bdp
= cep
->tx_bd_base
;
481 /* I don't know if we can be held off from processing these
482 * interrupts for more than one frame time. I really hope
483 * not. In such a case, we would now want to check the
484 * currently available BD (cur_tx) and determine if any
485 * buffers between the dirty_tx and cur_tx have also been
486 * sent. We would want to process anything in between that
487 * does not have BD_ENET_TX_READY set.
490 /* Since we have freed up a buffer, the ring is no longer
495 if (netif_queue_stopped(dev
)) {
496 netif_wake_queue(dev
);
500 cep
->dirty_tx
= (cbd_t
*)bdp
;
504 volatile cpm8260_t
*cp
;
506 /* Some transmit errors cause the transmitter to shut
507 * down. We now issue a restart transmit. Since the
508 * errors close the BD and update the pointers, the restart
509 * _should_ pick up without having to reset any of our
515 mk_cr_cmd(cep
->fip
->fc_cpmpage
, cep
->fip
->fc_cpmblock
,
516 0x0c, CPM_CR_RESTART_TX
) | CPM_CR_FLG
;
517 while (cp
->cp_cpcr
& CPM_CR_FLG
);
519 spin_unlock(&cep
->lock
);
522 /* Check for receive busy, i.e. packets coming but no place to
525 if (int_events
& FCC_ENET_BSY
) {
526 cep
->stats
.rx_dropped
++;
531 /* During a receive, the cur_rx points to the current incoming buffer.
532 * When we update through the ring, if the next incoming buffer has
533 * not been given to the system, we just set the empty indicator,
534 * effectively tossing the packet.
537 fcc_enet_rx(struct net_device
*dev
)
539 struct fcc_enet_private
*cep
;
544 cep
= (struct fcc_enet_private
*)dev
->priv
;
546 /* First, grab all of the stats for the incoming packet.
547 * These get messed up if we get called due to a busy condition.
552 if (bdp
->cbd_sc
& BD_ENET_RX_EMPTY
)
555 #ifndef final_version
556 /* Since we have allocated space to hold a complete frame, both
557 * the first and last indicators should be set.
559 if ((bdp
->cbd_sc
& (BD_ENET_RX_FIRST
| BD_ENET_RX_LAST
)) !=
560 (BD_ENET_RX_FIRST
| BD_ENET_RX_LAST
))
561 printk("CPM ENET: rcv is not first+last\n");
564 /* Frame too long or too short.
566 if (bdp
->cbd_sc
& (BD_ENET_RX_LG
| BD_ENET_RX_SH
))
567 cep
->stats
.rx_length_errors
++;
568 if (bdp
->cbd_sc
& BD_ENET_RX_NO
) /* Frame alignment */
569 cep
->stats
.rx_frame_errors
++;
570 if (bdp
->cbd_sc
& BD_ENET_RX_CR
) /* CRC Error */
571 cep
->stats
.rx_crc_errors
++;
572 if (bdp
->cbd_sc
& BD_ENET_RX_OV
) /* FIFO overrun */
573 cep
->stats
.rx_crc_errors
++;
575 /* Report late collisions as a frame error.
576 * On this error, the BD is closed, but we don't know what we
577 * have in the buffer. So, just drop this frame on the floor.
579 if (bdp
->cbd_sc
& BD_ENET_RX_CL
) {
580 cep
->stats
.rx_frame_errors
++;
584 /* Process the incoming frame.
586 cep
->stats
.rx_packets
++;
587 pkt_len
= bdp
->cbd_datlen
;
588 cep
->stats
.rx_bytes
+= pkt_len
;
590 /* This does 16 byte alignment, much more than we need.
591 * The packet length includes FCS, but we don't want to
592 * include that when passing upstream as it messes up
593 * bridging applications.
595 skb
= dev_alloc_skb(pkt_len
-4);
598 printk("%s: Memory squeeze, dropping packet.\n", dev
->name
);
599 cep
->stats
.rx_dropped
++;
603 skb_put(skb
,pkt_len
-4); /* Make room */
604 eth_copy_and_sum(skb
,
605 (unsigned char *)__va(bdp
->cbd_bufaddr
),
607 skb
->protocol
=eth_type_trans(skb
,dev
);
612 /* Clear the status flags for this buffer.
614 bdp
->cbd_sc
&= ~BD_ENET_RX_STATS
;
616 /* Mark the buffer empty.
618 bdp
->cbd_sc
|= BD_ENET_RX_EMPTY
;
620 /* Update BD pointer to next entry.
622 if (bdp
->cbd_sc
& BD_ENET_RX_WRAP
)
623 bdp
= cep
->rx_bd_base
;
628 cep
->cur_rx
= (cbd_t
*)bdp
;
634 fcc_enet_close(struct net_device
*dev
)
636 /* Don't know what to do yet.
638 netif_stop_queue(dev
);
643 static struct net_device_stats
*fcc_enet_get_stats(struct net_device
*dev
)
645 struct fcc_enet_private
*cep
= (struct fcc_enet_private
*)dev
->priv
;
650 /* The MII is simulated from the 8xx FEC implementation. The FCC
651 * is not responsible for the MII control/status interface.
654 fcc_enet_mii(struct net_device
*dev
)
656 struct fcc_enet_private
*fep
;
660 fep
= (struct fcc_enet_private
*)dev
->priv
;
662 ep
= &(((immap_t
*)IMAP_ADDR
)->im_cpm
.cp_fec
);
663 mii_reg
= ep
->fec_mii_data
;
666 if ((mip
= mii_head
) == NULL
) {
667 printk("MII and no head!\n");
671 if (mip
->mii_func
!= NULL
)
672 (*(mip
->mii_func
))(mii_reg
, dev
);
674 mii_head
= mip
->mii_next
;
675 mip
->mii_next
= mii_free
;
679 if ((mip
= mii_head
) != NULL
)
680 ep
->fec_mii_data
= mip
->mii_regval
;
685 mii_queue(int regval
, void (*func
)(uint
, struct net_device
*))
696 if ((mip
= mii_free
) != NULL
) {
697 mii_free
= mip
->mii_next
;
698 mip
->mii_regval
= regval
;
699 mip
->mii_func
= func
;
700 mip
->mii_next
= NULL
;
702 mii_tail
->mii_next
= mip
;
706 mii_head
= mii_tail
= mip
;
708 (&(((immap_t
*)IMAP_ADDR
)->im_cpm
.cp_fec
))->fec_mii_data
= regval
;
716 restore_flags(flags
);
721 static volatile uint full_duplex
;
724 mii_status(uint mii_reg
, struct net_device
*dev
)
726 volatile uint prev_duplex
;
728 if (((mii_reg
>> 18) & 0x1f) == 1) {
732 if (mii_reg
& 0x0004)
737 if (mii_reg
& 0x0010)
738 printk(",remote fault");
739 if (mii_reg
& 0x0020)
740 printk(",auto complete");
743 if (((mii_reg
>> 18) & 0x1f) == 0x14) {
744 /* Extended chip status register.
746 prev_duplex
= full_duplex
;
748 if (mii_reg
& 0x0800)
753 if (mii_reg
& 0x1000) {
754 printk(", Full-Duplex\n");
758 printk(", Half-Duplex\n");
762 if (prev_duplex
!= full_duplex
)
766 if (((mii_reg
>> 18) & 0x1f) == 31) {
767 /* QS6612 PHY Control/Status.
768 * OK, now we have it all, so figure out what is going on.
770 prev_duplex
= full_duplex
;
773 mii_reg
= (mii_reg
>> 2) & 7;
781 printk(", Full-Duplex\n");
785 printk(", Half-Duplex\n");
790 if (prev_duplex
!= full_duplex
)
799 mii_discover_phy3(uint mii_reg
, struct net_device
*dev
)
802 phytype
|= (mii_reg
& 0xffff);
803 printk("fec: Phy @ 0x%x, type 0x%08x\n", phyno
, phytype
);
808 mii_discover_phy(uint mii_reg
, struct net_device
*dev
)
811 if ((phytype
= (mii_reg
& 0xffff)) != 0xffff) {
813 mii_queue(mk_mii_read(3), mii_discover_phy3
);
817 mii_queue(mk_mii_phyaddr(phyno
), mii_discover_phy
);
821 printk("FEC: No PHY device found.\n");
826 mii_discover_phy_poll(fcc_info_t
*fip
)
831 for (i
=0; i
<32; i
++) {
832 rv
= mii_send_receive(fip
, mk_mii_phyaddr(i
));
833 if ((phytype
= (rv
& 0xffff)) != 0xffff) {
835 rv
= mii_send_receive(fip
, mk_mii_read(3));
837 phytype
|= (rv
& 0xffff);
838 printk("fec: Phy @ 0x%x, type 0x%08x\n", phyaddr
, phytype
);
844 mii_startup_cmds(void)
851 /* Read status registers to clear any pending interrupt.
853 mii_queue(mk_mii_read(1), mii_status
);
854 mii_queue(mk_mii_read(18), mii_status
);
856 /* Read extended chip status register.
858 mii_queue(mk_mii_read(0x14), mii_status
);
860 /* Set default operation of 100-TX....for some reason
861 * some of these bits are set on power up, which is wrong.
863 mii_queue(mk_mii_write(0x13, 0), NULL
);
865 /* Enable Link status change interrupts.
867 mii_queue(mk_mii_write(0x11, 0x0002), NULL
);
869 /* Don't advertize Full duplex.
870 mii_queue(mk_mii_write(0x04, 0x0021), NULL);
876 /* This supports the mii_link interrupt below.
877 * We should get called three times. Once for register 1, once for
878 * register 18, and once for register 20.
880 static uint mii_saved_reg1
;
883 mii_relink(uint mii_reg
, struct net_device
*dev
)
885 volatile uint prev_duplex
;
888 if (((mii_reg
>> 18) & 0x1f) == 1) {
889 /* Just save the status register and get out.
891 mii_saved_reg1
= mii_reg
;
894 if (((mii_reg
>> 18) & 0x1f) == 18) {
895 /* Not much here, but has to be read to clear the
896 * interrupt condition.
898 if ((mii_reg
& 0x8000) == 0)
899 printk("fec: re-link and no IRQ?\n");
900 if ((mii_reg
& 0x4000) == 0)
901 printk("fec: no PHY power?\n");
903 if (((mii_reg
>> 18) & 0x1f) == 20) {
904 /* Extended chip status register.
905 * OK, now we have it all, so figure out what is going on.
907 prev_duplex
= full_duplex
;
909 if (mii_saved_reg1
& 0x0004)
914 if (mii_saved_reg1
& 0x0010)
915 printk(", remote fault");
916 if (mii_saved_reg1
& 0x0020)
917 printk(", auto complete");
919 if (mii_reg
& 0x0800)
920 printk(", 100 Mbps");
924 if (mii_reg
& 0x1000) {
925 printk(", Full-Duplex\n");
929 printk(", Half-Duplex\n");
932 if (prev_duplex
!= full_duplex
) {
938 restore_flags(flags
);
941 if (((mii_reg
>> 18) & 0x1f) == 31) {
942 /* QS6612 PHY Control/Status.
943 * OK, now we have it all, so figure out what is going on.
945 prev_duplex
= full_duplex
;
947 if (mii_saved_reg1
& 0x0004)
952 if (mii_saved_reg1
& 0x0010)
953 printk(", remote fault");
954 if (mii_saved_reg1
& 0x0020)
955 printk(", auto complete");
957 mii_reg
= (mii_reg
>> 2) & 7;
962 printk(", 100 Mbps");
965 printk(", Full-Duplex\n");
969 printk(", Half-Duplex\n");
974 if (prev_duplex
!= full_duplex
) {
978 restore_flags(flags
);
984 /* Set or clear the multicast filter for this adaptor.
985 * Skeleton taken from sunlance driver.
986 * The CPM Ethernet implementation allows Multicast as well as individual
987 * MAC address filtering. Some of the drivers check to make sure it is
988 * a group multicast address, and discard those that are not. I guess I
989 * will do the same for now, but just remove the test if you want
990 * individual filtering as well (do the upper net layers want or support
991 * this kind of feature?).
994 set_multicast_list(struct net_device
*dev
)
996 struct fcc_enet_private
*cep
;
997 struct dev_mc_list
*dmi
;
998 u_char
*mcptr
, *tdptr
;
999 volatile fcc_enet_t
*ep
;
1002 cep
= (struct fcc_enet_private
*)dev
->priv
;
1005 /* Get pointer to FCC area in parameter RAM.
1007 ep
= (fcc_enet_t
*)dev
->base_addr
;
1009 if (dev
->flags
&IFF_PROMISC
) {
1011 /* Log any net taps. */
1012 printk("%s: Promiscuous mode enabled.\n", dev
->name
);
1013 cep
->fccp
->fcc_fpsmr
|= FCC_PSMR_PRO
;
1016 cep
->fccp
->fcc_fpsmr
&= ~FCC_PSMR_PRO
;
1018 if (dev
->flags
& IFF_ALLMULTI
) {
1019 /* Catch all multicast addresses, so set the
1020 * filter to all 1's.
1022 ep
->fen_gaddrh
= 0xffffffff;
1023 ep
->fen_gaddrl
= 0xffffffff;
1026 /* Clear filter and add the addresses in the list.
1033 for (i
=0; i
<dev
->mc_count
; i
++) {
1035 /* Only support group multicast for now.
1037 if (!(dmi
->dmi_addr
[0] & 1))
1040 /* The address in dmi_addr is LSB first,
1041 * and taddr is MSB first. We have to
1042 * copy bytes MSB first from dmi_addr.
1044 mcptr
= (u_char
*)dmi
->dmi_addr
+ 5;
1045 tdptr
= (u_char
*)&ep
->fen_taddrh
;
1047 *tdptr
++ = *mcptr
--;
1049 /* Ask CPM to run CRC and set bit in
1052 cpmp
->cp_cpcr
= mk_cr_cmd(cep
->fip
->fc_cpmpage
,
1053 cep
->fip
->fc_cpmblock
, 0x0c,
1054 CPM_CR_SET_GADDR
) | CPM_CR_FLG
;
1056 while (cpmp
->cp_cpcr
& CPM_CR_FLG
);
1062 /* Initialize the CPM Ethernet on FCC.
1064 int __init
fec_enet_init(void)
1066 struct net_device
*dev
;
1067 struct fcc_enet_private
*cep
;
1070 volatile immap_t
*immap
;
1071 volatile iop8260_t
*io
;
1073 immap
= (immap_t
*)IMAP_ADDR
; /* and to internal registers */
1074 io
= &immap
->im_ioport
;
1076 np
= sizeof(fcc_ports
) / sizeof(fcc_info_t
);
1081 /* Allocate some private information.
1083 cep
= (struct fcc_enet_private
*)
1084 kmalloc(sizeof(*cep
), GFP_KERNEL
);
1085 __clear_user(cep
,sizeof(*cep
));
1086 spin_lock_init(&cep
->lock
);
1089 /* Create an Ethernet device instance.
1091 dev
= init_etherdev(0, 0);
1094 init_fcc_shutdown(fip
, cep
, immap
);
1095 init_fcc_ioports(fip
, io
, immap
);
1096 init_fcc_param(fip
, dev
, immap
);
1098 dev
->base_addr
= (unsigned long)(cep
->ep
);
1100 /* The CPM Ethernet specific entries in the device
1103 dev
->open
= fcc_enet_open
;
1104 dev
->hard_start_xmit
= fcc_enet_start_xmit
;
1105 dev
->tx_timeout
= fcc_enet_timeout
;
1106 dev
->watchdog_timeo
= TX_TIMEOUT
;
1107 dev
->stop
= fcc_enet_close
;
1108 dev
->get_stats
= fcc_enet_get_stats
;
1109 dev
->set_multicast_list
= set_multicast_list
;
1111 init_fcc_startup(fip
, dev
);
1113 printk("%s: FCC ENET Version 0.2, ", dev
->name
);
1115 printk("%02x:", dev
->dev_addr
[i
]);
1116 printk("%02x\n", dev
->dev_addr
[5]);
1118 /* This is just a hack for now that works only on the EST
1119 * board, or anything else that has MDIO/CK configured.
1120 * It is mainly to test the MII software clocking.
1122 mii_discover_phy_poll(fip
);
1130 /* Make sure the device is shut down during initialization.
1133 init_fcc_shutdown(fcc_info_t
*fip
, struct fcc_enet_private
*cep
,
1134 volatile immap_t
*immap
)
1136 volatile fcc_enet_t
*ep
;
1137 volatile fcc_t
*fccp
;
1139 /* Get pointer to FCC area in parameter RAM.
1141 ep
= (fcc_enet_t
*)(&immap
->im_dprambase
[fip
->fc_proff
]);
1143 /* And another to the FCC register area.
1145 fccp
= (volatile fcc_t
*)(&immap
->im_fcc
[fip
->fc_fccnum
]);
1146 cep
->fccp
= fccp
; /* Keep the pointers handy */
1149 /* Disable receive and transmit in case someone left it running.
1151 fccp
->fcc_gfmr
&= ~(FCC_GFMR_ENR
| FCC_GFMR_ENT
);
1154 /* Initialize the I/O pins for the FCC Ethernet.
1157 init_fcc_ioports(fcc_info_t
*fip
, volatile iop8260_t
*io
,
1158 volatile immap_t
*immap
)
1161 /* FCC1 pins are on port A/C. FCC2/3 are port B/C.
1163 if (fip
->fc_proff
== PROFF_FCC1
) {
1164 /* Configure port A and C pins for FCC1 Ethernet.
1166 io
->iop_pdira
&= ~PA1_DIRA0
;
1167 io
->iop_pdira
|= PA1_DIRA1
;
1168 io
->iop_psora
&= ~PA1_PSORA0
;
1169 io
->iop_psora
|= PA1_PSORA1
;
1170 io
->iop_ppara
|= (PA1_DIRA0
| PA1_DIRA1
);
1172 if (fip
->fc_proff
== PROFF_FCC2
) {
1173 /* Configure port B and C pins for FCC Ethernet.
1175 io
->iop_pdirb
&= ~PB2_DIRB0
;
1176 io
->iop_pdirb
|= PB2_DIRB1
;
1177 io
->iop_psorb
&= ~PB2_PSORB0
;
1178 io
->iop_psorb
|= PB2_PSORB1
;
1179 io
->iop_pparb
|= (PB2_DIRB0
| PB2_DIRB1
);
1181 if (fip
->fc_proff
== PROFF_FCC3
) {
1182 /* Configure port B and C pins for FCC Ethernet.
1184 io
->iop_pdirb
&= ~PB3_DIRB0
;
1185 io
->iop_pdirb
|= PB3_DIRB1
;
1186 io
->iop_psorb
&= ~PB3_PSORB0
;
1187 io
->iop_psorb
|= PB3_PSORB1
;
1188 io
->iop_pparb
|= (PB3_DIRB0
| PB3_DIRB1
);
1191 /* Port C has clocks......
1193 io
->iop_psorc
&= ~(fip
->fc_trxclocks
);
1194 io
->iop_pdirc
&= ~(fip
->fc_trxclocks
);
1195 io
->iop_pparc
|= fip
->fc_trxclocks
;
1197 /* ....and the MII serial clock/data.
1199 io
->iop_pdatc
|= (fip
->fc_mdio
| fip
->fc_mdck
);
1200 io
->iop_podrc
|= fip
->fc_mdio
;
1201 io
->iop_pdirc
|= (fip
->fc_mdio
| fip
->fc_mdck
);
1202 io
->iop_pparc
&= ~(fip
->fc_mdio
| fip
->fc_mdck
);
1204 /* Configure Serial Interface clock routing.
1205 * First, clear all FCC bits to zero,
1206 * then set the ones we want.
1208 immap
->im_cpmux
.cmx_fcr
&= ~(fip
->fc_clockmask
);
1209 immap
->im_cpmux
.cmx_fcr
|= fip
->fc_clockroute
;
1213 init_fcc_param(fcc_info_t
*fip
, struct net_device
*dev
,
1214 volatile immap_t
*immap
)
1217 unsigned long mem_addr
;
1220 struct fcc_enet_private
*cep
;
1221 volatile fcc_enet_t
*ep
;
1222 volatile cbd_t
*bdp
;
1223 volatile cpm8260_t
*cp
;
1225 cep
= (struct fcc_enet_private
*)(dev
->priv
);
1231 /* Zero the whole thing.....I must have missed some individually.
1232 * It works when I do this.
1234 memset((char *)ep
, 0, sizeof(fcc_enet_t
));
1236 /* Allocate space for the buffer descriptors in the DP ram.
1237 * These are relative offsets in the DP ram address space.
1238 * Initialize base addresses for the buffer descriptors.
1241 /* I really want to do this, but for some reason it doesn't
1242 * work with the data cache enabled, so I allocate from the
1243 * main memory instead.
1245 i
= m8260_cpm_dpalloc(sizeof(cbd_t
) * RX_RING_SIZE
, 8);
1246 ep
->fen_genfcc
.fcc_rbase
= (uint
)&immap
->im_dprambase
[i
];
1247 cep
->rx_bd_base
= (cbd_t
*)&immap
->im_dprambase
[i
];
1249 i
= m8260_cpm_dpalloc(sizeof(cbd_t
) * TX_RING_SIZE
, 8);
1250 ep
->fen_genfcc
.fcc_tbase
= (uint
)&immap
->im_dprambase
[i
];
1251 cep
->tx_bd_base
= (cbd_t
*)&immap
->im_dprambase
[i
];
1253 cep
->rx_bd_base
= (cbd_t
*)m8260_cpm_hostalloc(sizeof(cbd_t
) * RX_RING_SIZE
, 8);
1254 ep
->fen_genfcc
.fcc_rbase
= __pa(cep
->rx_bd_base
);
1255 cep
->tx_bd_base
= (cbd_t
*)m8260_cpm_hostalloc(sizeof(cbd_t
) * TX_RING_SIZE
, 8);
1256 ep
->fen_genfcc
.fcc_tbase
= __pa(cep
->tx_bd_base
);
1259 cep
->dirty_tx
= cep
->cur_tx
= cep
->tx_bd_base
;
1260 cep
->cur_rx
= cep
->rx_bd_base
;
1262 ep
->fen_genfcc
.fcc_rstate
= (CPMFCR_GBL
| CPMFCR_EB
) << 24;
1263 ep
->fen_genfcc
.fcc_tstate
= (CPMFCR_GBL
| CPMFCR_EB
) << 24;
1265 /* Set maximum bytes per receive buffer.
1266 * It must be a multiple of 32.
1268 ep
->fen_genfcc
.fcc_mrblr
= PKT_MAXBLR_SIZE
;
1270 /* Allocate space in the reserved FCC area of DPRAM for the
1271 * internal buffers. No one uses this space (yet), so we
1272 * can do this. Later, we will add resource management for
1275 mem_addr
= CPM_FCC_SPECIAL_BASE
+ (fip
->fc_fccnum
* 128);
1276 ep
->fen_genfcc
.fcc_riptr
= mem_addr
;
1277 ep
->fen_genfcc
.fcc_tiptr
= mem_addr
+32;
1278 ep
->fen_padptr
= mem_addr
+64;
1279 memset((char *)(&(immap
->im_dprambase
[(mem_addr
+64)])), 0x88, 32);
1281 ep
->fen_genfcc
.fcc_rbptr
= 0;
1282 ep
->fen_genfcc
.fcc_tbptr
= 0;
1283 ep
->fen_genfcc
.fcc_rcrc
= 0;
1284 ep
->fen_genfcc
.fcc_tcrc
= 0;
1285 ep
->fen_genfcc
.fcc_res1
= 0;
1286 ep
->fen_genfcc
.fcc_res2
= 0;
1288 ep
->fen_camptr
= 0; /* CAM isn't used in this driver */
1290 /* Set CRC preset and mask.
1292 ep
->fen_cmask
= 0xdebb20e3;
1293 ep
->fen_cpres
= 0xffffffff;
1295 ep
->fen_crcec
= 0; /* CRC Error counter */
1296 ep
->fen_alec
= 0; /* alignment error counter */
1297 ep
->fen_disfc
= 0; /* discard frame counter */
1298 ep
->fen_retlim
= 15; /* Retry limit threshold */
1299 ep
->fen_pper
= 0; /* Normal persistence */
1301 /* Clear hash filter tables.
1308 /* Clear the Out-of-sequence TxBD.
1310 ep
->fen_tfcstat
= 0;
1314 ep
->fen_mflr
= PKT_MAXBUF_SIZE
; /* maximum frame length register */
1315 ep
->fen_minflr
= PKT_MINBUF_SIZE
; /* minimum frame length register */
1317 /* Set Ethernet station address.
1319 * This is supplied in the board information structure, so we
1320 * copy that into the controller.
1321 * So, far we have only been given one Ethernet address. We make
1322 * it unique by setting a few bits in the upper byte of the
1323 * non-static part of the address.
1325 eap
= (unsigned char *)&(ep
->fen_paddrh
);
1326 for (i
=5; i
>=0; i
--) {
1328 dev
->dev_addr
[i
] = bd
->bi_enetaddr
[i
];
1329 dev
->dev_addr
[i
] |= (1 << (7 - fip
->fc_fccnum
));
1330 *eap
++ = dev
->dev_addr
[i
];
1333 *eap
++ = dev
->dev_addr
[i
] = bd
->bi_enetaddr
[i
];
1341 ep
->fen_maxd1
= PKT_MAXDMA_SIZE
; /* maximum DMA1 length */
1342 ep
->fen_maxd2
= PKT_MAXDMA_SIZE
; /* maximum DMA2 length */
1344 /* Clear stat counters, in case we ever enable RMON.
1361 ep
->fen_rfthr
= 0; /* Suggested by manual */
1365 /* Now allocate the host memory pages and initialize the
1366 * buffer descriptors.
1368 bdp
= cep
->tx_bd_base
;
1369 for (i
=0; i
<TX_RING_SIZE
; i
++) {
1371 /* Initialize the BD for every fragment in the page.
1374 bdp
->cbd_datlen
= 0;
1375 bdp
->cbd_bufaddr
= 0;
1379 /* Set the last buffer to wrap.
1382 bdp
->cbd_sc
|= BD_SC_WRAP
;
1384 bdp
= cep
->rx_bd_base
;
1385 for (i
=0; i
<FCC_ENET_RX_PAGES
; i
++) {
1389 mem_addr
= __get_free_page(GFP_KERNEL
);
1391 /* Initialize the BD for every fragment in the page.
1393 for (j
=0; j
<FCC_ENET_RX_FRPPG
; j
++) {
1394 bdp
->cbd_sc
= BD_ENET_RX_EMPTY
| BD_ENET_RX_INTR
;
1395 bdp
->cbd_datlen
= 0;
1396 bdp
->cbd_bufaddr
= __pa(mem_addr
);
1397 mem_addr
+= FCC_ENET_RX_FRSIZE
;
1402 /* Set the last buffer to wrap.
1405 bdp
->cbd_sc
|= BD_SC_WRAP
;
1407 /* Let's re-initialize the channel now. We have to do it later
1408 * than the manual describes because we have just now finished
1409 * the BD initialization.
1411 cp
->cp_cpcr
= mk_cr_cmd(fip
->fc_cpmpage
, fip
->fc_cpmblock
, 0x0c,
1412 CPM_CR_INIT_TRX
) | CPM_CR_FLG
;
1413 while (cp
->cp_cpcr
& CPM_CR_FLG
);
1415 cep
->skb_cur
= cep
->skb_dirty
= 0;
1421 init_fcc_startup(fcc_info_t
*fip
, struct net_device
*dev
)
1423 volatile fcc_t
*fccp
;
1424 struct fcc_enet_private
*cep
;
1426 cep
= (struct fcc_enet_private
*)(dev
->priv
);
1429 fccp
->fcc_fcce
= 0xffff; /* Clear any pending events */
1431 /* Enable interrupts for transmit error, complete frame
1432 * received, and any transmit buffer we have also set the
1435 fccp
->fcc_fccm
= (FCC_ENET_TXE
| FCC_ENET_RXF
| FCC_ENET_TXB
);
1437 /* Install our interrupt handler.
1439 if (request_8xxirq(fip
->fc_interrupt
, fcc_enet_interrupt
, 0,
1441 printk("Can't get FCC IRQ %d\n", fip
->fc_interrupt
);
1443 /* Set GFMR to enable Ethernet operating mode.
1445 fccp
->fcc_gfmr
= (FCC_GFMR_TCI
| FCC_GFMR_MODE_ENET
);
1447 /* Set sync/delimiters.
1449 fccp
->fcc_fdsr
= 0xd555;
1451 /* Set protocol specific processing mode for Ethernet.
1452 * This has to be adjusted for Full Duplex operation after we can
1453 * determine how to detect that.
1455 fccp
->fcc_fpsmr
= FCC_PSMR_ENCRC
;
1457 /* And last, enable the transmit and receive processing.
1459 fccp
->fcc_gfmr
|= (FCC_GFMR_ENR
| FCC_GFMR_ENT
);
1462 /* MII command/status interface.
1463 * I'm not going to describe all of the details. You can find the
1464 * protocol definition in many other places, including the data sheet
1465 * of most PHY parts.
1466 * I wonder what "they" were thinking (maybe weren't) when they leave
1467 * the I2C in the CPM but I have to toggle these bits......
1470 mii_send_receive(fcc_info_t
*fip
, uint cmd
)
1472 unsigned long flags
;
1475 volatile immap_t
*immap
;
1476 volatile iop8260_t
*io
;
1478 immap
= (immap_t
*)IMAP_ADDR
;
1479 io
= &immap
->im_ioport
;
1481 /* When we get here, both clock and data are high, outputs.
1482 * Output is open drain.
1483 * Data transitions on high->low clock, is valid on low->high clock.
1484 * Spec says edge transitions no closer than 160 nSec, minimum clock
1485 * cycle 400 nSec. I could only manage about 500 nSec edges with
1486 * an XOR loop, so I won't worry about delays yet.
1487 * I disable interrupts during bit flipping to ensure atomic
1488 * updates of the registers. I do lots of interrupt disable/enable
1489 * to ensure we don't hang out too long with interrupts disabled.
1492 /* First, crank out 32 1-bits as preamble.
1493 * This is 64 transitions to clock the bits, with clock/data
1498 for (i
=0; i
<64; i
++) {
1499 io
->iop_pdatc
^= fip
->fc_mdck
;
1502 restore_flags(flags
);
1504 read_op
= ((cmd
& 0xf0000000) == 0x60000000);
1506 /* We return the command word on a write op, or the command portion
1507 * plus the new data on a read op. This is what the 8xx FEC does,
1508 * and it allows the functions to simply look at the returned value
1509 * and know the PHY/register as well.
1514 retval
= (cmd
>> 16);
1516 /* Clock out the first 16 MS bits of the command.
1520 for (i
=0; i
<16; i
++) {
1521 io
->iop_pdatc
&= ~(fip
->fc_mdck
);
1522 if (cmd
& 0x80000000)
1523 io
->iop_pdatc
|= fip
->fc_mdio
;
1525 io
->iop_pdatc
&= ~(fip
->fc_mdio
);
1527 io
->iop_pdatc
|= fip
->fc_mdck
;
1531 /* Do the turn-around. If read op, we make the IO and input.
1532 * If write op, do the 1/0 thing.
1534 io
->iop_pdatc
&= ~(fip
->fc_mdck
);
1536 io
->iop_pdirc
&= ~(fip
->fc_mdio
);
1538 io
->iop_pdatc
|= fip
->fc_mdio
;
1539 io
->iop_pdatc
|= fip
->fc_mdck
;
1541 /* I do this mainly to get just a little delay.
1543 restore_flags(flags
);
1546 io
->iop_pdatc
&= ~(fip
->fc_mdck
);
1547 io
->iop_pdirc
&= ~(fip
->fc_mdio
);
1548 io
->iop_pdatc
|= fip
->fc_mdck
;
1550 restore_flags(flags
);
1554 /* For read, clock in 16 bits. For write, clock out
1558 io
->iop_pdatc
&= ~(fip
->fc_mdck
);
1560 for (i
=0; i
<16; i
++) {
1561 io
->iop_pdatc
|= fip
->fc_mdck
;
1564 if (io
->iop_pdatc
& fip
->fc_mdio
)
1566 io
->iop_pdatc
&= ~(fip
->fc_mdck
);
1571 for (i
=0; i
<16; i
++) {
1572 io
->iop_pdatc
&= ~(fip
->fc_mdck
);
1573 if (cmd
& 0x80000000)
1574 io
->iop_pdatc
|= fip
->fc_mdio
;
1576 io
->iop_pdatc
&= ~(fip
->fc_mdio
);
1578 io
->iop_pdatc
|= fip
->fc_mdck
;
1581 io
->iop_pdatc
&= ~(fip
->fc_mdck
);
1583 restore_flags(flags
);
1585 /* Some diagrams show two 1 bits for "idle". I don't know if
1586 * this is really necessary or if it was just to indicate nothing
1587 * is going to happen for a while.
1588 * Make the data pin an output, set the data high, and clock it.
1592 io
->iop_pdatc
|= fip
->fc_mdio
;
1593 io
->iop_pdirc
|= fip
->fc_mdio
;
1595 io
->iop_pdatc
^= fip
->fc_mdck
;
1596 restore_flags(flags
);
1598 /* We exit with the same conditions as entry.