- Linus: drop support for old-style Makefiles entirely. Big.
[davej-history.git] / arch / arm / lib / csumpartialcopy.S
blob005bc93329c3cfab5bee85135b21c9e72b9e2d0f
1 /*
2  *  linux/arch/arm/lib/csumpartialcopy.S
3  *
4  *  Copyright (C) 1995-1998 Russell King
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 #include <linux/linkage.h>
11 #include <asm/assembler.h>
13                 .text
15 /* Function: __u32 csum_partial_copy_nocheck(const char *src, char *dst, int len, __u32 sum)
16  * Params  : r0 = src, r1 = dst, r2 = len, r3 = checksum
17  * Returns : r0 = new checksum
18  */
20                 .macro  save_regs
21                 stmfd   sp!, {r4 - r8, fp, ip, lr, pc}
22                 .endm
24                 .macro  load_regs,flags
25                 LOADREGS(\flags,fp,{r4 - r8, fp, sp, pc})
26                 .endm
28                 .macro  load1b, reg1
29                 ldrb    \reg1, [r0], #1
30                 .endm
32                 .macro  load2b, reg1, reg2
33                 ldrb    \reg1, [r0], #1
34                 ldrb    \reg2, [r0], #1
35                 .endm
37                 .macro  load1l, reg1
38                 ldr     \reg1, [r0], #4
39                 .endm
41                 .macro  load2l, reg1, reg2
42                 ldr     \reg1, [r0], #4
43                 ldr     \reg2, [r0], #4
44                 .endm
46                 .macro  load4l, reg1, reg2, reg3, reg4
47                 ldmia   r0!, {\reg1, \reg2, \reg3, \reg4}
48                 .endm
50 ENTRY(csum_partial_copy_nocheck)
51                 mov     ip, sp
52                 save_regs
53                 sub     fp, ip, #4
54                 cmp     r2, #4
55                 blt     .too_small
56                 tst     r1, #2                  @ Test destination alignment
57                 beq     .dst_aligned
58                 load2b  ip, r8
59                 subs    r2, r2, #2              @ We do not know if SRC is aligned...
60                 orr     ip, ip, r8, lsl #8
61                 adds    r3, r3, ip
62                 adcs    r3, r3, #0
63                 strb    ip, [r1], #1
64                 mov     ip, ip, lsr #8
65                 strb    ip, [r1], #1            @ Destination now aligned
66 .dst_aligned:   tst     r0, #3
67                 bne     .src_not_aligned
68                 adds    r3, r3, #0
69                 bics    ip, r2, #15             @ Routine for src & dst aligned
70                 beq     2f
71 1:              load4l  r4, r5, r6, r7
72                 stmia   r1!, {r4, r5, r6, r7}
73                 adcs    r3, r3, r4
74                 adcs    r3, r3, r5
75                 adcs    r3, r3, r6
76                 adcs    r3, r3, r7
77                 sub     ip, ip, #16
78                 teq     ip, #0
79                 bne     1b
80 2:              ands    ip, r2, #12
81                 beq     4f
82                 tst     ip, #8
83                 beq     3f
84                 load2l  r4, r5
85                 stmia   r1!, {r4, r5}
86                 adcs    r3, r3, r4
87                 adcs    r3, r3, r5
88                 tst     ip, #4
89                 beq     4f
90 3:              load1l  r4
91                 str     r4, [r1], #4
92                 adcs    r3, r3, r4
93 4:              ands    r2, r2, #3
94                 adceq   r0, r3, #0
95                 load_regs       eqea
96                 load1l  r4
97                 tst     r2, #2
98                 beq     .exit
99                 adcs    r3, r3, r4, lsl #16
100                 strb    r4, [r1], #1
101                 mov     r4, r4, lsr #8
102                 strb    r4, [r1], #1
103                 mov     r4, r4, lsr #8
104 .exit:          tst     r2, #1
105                 strneb  r4, [r1], #1
106                 andne   r4, r4, #255
107                 adcnes  r3, r3, r4
108                 adcs    r0, r3, #0
109                 load_regs       ea
111 .too_small:     teq     r2, #0
112                 load_regs       eqea
113                 cmp     r2, #2
114                 blt     .too_small1
115                 load2b  ip, r8
116                 orr     ip, ip, r8, lsl #8
117                 adds    r3, r3, ip
118                 strb    ip, [r1], #1
119                 strb    r8, [r1], #1
120                 tst     r2, #1
121 .too_small1:                            @ C = 0
122                 beq     .csum_exit
123                 load1b  ip
124                 strb    ip, [r1], #1
125                 adcs    r3, r3, ip
126 .csum_exit:     adc     r0, r3, #0
127                 load_regs       ea
129 .src_not_aligned:
130                 cmp     r2, #4
131                 blt     .too_small
132                 and     ip, r0, #3
133                 bic     r0, r0, #3
134                 load1l  r4
135                 cmp     ip, #2
136                 beq     .src2_aligned
137                 bhi     .src3_aligned
138                 mov     r4, r4, lsr #8
139                 adds    r3, r3, #0
140                 bics    ip, r2, #15
141                 beq     2f
142 1:              load4l  r5, r6, r7, r8
143                 orr     r4, r4, r5, lsl #24
144                 mov     r5, r5, lsr #8
145                 orr     r5, r5, r6, lsl #24
146                 mov     r6, r6, lsr #8
147                 orr     r6, r6, r7, lsl #24
148                 mov     r7, r7, lsr #8
149                 orr     r7, r7, r8, lsl #24
150                 stmia   r1!, {r4, r5, r6, r7}
151                 adcs    r3, r3, r4
152                 adcs    r3, r3, r5
153                 adcs    r3, r3, r6
154                 adcs    r3, r3, r7
155                 mov     r4, r8, lsr #8
156                 sub     ip, ip, #16
157                 teq     ip, #0
158                 bne     1b
159 2:              ands    ip, r2, #12
160                 beq     4f
161                 tst     ip, #8
162                 beq     3f
163                 load2l  r5, r6
164                 orr     r4, r4, r5, lsl #24
165                 mov     r5, r5, lsr #8
166                 orr     r5, r5, r6, lsl #24
167                 stmia   r1!, {r4, r5}
168                 adcs    r3, r3, r4
169                 adcs    r3, r3, r5
170                 mov     r4, r6, lsr #8
171                 tst     ip, #4
172                 beq     4f
173 3:              load1l  r5
174                 orr     r4, r4, r5, lsl #24
175                 str     r4, [r1], #4
176                 adcs    r3, r3, r4
177                 mov     r4, r5, lsr #8
178 4:              ands    r2, r2, #3
179                 adceq   r0, r3, #0
180                 load_regs       eqea
181                 tst     r2, #2
182                 beq     .exit
183                 adcs    r3, r3, r4, lsl #16
184                 strb    r4, [r1], #1
185                 mov     r4, r4, lsr #8
186                 strb    r4, [r1], #1
187                 mov     r4, r4, lsr #8
188                 b       .exit
190 .src2_aligned:  mov     r4, r4, lsr #16
191                 adds    r3, r3, #0
192                 bics    ip, r2, #15
193                 beq     2f
194 1:              load4l  r5, r6, r7, r8
195                 orr     r4, r4, r5, lsl #16
196                 mov     r5, r5, lsr #16
197                 orr     r5, r5, r6, lsl #16
198                 mov     r6, r6, lsr #16
199                 orr     r6, r6, r7, lsl #16
200                 mov     r7, r7, lsr #16
201                 orr     r7, r7, r8, lsl #16
202                 stmia   r1!, {r4, r5, r6, r7}
203                 adcs    r3, r3, r4
204                 adcs    r3, r3, r5
205                 adcs    r3, r3, r6
206                 adcs    r3, r3, r7
207                 mov     r4, r8, lsr #16
208                 sub     ip, ip, #16
209                 teq     ip, #0
210                 bne     1b
211 2:              ands    ip, r2, #12
212                 beq     4f
213                 tst     ip, #8
214                 beq     3f
215                 load2l  r5, r6
216                 orr     r4, r4, r5, lsl #16
217                 mov     r5, r5, lsr #16
218                 orr     r5, r5, r6, lsl #16
219                 stmia   r1!, {r4, r5}
220                 adcs    r3, r3, r4
221                 adcs    r3, r3, r5
222                 mov     r4, r6, lsr #16
223                 tst     ip, #4
224                 beq     4f
225 3:              load1l  r5
226                 orr     r4, r4, r5, lsl #16
227                 str     r4, [r1], #4
228                 adcs    r3, r3, r4
229                 mov     r4, r5, lsr #16
230 4:              ands    r2, r2, #3
231                 adceq   r0, r3, #0
232                 load_regs       eqea
233                 tst     r2, #2
234                 beq     .exit
235                 adcs    r3, r3, r4, lsl #16
236                 strb    r4, [r1], #1
237                 mov     r4, r4, lsr #8
238                 strb    r4, [r1], #1
239                 tst     r2, #1
240                 adceq   r0, r3, #0
241                 load_regs       eqea
242                 load1b  r4
243                 b       .exit
245 .src3_aligned:  mov     r4, r4, lsr #24
246                 adds    r3, r3, #0
247                 bics    ip, r2, #15
248                 beq     2f
249 1:              load4l  r5, r6, r7, r8
250                 orr     r4, r4, r5, lsl #8
251                 mov     r5, r5, lsr #24
252                 orr     r5, r5, r6, lsl #8
253                 mov     r6, r6, lsr #24
254                 orr     r6, r6, r7, lsl #8
255                 mov     r7, r7, lsr #24
256                 orr     r7, r7, r8, lsl #8
257                 stmia   r1!, {r4, r5, r6, r7}
258                 adcs    r3, r3, r4
259                 adcs    r3, r3, r5
260                 adcs    r3, r3, r6
261                 adcs    r3, r3, r7
262                 mov     r4, r8, lsr #24
263                 sub     ip, ip, #16
264                 teq     ip, #0
265                 bne     1b
266 2:              ands    ip, r2, #12
267                 beq     4f
268                 tst     ip, #8
269                 beq     3f
270                 load2l  r5, r6
271                 orr     r4, r4, r5, lsl #8
272                 mov     r5, r5, lsr #24
273                 orr     r5, r5, r6, lsl #8
274                 stmia   r1!, {r4, r5}
275                 adcs    r3, r3, r4
276                 adcs    r3, r3, r5
277                 mov     r4, r6, lsr #24
278                 tst     ip, #4
279                 beq     4f
280 3:              load1l  r5
281                 orr     r4, r4, r5, lsl #8
282                 str     r4, [r1], #4
283                 adcs    r3, r3, r4
284                 mov     r4, r5, lsr #24
285 4:              ands    r2, r2, #3
286                 adceq   r0, r3, #0
287                 load_regs       eqea
288                 tst     r2, #2
289                 beq     .exit
290                 adcs    r3, r3, r4, lsl #16
291                 strb    r4, [r1], #1
292                 load1l  r4
293                 strb    r4, [r1], #1
294                 adcs    r3, r3, r4, lsl #24
295                 mov     r4, r4, lsr #8
296                 b       .exit