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- Andries Brouwer: final isofs pieces.
[davej-history.git] / drivers / isdn / hisax / bkm_a8.c
blob45011d356a7fc3f17b2ad35f3952ea4e301a72f0
1 /* $Id: bkm_a8.c,v 1.14.6.2 2000/11/29 16:00:14 kai Exp $
2 * bkm_a8.c low level stuff for Scitel Quadro (4*S0, passive)
3 * derived from the original file sedlbauer.c
4 * derived from the original file niccy.c
5 * derived from the original file netjet.c
6 *
7 * Author Roland Klabunde (R.Klabunde@Berkom.de)
8 *
9 * This file is (c) under GNU PUBLIC LICENSE
10 *
11 */
12 #define __NO_VERSION__
13
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include "hisax.h"
17 #include "isac.h"
18 #include "ipac.h"
19 #include "hscx.h"
20 #include "isdnl1.h"
21 #include <linux/pci.h>
22 #include "bkm_ax.h"
23
24 #if CONFIG_PCI
25
26 #define ATTEMPT_PCI_REMAPPING /* Required for PLX rev 1 */
27
28 extern const char *CardType[];
29
30 const char sct_quadro_revision[] = "$Revision: 1.14.6.2 $";
31
32 static const char *sct_quadro_subtypes[] =
33 {
34 "",
35 "#1",
36 "#2",
37 "#3",
38 "#4"
39 };
40
41
42 #define wordout(addr,val) outw(val,addr)
43 #define wordin(addr) inw(addr)
44
45 static inline u_char
46 readreg(unsigned int ale, unsigned int adr, u_char off)
47 {
48 register u_char ret;
49 long flags;
50 save_flags(flags);
51 cli();
52 wordout(ale, off);
53 ret = wordin(adr) & 0xFF;
54 restore_flags(flags);
55 return (ret);
56 }
57
58 static inline void
59 readfifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
60 {
61 /* fifo read without cli because it's allready done */
62 int i;
63 wordout(ale, off);
64 for (i = 0; i < size; i++)
65 data[i] = wordin(adr) & 0xFF;
66 }
67
68
69 static inline void
70 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
71 {
72 long flags;
73 save_flags(flags);
74 cli();
75 wordout(ale, off);
76 wordout(adr, data);
77 restore_flags(flags);
78 }
79
80 static inline void
81 writefifo(unsigned int ale, unsigned int adr, u_char off, u_char * data, int size)
82 {
83 /* fifo write without cli because it's allready done */
84 int i;
85 wordout(ale, off);
86 for (i = 0; i < size; i++)
87 wordout(adr, data[i]);
88 }
89
90 /* Interface functions */
91
92 static u_char
93 ReadISAC(struct IsdnCardState *cs, u_char offset)
94 {
95 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80));
96 }
97
98 static void
99 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
100 {
101 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value);
102 }
103
104 static void
105 ReadISACfifo(struct IsdnCardState *cs, u_char * data, int size)
106 {
107 readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
108 }
109
110 static void
111 WriteISACfifo(struct IsdnCardState *cs, u_char * data, int size)
112 {
113 writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
114 }
115
116
117 static u_char
118 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
119 {
120 return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0)));
121 }
122
123 static void
124 WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
125 {
126 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value);
127 }
128
129 /* Set the specific ipac to active */
130 static void
131 set_ipac_active(struct IsdnCardState *cs, u_int active)
132 {
133 /* set irq mask */
134 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK,
135 active ? 0xc0 : 0xff);
136 }
137
138 /*
139 * fast interrupt HSCX stuff goes here
140 */
141
142 #define READHSCX(cs, nr, reg) readreg(cs->hw.ax.base, \
143 cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0))
144 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \
145 cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0), data)
146 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ax.base, \
147 cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
148 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ax.base, \
149 cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
150
151 #include "hscx_irq.c"
152
153 static void
154 bkm_interrupt_ipac(int intno, void *dev_id, struct pt_regs *regs)
155 {
156 struct IsdnCardState *cs = dev_id;
157 u_char ista, val, icnt = 5;
158
159 if (!cs) {
160 printk(KERN_WARNING "HiSax: Scitel Quadro: Spurious interrupt!\n");
161 return;
162 }
163 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
164 if (!(ista & 0x3f)) /* not this IPAC */
165 return;
166 Start_IPAC:
167 if (cs->debug & L1_DEB_IPAC)
168 debugl1(cs, "IPAC ISTA %02X", ista);
169 if (ista & 0x0f) {
170 val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40);
171 if (ista & 0x01)
172 val |= 0x01;
173 if (ista & 0x04)
174 val |= 0x02;
175 if (ista & 0x08)
176 val |= 0x04;
177 if (val) {
178 hscx_int_main(cs, val);
179 }
180 }
181 if (ista & 0x20) {
182 val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80);
183 if (val) {
184 isac_interrupt(cs, val);
185 }
186 }
187 if (ista & 0x10) {
188 val = 0x01;
189 isac_interrupt(cs, val);
190 }
191 ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
192 if ((ista & 0x3f) && icnt) {
193 icnt--;
194 goto Start_IPAC;
195 }
196 if (!icnt)
197 printk(KERN_WARNING "HiSax: %s (%s) IRQ LOOP\n",
198 CardType[cs->typ],
199 sct_quadro_subtypes[cs->subtyp]);
200 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF);
201 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0);
202 }
203
204
205 void
206 release_io_sct_quadro(struct IsdnCardState *cs)
207 {
208 release_region(cs->hw.ax.base & 0xffffffc0, 256);
209 if (cs->subtyp == SCT_1)
210 release_region(cs->hw.ax.plx_adr, 256);
211 }
212
213 static void
214 enable_bkm_int(struct IsdnCardState *cs, unsigned bEnable)
215 {
216 if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
217 if (bEnable)
218 wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) | 0x41));
219 else
220 wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) & ~0x41));
221 }
222 }
223
224 static void
225 reset_bkm(struct IsdnCardState *cs)
226 {
227 long flags;
228
229 if (cs->subtyp == SCT_1) {
230 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) & ~4));
231 save_flags(flags);
232 sti();
233 set_current_state(TASK_UNINTERRUPTIBLE);
234 schedule_timeout((10 * HZ) / 1000);
235 /* Remove the soft reset */
236 wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) | 4));
237 set_current_state(TASK_UNINTERRUPTIBLE);
238 schedule_timeout((10 * HZ) / 1000);
239 restore_flags(flags);
240 }
241 }
242
243 static int
244 BKM_card_msg(struct IsdnCardState *cs, int mt, void *arg)
245 {
246 switch (mt) {
247 case CARD_RESET:
248 /* Disable ints */
249 set_ipac_active(cs, 0);
250 enable_bkm_int(cs, 0);
251 reset_bkm(cs);
252 return (0);
253 case CARD_RELEASE:
254 /* Sanity */
255 set_ipac_active(cs, 0);
256 enable_bkm_int(cs, 0);
257 release_io_sct_quadro(cs);
258 return (0);
259 case CARD_INIT:
260 cs->debug |= L1_DEB_IPAC;
261 set_ipac_active(cs, 1);
262 inithscxisac(cs, 3);
263 /* Enable ints */
264 enable_bkm_int(cs, 1);
265 return (0);
266 case CARD_TEST:
267 return (0);
268 }
269 return (0);
270 }
271
272 int __init
273 sct_alloc_io(u_int adr, u_int len)
274 {
275 if (check_region(adr, len)) {
276 printk(KERN_WARNING
277 "HiSax: Scitel port %#x-%#x already in use\n",
278 adr, adr + len);
279 return (1);
280 } else {
281 request_region(adr, len, "scitel");
282 }
283 return(0);
284 }
285
286 static struct pci_dev *dev_a8 __initdata = NULL;
287 static u16 sub_vendor_id __initdata = 0;
288 static u16 sub_sys_id __initdata = 0;
289 static u_char pci_bus __initdata = 0;
290 static u_char pci_device_fn __initdata = 0;
291 static u_char pci_irq __initdata = 0;
292
293 #endif /* CONFIG_PCI */
294
295 int __init
296 setup_sct_quadro(struct IsdnCard *card)
297 {
298 #if CONFIG_PCI
299 struct IsdnCardState *cs = card->cs;
300 char tmp[64];
301 u_char pci_rev_id;
302 u_int found = 0;
303 u_int pci_ioaddr1, pci_ioaddr2, pci_ioaddr3, pci_ioaddr4, pci_ioaddr5;
304
305 strcpy(tmp, sct_quadro_revision);
306 printk(KERN_INFO "HiSax: T-Berkom driver Rev. %s\n", HiSax_getrev(tmp));
307 if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
308 cs->subtyp = SCT_1; /* Preset */
309 } else
310 return (0);
311
312 /* Identify subtype by para[0] */
313 if (card->para[0] >= SCT_1 && card->para[0] <= SCT_4)
314 cs->subtyp = card->para[0];
315 else {
316 printk(KERN_WARNING "HiSax: %s: Invalid subcontroller in configuration, default to 1\n",
317 CardType[card->typ]);
318 return (0);
319 }
320 if ((cs->subtyp != SCT_1) && ((sub_sys_id != PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) ||
321 (sub_vendor_id != PCI_VENDOR_ID_BERKOM)))
322 return (0);
323 if (cs->subtyp == SCT_1) {
324 if (!pci_present()) {
325 printk(KERN_ERR "bkm_a4t: no PCI bus present\n");
326 return (0);
327 }
328 while ((dev_a8 = pci_find_device(PCI_VENDOR_ID_PLX,
329 PCI_DEVICE_ID_PLX_9050, dev_a8))) {
330
331 sub_vendor_id = dev_a8->subsystem_vendor;
332 sub_sys_id = dev_a8->subsystem_device;
333 if ((sub_sys_id == PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) &&
334 (sub_vendor_id == PCI_VENDOR_ID_BERKOM)) {
335 if (pci_enable_device(dev_a8))
336 return(0);
337 pci_ioaddr1 = pci_resource_start(dev_a8, 1);
338 pci_irq = dev_a8->irq;
339 pci_bus = dev_a8->bus->number;
340 pci_device_fn = dev_a8->devfn;
341 found = 1;
342 break;
343 }
344 }
345 if (!found) {
346 printk(KERN_WARNING "HiSax: %s (%s): Card not found\n",
347 CardType[card->typ],
348 sct_quadro_subtypes[cs->subtyp]);
349 return (0);
350 }
351 #ifdef ATTEMPT_PCI_REMAPPING
352 /* HACK: PLX revision 1 bug: PLX address bit 7 must not be set */
353 pcibios_read_config_byte(pci_bus, pci_device_fn,
354 PCI_REVISION_ID, &pci_rev_id);
355 if ((pci_ioaddr1 & 0x80) && (pci_rev_id == 1)) {
356 printk(KERN_WARNING "HiSax: %s (%s): PLX rev 1, remapping required!\n",
357 CardType[card->typ],
358 sct_quadro_subtypes[cs->subtyp]);
359 /* Restart PCI negotiation */
360 pcibios_write_config_dword(pci_bus, pci_device_fn,
361 PCI_BASE_ADDRESS_1, (u_int) - 1);
362 /* Move up by 0x80 byte */
363 pci_ioaddr1 += 0x80;
364 pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
365 pcibios_write_config_dword(pci_bus, pci_device_fn,
366 PCI_BASE_ADDRESS_1, pci_ioaddr1);
367 dev_a8->resource[ 1].start = pci_ioaddr1;
368 }
369 #endif /* End HACK */
370 }
371 if (!pci_irq) { /* IRQ range check ?? */
372 printk(KERN_WARNING "HiSax: %s (%s): No IRQ\n",
373 CardType[card->typ],
374 sct_quadro_subtypes[cs->subtyp]);
375 return (0);
376 }
377 pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_1, &pci_ioaddr1);
378 pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_2, &pci_ioaddr2);
379 pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_3, &pci_ioaddr3);
380 pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_4, &pci_ioaddr4);
381 pcibios_read_config_dword(pci_bus, pci_device_fn, PCI_BASE_ADDRESS_5, &pci_ioaddr5);
382 if (!pci_ioaddr1 || !pci_ioaddr2 || !pci_ioaddr3 || !pci_ioaddr4 || !pci_ioaddr5) {
383 printk(KERN_WARNING "HiSax: %s (%s): No IO base address(es)\n",
384 CardType[card->typ],
385 sct_quadro_subtypes[cs->subtyp]);
386 return (0);
387 }
388 pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
389 pci_ioaddr2 &= PCI_BASE_ADDRESS_IO_MASK;
390 pci_ioaddr3 &= PCI_BASE_ADDRESS_IO_MASK;
391 pci_ioaddr4 &= PCI_BASE_ADDRESS_IO_MASK;
392 pci_ioaddr5 &= PCI_BASE_ADDRESS_IO_MASK;
393 /* Take over */
394 cs->irq = pci_irq;
395 cs->irq_flags |= SA_SHIRQ;
396 /* pci_ioaddr1 is unique to all subdevices */
397 /* pci_ioaddr2 is for the fourth subdevice only */
398 /* pci_ioaddr3 is for the third subdevice only */
399 /* pci_ioaddr4 is for the second subdevice only */
400 /* pci_ioaddr5 is for the first subdevice only */
401 cs->hw.ax.plx_adr = pci_ioaddr1;
402 /* Enter all ipac_base addresses */
403 switch(cs->subtyp) {
404 case 1:
405 cs->hw.ax.base = pci_ioaddr5 + 0x00;
406 if (sct_alloc_io(pci_ioaddr1, 256))
407 return(0);
408 if (sct_alloc_io(pci_ioaddr5, 256))
409 return(0);
410 /* disable all IPAC */
411 writereg(pci_ioaddr5, pci_ioaddr5 + 4,
412 IPAC_MASK, 0xFF);
413 writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c,
414 IPAC_MASK, 0xFF);
415 writereg(pci_ioaddr3 + 0x10, pci_ioaddr3 + 0x14,
416 IPAC_MASK, 0xFF);
417 writereg(pci_ioaddr2 + 0x20, pci_ioaddr2 + 0x24,
418 IPAC_MASK, 0xFF);
419 break;
420 case 2:
421 cs->hw.ax.base = pci_ioaddr4 + 0x08;
422 if (sct_alloc_io(pci_ioaddr4, 256))
423 return(0);
424 break;
425 case 3:
426 cs->hw.ax.base = pci_ioaddr3 + 0x10;
427 if (sct_alloc_io(pci_ioaddr3, 256))
428 return(0);
429 break;
430 case 4:
431 cs->hw.ax.base = pci_ioaddr2 + 0x20;
432 if (sct_alloc_io(pci_ioaddr2, 256))
433 return(0);
434 break;
435 }
436 /* For isac and hscx data path */
437 cs->hw.ax.data_adr = cs->hw.ax.base + 4;
438
439 printk(KERN_INFO "HiSax: %s (%s) configured at 0x%.4X, 0x%.4X, 0x%.4X and IRQ %d\n",
440 CardType[card->typ],
441 sct_quadro_subtypes[cs->subtyp],
442 cs->hw.ax.plx_adr,
443 cs->hw.ax.base,
444 cs->hw.ax.data_adr,
445 cs->irq);
446
447 test_and_set_bit(HW_IPAC, &cs->HW_Flags);
448
449 cs->readisac = &ReadISAC;
450 cs->writeisac = &WriteISAC;
451 cs->readisacfifo = &ReadISACfifo;
452 cs->writeisacfifo = &WriteISACfifo;
453
454 cs->BC_Read_Reg = &ReadHSCX;
455 cs->BC_Write_Reg = &WriteHSCX;
456 cs->BC_Send_Data = &hscx_fill_fifo;
457 cs->cardmsg = &BKM_card_msg;
458 cs->irq_func = &bkm_interrupt_ipac;
459
460 printk(KERN_INFO "HiSax: %s (%s): IPAC Version %d\n",
461 CardType[card->typ],
462 sct_quadro_subtypes[cs->subtyp],
463 readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));
464 return (1);
465 #else
466 printk(KERN_ERR "HiSax: bkm_a8 only supported on PCI Systems\n");
467 #endif /* CONFIG_PCI */
468 }
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