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- Andries Brouwer: final isofs pieces.
[davej-history.git] / drivers / char / drm / mga_drv.h
blob59bb9c24773a415f71d9dbd1c07d26d89b15d65b
1 /* mga_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
28 * Jeff Hartmann <jhartmann@valinux.com>
29 *
30 */
31
32 #ifndef _MGA_DRV_H_
33 #define _MGA_DRV_H_
34
35 #define MGA_BUF_IN_USE 0
36 #define MGA_BUF_SWAP_PENDING 1
37 #define MGA_BUF_FORCE_FIRE 2
38 #define MGA_BUF_NEEDS_OVERFLOW 3
39
40 typedef struct {
41 long buffer_status; /* long req'd for set_bit() --RR */
42 int num_dwords;
43 int max_dwords;
44 u32 *current_dma_ptr;
45 u32 *head;
46 u32 phys_head;
47 unsigned int prim_age;
48 int sec_used;
49 int idx;
50 } drm_mga_prim_buf_t;
51
52 typedef struct _drm_mga_freelist {
53 __volatile__ unsigned int age;
54 drm_buf_t *buf;
55 struct _drm_mga_freelist *next;
56 struct _drm_mga_freelist *prev;
57 } drm_mga_freelist_t;
58
59 #define MGA_IN_DISPATCH 0
60 #define MGA_IN_FLUSH 1
61 #define MGA_IN_WAIT 2
62 #define MGA_IN_GETBUF 3
63
64 typedef struct _drm_mga_private {
65 long dispatch_status; /* long req'd for set_bit() --RR */
66 unsigned int next_prim_age;
67 __volatile__ unsigned int last_prim_age;
68 int reserved_map_idx;
69 int buffer_map_idx;
70 drm_mga_sarea_t *sarea_priv;
71 int primary_size;
72 int warp_ucode_size;
73 int chipset;
74 unsigned int frontOffset;
75 unsigned int backOffset;
76 unsigned int depthOffset;
77 unsigned int textureOffset;
78 unsigned int textureSize;
79 int cpp;
80 unsigned int stride;
81 int sgram;
82 int use_agp;
83 drm_mga_warp_index_t WarpIndex[MGA_MAX_G400_PIPES];
84 unsigned int WarpPipe;
85 unsigned int vertexsize;
86 atomic_t pending_bufs;
87 void *status_page;
88 unsigned long real_status_page;
89 u8 *ioremap;
90 drm_mga_prim_buf_t **prim_bufs;
91 drm_mga_prim_buf_t *next_prim;
92 drm_mga_prim_buf_t *last_prim;
93 drm_mga_prim_buf_t *current_prim;
94 int current_prim_idx;
95 drm_mga_freelist_t *head;
96 drm_mga_freelist_t *tail;
97 wait_queue_head_t flush_queue; /* Processes waiting until flush */
98 wait_queue_head_t wait_queue; /* Processes waiting until interrupt */
99 wait_queue_head_t buf_queue; /* Processes waiting for a free buf */
100 /* Some validated register values:
101 */
102 u32 mAccess;
103 } drm_mga_private_t;
104
105 /* mga_drv.c */
106 extern int mga_version(struct inode *inode, struct file *filp,
107 unsigned int cmd, unsigned long arg);
108 extern int mga_open(struct inode *inode, struct file *filp);
109 extern int mga_release(struct inode *inode, struct file *filp);
110 extern int mga_ioctl(struct inode *inode, struct file *filp,
111 unsigned int cmd, unsigned long arg);
112 extern int mga_unlock(struct inode *inode, struct file *filp,
113 unsigned int cmd, unsigned long arg);
114
115 /* mga_dma.c */
116 extern int mga_dma_schedule(drm_device_t *dev, int locked);
117 extern int mga_dma(struct inode *inode, struct file *filp,
118 unsigned int cmd, unsigned long arg);
119 extern int mga_irq_install(drm_device_t *dev, int irq);
120 extern int mga_irq_uninstall(drm_device_t *dev);
121 extern int mga_control(struct inode *inode, struct file *filp,
122 unsigned int cmd, unsigned long arg);
123 extern int mga_lock(struct inode *inode, struct file *filp,
124 unsigned int cmd, unsigned long arg);
125
126 /* mga_dma_init does init and release */
127 extern int mga_dma_init(struct inode *inode, struct file *filp,
128 unsigned int cmd, unsigned long arg);
129 extern int mga_dma_cleanup(drm_device_t *dev);
130 extern int mga_flush_ioctl(struct inode *inode, struct file *filp,
131 unsigned int cmd, unsigned long arg);
132 extern unsigned int mga_create_sync_tag(drm_device_t *dev);
133 extern drm_buf_t *mga_freelist_get(drm_device_t *dev);
134 extern int mga_freelist_put(drm_device_t *dev, drm_buf_t *buf);
135 extern int mga_advance_primary(drm_device_t *dev);
136 extern void mga_reclaim_buffers(drm_device_t *dev, pid_t pid);
137
138
139 /* mga_bufs.c */
140 extern int mga_addbufs(struct inode *inode, struct file *filp,
141 unsigned int cmd, unsigned long arg);
142 extern int mga_infobufs(struct inode *inode, struct file *filp,
143 unsigned int cmd, unsigned long arg);
144 extern int mga_markbufs(struct inode *inode, struct file *filp,
145 unsigned int cmd, unsigned long arg);
146 extern int mga_freebufs(struct inode *inode, struct file *filp,
147 unsigned int cmd, unsigned long arg);
148 extern int mga_mapbufs(struct inode *inode, struct file *filp,
149 unsigned int cmd, unsigned long arg);
150 extern int mga_addmap(struct inode *inode, struct file *filp,
151 unsigned int cmd, unsigned long arg);
152 /* mga_state.c */
153 extern int mga_clear_bufs(struct inode *inode, struct file *filp,
154 unsigned int cmd, unsigned long arg);
155 extern int mga_swap_bufs(struct inode *inode, struct file *filp,
156 unsigned int cmd, unsigned long arg);
157 extern int mga_iload(struct inode *inode, struct file *filp,
158 unsigned int cmd, unsigned long arg);
159 extern int mga_vertex(struct inode *inode, struct file *filp,
160 unsigned int cmd, unsigned long arg);
161 extern int mga_indices(struct inode *inode, struct file *filp,
162 unsigned int cmd, unsigned long arg);
163 /* mga_context.c */
164 extern int mga_resctx(struct inode *inode, struct file *filp,
165 unsigned int cmd, unsigned long arg);
166 extern int mga_addctx(struct inode *inode, struct file *filp,
167 unsigned int cmd, unsigned long arg);
168 extern int mga_modctx(struct inode *inode, struct file *filp,
169 unsigned int cmd, unsigned long arg);
170 extern int mga_getctx(struct inode *inode, struct file *filp,
171 unsigned int cmd, unsigned long arg);
172 extern int mga_switchctx(struct inode *inode, struct file *filp,
173 unsigned int cmd, unsigned long arg);
174 extern int mga_newctx(struct inode *inode, struct file *filp,
175 unsigned int cmd, unsigned long arg);
176 extern int mga_rmctx(struct inode *inode, struct file *filp,
177 unsigned int cmd, unsigned long arg);
178
179 extern int mga_context_switch(drm_device_t *dev, int old, int new);
180 extern int mga_context_switch_complete(drm_device_t *dev, int new);
181
182 #define mga_flush_write_combine() mb()
183
184 typedef enum {
185 TT_GENERAL,
186 TT_BLIT,
187 TT_VECTOR,
188 TT_VERTEX
189 } transferType_t;
190
191 typedef struct {
192 drm_mga_freelist_t *my_freelist;
193 int discard;
194 int dispatched;
195 } drm_mga_buf_priv_t;
196
197 #define DWGREG0 0x1c00
198 #define DWGREG0_END 0x1dff
199 #define DWGREG1 0x2c00
200 #define DWGREG1_END 0x2dff
201
202 #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
203 #define ADRINDEX0(r) (u8)((r - DWGREG0) >> 2)
204 #define ADRINDEX1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
205 #define ADRINDEX(r) (ISREG0(r) ? ADRINDEX0(r) : ADRINDEX1(r))
206
207 #define MGA_VERBOSE 0
208 #define MGA_NUM_PRIM_BUFS 8
209
210 #define PRIMLOCALS u8 tempIndex[4]; u32 *dma_ptr; u32 phys_head; \
211 int outcount, num_dwords
212
213 #define PRIM_OVERFLOW(dev, dev_priv, length) do { \
214 drm_mga_prim_buf_t *tmp_buf = \
215 dev_priv->prim_bufs[dev_priv->current_prim_idx]; \
216 if( test_bit(MGA_BUF_NEEDS_OVERFLOW, &tmp_buf->buffer_status)) { \
217 mga_advance_primary(dev); \
218 mga_dma_schedule(dev, 1); \
219 tmp_buf = dev_priv->prim_bufs[dev_priv->current_prim_idx]; \
220 } else if( tmp_buf->max_dwords - tmp_buf->num_dwords < length || \
221 tmp_buf->sec_used > MGA_DMA_BUF_NR/2) { \
222 set_bit(MGA_BUF_FORCE_FIRE, &tmp_buf->buffer_status); \
223 mga_advance_primary(dev); \
224 mga_dma_schedule(dev, 1); \
225 tmp_buf = dev_priv->prim_bufs[dev_priv->current_prim_idx]; \
226 } \
227 if(MGA_VERBOSE) \
228 DRM_DEBUG("PRIMGETPTR in %s\n", __FUNCTION__); \
229 dma_ptr = tmp_buf->current_dma_ptr; \
230 num_dwords = tmp_buf->num_dwords; \
231 phys_head = tmp_buf->phys_head; \
232 outcount = 0; \
233 } while(0)
234
235 #define PRIMGETPTR(dev_priv) do { \
236 drm_mga_prim_buf_t *tmp_buf = \
237 dev_priv->prim_bufs[dev_priv->current_prim_idx]; \
238 if(MGA_VERBOSE) \
239 DRM_DEBUG("PRIMGETPTR in %s\n", __FUNCTION__); \
240 dma_ptr = tmp_buf->current_dma_ptr; \
241 num_dwords = tmp_buf->num_dwords; \
242 phys_head = tmp_buf->phys_head; \
243 outcount = 0; \
244 } while(0)
245
246 #define PRIMPTR(prim_buf) do { \
247 if(MGA_VERBOSE) \
248 DRM_DEBUG("PRIMPTR in %s\n", __FUNCTION__); \
249 dma_ptr = prim_buf->current_dma_ptr; \
250 num_dwords = prim_buf->num_dwords; \
251 phys_head = prim_buf->phys_head; \
252 outcount = 0; \
253 } while(0)
254
255 #define PRIMFINISH(prim_buf) do { \
256 if (MGA_VERBOSE) { \
257 DRM_DEBUG( "PRIMFINISH in %s\n", __FUNCTION__); \
258 if (outcount & 3) \
259 DRM_DEBUG(" --- truncation\n"); \
260 } \
261 prim_buf->num_dwords = num_dwords; \
262 prim_buf->current_dma_ptr = dma_ptr; \
263 } while(0)
264
265 #define PRIMADVANCE(dev_priv) do { \
266 drm_mga_prim_buf_t *tmp_buf = \
267 dev_priv->prim_bufs[dev_priv->current_prim_idx]; \
268 if (MGA_VERBOSE) { \
269 DRM_DEBUG("PRIMADVANCE in %s\n", __FUNCTION__); \
270 if (outcount & 3) \
271 DRM_DEBUG(" --- truncation\n"); \
272 } \
273 tmp_buf->num_dwords = num_dwords; \
274 tmp_buf->current_dma_ptr = dma_ptr; \
275 } while (0)
276
277 #define PRIMUPDATE(dev_priv) do { \
278 drm_mga_prim_buf_t *tmp_buf = \
279 dev_priv->prim_bufs[dev_priv->current_prim_idx]; \
280 tmp_buf->sec_used++; \
281 } while (0)
282
283 #define AGEBUF(dev_priv, buf_priv) do { \
284 drm_mga_prim_buf_t *tmp_buf = \
285 dev_priv->prim_bufs[dev_priv->current_prim_idx]; \
286 buf_priv->my_freelist->age = tmp_buf->prim_age; \
287 } while (0)
288
289
290 #define PRIMOUTREG(reg, val) do { \
291 tempIndex[outcount]=ADRINDEX(reg); \
292 dma_ptr[1+outcount] = val; \
293 if (MGA_VERBOSE) \
294 DRM_DEBUG(" PRIMOUT %d: 0x%x -- 0x%x\n", \
295 num_dwords + 1 + outcount, ADRINDEX(reg), val); \
296 if( ++outcount == 4) { \
297 outcount = 0; \
298 dma_ptr[0] = *(unsigned long *)tempIndex; \
299 dma_ptr+=5; \
300 num_dwords += 5; \
301 } \
302 }while (0)
303
304 /* A reduced set of the mga registers.
305 */
306
307 #define MGAREG_MGA_EXEC 0x0100
308 #define MGAREG_ALPHACTRL 0x2c7c
309 #define MGAREG_AR0 0x1c60
310 #define MGAREG_AR1 0x1c64
311 #define MGAREG_AR2 0x1c68
312 #define MGAREG_AR3 0x1c6c
313 #define MGAREG_AR4 0x1c70
314 #define MGAREG_AR5 0x1c74
315 #define MGAREG_AR6 0x1c78
316 #define MGAREG_CXBNDRY 0x1c80
317 #define MGAREG_CXLEFT 0x1ca0
318 #define MGAREG_CXRIGHT 0x1ca4
319 #define MGAREG_DMAPAD 0x1c54
320 #define MGAREG_DSTORG 0x2cb8
321 #define MGAREG_DWGCTL 0x1c00
322 #define MGAREG_DWGSYNC 0x2c4c
323 #define MGAREG_FCOL 0x1c24
324 #define MGAREG_FIFOSTATUS 0x1e10
325 #define MGAREG_FOGCOL 0x1cf4
326 #define MGAREG_FXBNDRY 0x1c84
327 #define MGAREG_FXLEFT 0x1ca8
328 #define MGAREG_FXRIGHT 0x1cac
329 #define MGAREG_ICLEAR 0x1e18
330 #define MGAREG_IEN 0x1e1c
331 #define MGAREG_LEN 0x1c5c
332 #define MGAREG_MACCESS 0x1c04
333 #define MGAREG_PITCH 0x1c8c
334 #define MGAREG_PLNWT 0x1c1c
335 #define MGAREG_PRIMADDRESS 0x1e58
336 #define MGAREG_PRIMEND 0x1e5c
337 #define MGAREG_PRIMPTR 0x1e50
338 #define MGAREG_SECADDRESS 0x2c40
339 #define MGAREG_SECEND 0x2c44
340 #define MGAREG_SETUPADDRESS 0x2cd0
341 #define MGAREG_SETUPEND 0x2cd4
342 #define MGAREG_SOFTRAP 0x2c48
343 #define MGAREG_SRCORG 0x2cb4
344 #define MGAREG_STATUS 0x1e14
345 #define MGAREG_STENCIL 0x2cc8
346 #define MGAREG_STENCILCTL 0x2ccc
347 #define MGAREG_TDUALSTAGE0 0x2cf8
348 #define MGAREG_TDUALSTAGE1 0x2cfc
349 #define MGAREG_TEXBORDERCOL 0x2c5c
350 #define MGAREG_TEXCTL 0x2c30
351 #define MGAREG_TEXCTL2 0x2c3c
352 #define MGAREG_TEXFILTER 0x2c58
353 #define MGAREG_TEXHEIGHT 0x2c2c
354 #define MGAREG_TEXORG 0x2c24
355 #define MGAREG_TEXORG1 0x2ca4
356 #define MGAREG_TEXORG2 0x2ca8
357 #define MGAREG_TEXORG3 0x2cac
358 #define MGAREG_TEXORG4 0x2cb0
359 #define MGAREG_TEXTRANS 0x2c34
360 #define MGAREG_TEXTRANSHIGH 0x2c38
361 #define MGAREG_TEXWIDTH 0x2c28
362 #define MGAREG_WACCEPTSEQ 0x1dd4
363 #define MGAREG_WCODEADDR 0x1e6c
364 #define MGAREG_WFLAG 0x1dc4
365 #define MGAREG_WFLAG1 0x1de0
366 #define MGAREG_WFLAGNB 0x1e64
367 #define MGAREG_WFLAGNB1 0x1e08
368 #define MGAREG_WGETMSB 0x1dc8
369 #define MGAREG_WIADDR 0x1dc0
370 #define MGAREG_WIADDR2 0x1dd8
371 #define MGAREG_WMISC 0x1e70
372 #define MGAREG_WVRTXSZ 0x1dcc
373 #define MGAREG_YBOT 0x1c9c
374 #define MGAREG_YDST 0x1c90
375 #define MGAREG_YDSTLEN 0x1c88
376 #define MGAREG_YDSTORG 0x1c94
377 #define MGAREG_YTOP 0x1c98
378 #define MGAREG_ZORG 0x1c0c
379
380 /* Warp registers */
381 #define MGAREG_WR0 0x2d00
382 #define MGAREG_WR1 0x2d04
383 #define MGAREG_WR2 0x2d08
384 #define MGAREG_WR3 0x2d0c
385 #define MGAREG_WR4 0x2d10
386 #define MGAREG_WR5 0x2d14
387 #define MGAREG_WR6 0x2d18
388 #define MGAREG_WR7 0x2d1c
389 #define MGAREG_WR8 0x2d20
390 #define MGAREG_WR9 0x2d24
391 #define MGAREG_WR10 0x2d28
392 #define MGAREG_WR11 0x2d2c
393 #define MGAREG_WR12 0x2d30
394 #define MGAREG_WR13 0x2d34
395 #define MGAREG_WR14 0x2d38
396 #define MGAREG_WR15 0x2d3c
397 #define MGAREG_WR16 0x2d40
398 #define MGAREG_WR17 0x2d44
399 #define MGAREG_WR18 0x2d48
400 #define MGAREG_WR19 0x2d4c
401 #define MGAREG_WR20 0x2d50
402 #define MGAREG_WR21 0x2d54
403 #define MGAREG_WR22 0x2d58
404 #define MGAREG_WR23 0x2d5c
405 #define MGAREG_WR24 0x2d60
406 #define MGAREG_WR25 0x2d64
407 #define MGAREG_WR26 0x2d68
408 #define MGAREG_WR27 0x2d6c
409 #define MGAREG_WR28 0x2d70
410 #define MGAREG_WR29 0x2d74
411 #define MGAREG_WR30 0x2d78
412 #define MGAREG_WR31 0x2d7c
413 #define MGAREG_WR32 0x2d80
414 #define MGAREG_WR33 0x2d84
415 #define MGAREG_WR34 0x2d88
416 #define MGAREG_WR35 0x2d8c
417 #define MGAREG_WR36 0x2d90
418 #define MGAREG_WR37 0x2d94
419 #define MGAREG_WR38 0x2d98
420 #define MGAREG_WR39 0x2d9c
421 #define MGAREG_WR40 0x2da0
422 #define MGAREG_WR41 0x2da4
423 #define MGAREG_WR42 0x2da8
424 #define MGAREG_WR43 0x2dac
425 #define MGAREG_WR44 0x2db0
426 #define MGAREG_WR45 0x2db4
427 #define MGAREG_WR46 0x2db8
428 #define MGAREG_WR47 0x2dbc
429 #define MGAREG_WR48 0x2dc0
430 #define MGAREG_WR49 0x2dc4
431 #define MGAREG_WR50 0x2dc8
432 #define MGAREG_WR51 0x2dcc
433 #define MGAREG_WR52 0x2dd0
434 #define MGAREG_WR53 0x2dd4
435 #define MGAREG_WR54 0x2dd8
436 #define MGAREG_WR55 0x2ddc
437 #define MGAREG_WR56 0x2de0
438 #define MGAREG_WR57 0x2de4
439 #define MGAREG_WR58 0x2de8
440 #define MGAREG_WR59 0x2dec
441 #define MGAREG_WR60 0x2df0
442 #define MGAREG_WR61 0x2df4
443 #define MGAREG_WR62 0x2df8
444 #define MGAREG_WR63 0x2dfc
445
446 #define PDEA_pagpxfer_enable 0x2
447
448 #define WIA_wmode_suspend 0x0
449 #define WIA_wmode_start 0x3
450 #define WIA_wagp_agp 0x4
451
452 #define DC_opcod_line_open 0x0
453 #define DC_opcod_autoline_open 0x1
454 #define DC_opcod_line_close 0x2
455 #define DC_opcod_autoline_close 0x3
456 #define DC_opcod_trap 0x4
457 #define DC_opcod_texture_trap 0x6
458 #define DC_opcod_bitblt 0x8
459 #define DC_opcod_iload 0x9
460 #define DC_atype_rpl 0x0
461 #define DC_atype_rstr 0x10
462 #define DC_atype_zi 0x30
463 #define DC_atype_blk 0x40
464 #define DC_atype_i 0x70
465 #define DC_linear_xy 0x0
466 #define DC_linear_linear 0x80
467 #define DC_zmode_nozcmp 0x0
468 #define DC_zmode_ze 0x200
469 #define DC_zmode_zne 0x300
470 #define DC_zmode_zlt 0x400
471 #define DC_zmode_zlte 0x500
472 #define DC_zmode_zgt 0x600
473 #define DC_zmode_zgte 0x700
474 #define DC_solid_disable 0x0
475 #define DC_solid_enable 0x800
476 #define DC_arzero_disable 0x0
477 #define DC_arzero_enable 0x1000
478 #define DC_sgnzero_disable 0x0
479 #define DC_sgnzero_enable 0x2000
480 #define DC_shftzero_disable 0x0
481 #define DC_shftzero_enable 0x4000
482 #define DC_bop_SHIFT 16
483 #define DC_trans_SHIFT 20
484 #define DC_bltmod_bmonolef 0x0
485 #define DC_bltmod_bmonowf 0x8000000
486 #define DC_bltmod_bplan 0x2000000
487 #define DC_bltmod_bfcol 0x4000000
488 #define DC_bltmod_bu32bgr 0x6000000
489 #define DC_bltmod_bu32rgb 0xe000000
490 #define DC_bltmod_bu24bgr 0x16000000
491 #define DC_bltmod_bu24rgb 0x1e000000
492 #define DC_pattern_disable 0x0
493 #define DC_pattern_enable 0x20000000
494 #define DC_transc_disable 0x0
495 #define DC_transc_enable 0x40000000
496 #define DC_clipdis_disable 0x0
497 #define DC_clipdis_enable 0x80000000
498
499
500 #define SETADD_mode_vertlist 0x0
501
502
503 #define MGA_CLEAR_CMD (DC_opcod_trap | DC_arzero_enable | \
504 DC_sgnzero_enable | DC_shftzero_enable | \
505 (0xC << DC_bop_SHIFT) | DC_clipdis_enable | \
506 DC_solid_enable | DC_transc_enable)
507
508
509 #define MGA_COPY_CMD (DC_opcod_bitblt | DC_atype_rpl | DC_linear_xy | \
510 DC_solid_disable | DC_arzero_disable | \
511 DC_sgnzero_enable | DC_shftzero_enable | \
512 (0xC << DC_bop_SHIFT) | DC_bltmod_bfcol | \
513 DC_pattern_disable | DC_transc_disable | \
514 DC_clipdis_enable) \
515
516 #define MGA_FLUSH_CMD (DC_opcod_texture_trap | (0xF << DC_trans_SHIFT) |\
517 DC_arzero_enable | DC_sgnzero_enable | \
518 DC_atype_i)
519
520 #endif
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