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Import 2.3.15pre2
[davej-history.git] / drivers / video / imsttfb.c
blob398e8e500a92c64728272429102104159901c763
1 /*
2 * drivers/video/imsttfb.c -- frame buffer device for IMS TwinTurbo
3 *
4 * This file is derived from the powermac console "imstt" driver:
5 * Copyright (C) 1997 Sigurdur Asgeirsson
6 * With additional hacking by Jeffrey Kuskin (jsk@mojave.stanford.edu)
7 * Modified by Danilo Beuche 1998
8 * Some register values added by Damien Doligez, INRIA Rocquencourt
9 *
10 * This file was written by Ryan Nielsen (ran@krazynet.com)
11 * Most of the frame buffer device stuff was copied from atyfb.c
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file COPYING in the main directory of this archive for
15 * more details.
16 */
17
18 #include <linux/config.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/string.h>
23 #include <linux/mm.h>
24 #include <linux/tty.h>
25 #include <linux/malloc.h>
26 #include <linux/vmalloc.h>
27 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/fb.h>
30 #include <linux/console.h>
31 #include <linux/selection.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <asm/io.h>
35 #include <asm/uaccess.h>
36
37 #if defined(CONFIG_PPC)
38 #include <linux/nvram.h>
39 #include <asm/prom.h>
40 #include <asm/pci-bridge.h>
41 #include <video/macmodes.h>
42 #endif
43
44 #include <video/fbcon.h>
45 #include <video/fbcon-cfb8.h>
46 #include <video/fbcon-cfb16.h>
47 #include <video/fbcon-cfb24.h>
48 #include <video/fbcon-cfb32.h>
49
50 #ifndef __powerpc__
51 #define eieio() /* Enforce In-order Execution of I/O */
52 #endif
53
54 /* TwinTurbo (Cosmo) registers */
55 enum {
56 S1SA = 0, /* 0x00 */
57 S2SA = 1, /* 0x04 */
58 SP = 2, /* 0x08 */
59 DSA = 3, /* 0x0C */
60 CNT = 4, /* 0x10 */
61 DP_OCTL = 5, /* 0x14 */
62 CLR = 6, /* 0x18 */
63 BI = 8, /* 0x20 */
64 MBC = 9, /* 0x24 */
65 BLTCTL = 10, /* 0x28 */
66
67 /* Scan Timing Generator Registers */
68 HES = 12, /* 0x30 */
69 HEB = 13, /* 0x34 */
70 HSB = 14, /* 0x38 */
71 HT = 15, /* 0x3C */
72 VES = 16, /* 0x40 */
73 VEB = 17, /* 0x44 */
74 VSB = 18, /* 0x48 */
75 VT = 19, /* 0x4C */
76 HCIV = 20, /* 0x50 */
77 VCIV = 21, /* 0x54 */
78 TCDR = 22, /* 0x58 */
79 VIL = 23, /* 0x5C */
80 STGCTL = 24, /* 0x60 */
81
82 /* Screen Refresh Generator Registers */
83 SSR = 25, /* 0x64 */
84 HRIR = 26, /* 0x68 */
85 SPR = 27, /* 0x6C */
86 CMR = 28, /* 0x70 */
87 SRGCTL = 29, /* 0x74 */
88
89 /* RAM Refresh Generator Registers */
90 RRCIV = 30, /* 0x78 */
91 RRSC = 31, /* 0x7C */
92 RRCR = 34, /* 0x88 */
93
94 /* System Registers */
95 GIOE = 32, /* 0x80 */
96 GIO = 33, /* 0x84 */
97 SCR = 35, /* 0x8C */
98 SSTATUS = 36, /* 0x90 */
99 PRC = 37, /* 0x94 */
100
101 #if 0
102 /* PCI Registers */
103 DVID = 0x00000000L,
104 SC = 0x00000004L,
105 CCR = 0x00000008L,
106 OG = 0x0000000CL,
107 BARM = 0x00000010L,
108 BARER = 0x00000030L,
109 #endif
110 };
111
112 /* IBM 624 RAMDAC Direct Registers */
113 enum {
114 PADDRW = 0x00,
115 PDATA = 0x04,
116 PPMASK = 0x08,
117 PADDRR = 0x0c,
118 PIDXLO = 0x10,
119 PIDXHI = 0x14,
120 PIDXDATA= 0x18,
121 PIDXCTL = 0x1c
122 };
123
124 /* IBM 624 RAMDAC Indirect Registers */
125 enum {
126 CLKCTL = 0x02, /* (0x01) Miscellaneous Clock Control */
127 SYNCCTL = 0x03, /* (0x00) Sync Control */
128 HSYNCPOS = 0x04, /* (0x00) Horizontal Sync Position */
129 PWRMNGMT = 0x05, /* (0x00) Power Management */
130 DACOP = 0x06, /* (0x02) DAC Operation */
131 PALETCTL = 0x07, /* (0x00) Palette Control */
132 SYSCLKCTL = 0x08, /* (0x01) System Clock Control */
133 PIXFMT = 0x0a, /* () Pixel Format [bpp >> 3 + 2] */
134 BPP8 = 0x0b, /* () 8 Bits/Pixel Control */
135 BPP16 = 0x0c, /* () 16 Bits/Pixel Control [bit 1=1 for 565] */
136 BPP24 = 0x0d, /* () 24 Bits/Pixel Control */
137 BPP32 = 0x0e, /* () 32 Bits/Pixel Control */
138 PIXCTL1 = 0x10, /* (0x05) Pixel PLL Control 1 */
139 PIXCTL2 = 0x11, /* (0x00) Pixel PLL Control 2 */
140 SYSCLKN = 0x15, /* () System Clock N (System PLL Reference Divider) */
141 SYSCLKM = 0x16, /* () System Clock M (System PLL VCO Divider) */
142 SYSCLKP = 0x17, /* () System Clock P */
143 SYSCLKC = 0x18, /* () System Clock C */
144 /*
145 * Dot clock rate is 20MHz * (m + 1) / ((n + 1) * (p ? 2 * p : 1)
146 * c is charge pump bias which depends on the VCO frequency
147 */
148 PIXM0 = 0x20, /* () Pixel M 0 */
149 PIXN0 = 0x21, /* () Pixel N 0 */
150 PIXP0 = 0x22, /* () Pixel P 0 */
151 PIXC0 = 0x23, /* () Pixel C 0 */
152 CURSCTL = 0x30, /* (0x00) Cursor Control */
153 CURSXLO = 0x31, /* () Cursor X position, low 8 bits */
154 CURSXHI = 0x32, /* () Cursor X position, high 8 bits */
155 CURSYLO = 0x33, /* () Cursor Y position, low 8 bits */
156 CURSYHI = 0x34, /* () Cursor Y position, high 8 bits */
157 CURSHOTX = 0x35, /* () Cursor Hot Spot X */
158 CURSHOTY = 0x36, /* () Cursor Hot Spot Y */
159 CURSACCTL = 0x37, /* () Advanced Cursor Control Enable */
160 CURSACATTR = 0x38, /* () Advanced Cursor Attribute */
161 CURS1R = 0x40, /* () Cursor 1 Red */
162 CURS1G = 0x41, /* () Cursor 1 Green */
163 CURS1B = 0x42, /* () Cursor 1 Blue */
164 CURS2R = 0x43, /* () Cursor 2 Red */
165 CURS2G = 0x44, /* () Cursor 2 Green */
166 CURS2B = 0x45, /* () Cursor 2 Blue */
167 CURS3R = 0x46, /* () Cursor 3 Red */
168 CURS3G = 0x47, /* () Cursor 3 Green */
169 CURS3B = 0x48, /* () Cursor 3 Blue */
170 BORDR = 0x60, /* () Border Color Red */
171 BORDG = 0x61, /* () Border Color Green */
172 BORDB = 0x62, /* () Border Color Blue */
173 MISCTL1 = 0x70, /* (0x00) Miscellaneous Control 1 */
174 MISCTL2 = 0x71, /* (0x00) Miscellaneous Control 2 */
175 MISCTL3 = 0x72, /* (0x00) Miscellaneous Control 3 */
176 KEYCTL = 0x78 /* (0x00) Key Control/DB Operation */
177 };
178
179 /* TI TVP 3030 RAMDAC Direct Registers */
180 enum {
181 TVPADDRW = 0x00, /* 0 Palette/Cursor RAM Write Adress/Index */
182 TVPPDATA = 0x04, /* 1 Palette Data RAM Data */
183 TVPPMASK = 0x08, /* 2 Pixel Read-Mask */
184 TVPPADRR = 0x0c, /* 3 Palette/Cursor RAM Read Adress */
185 TVPCADRW = 0x10, /* 4 Cursor/Overscan Color Write Address */
186 TVPCDATA = 0x14, /* 5 Cursor/Overscan Color Data */
187 /* 6 reserved */
188 TVPCADRR = 0x1c, /* 7 Cursor/Overscan Color Read Address */
189 /* 8 reserved */
190 TVPDCCTL = 0x24, /* 9 Direct Cursor Control */
191 TVPIDATA = 0x28, /* 10 Index Data */
192 TVPCRDAT = 0x2c, /* 11 Cursor RAM Data */
193 TVPCXPOL = 0x30, /* 12 Cursor-Position X LSB */
194 TVPCXPOH = 0x34, /* 13 Cursor-Position X MSB */
195 TVPCYPOL = 0x38, /* 14 Cursor-Position Y LSB */
196 TVPCYPOH = 0x3c, /* 15 Cursor-Position Y MSB */
197 };
198
199 /* TI TVP 3030 RAMDAC Indirect Registers */
200 enum {
201 TVPIRREV = 0x01, /* Silicon Revision [RO] */
202 TVPIRICC = 0x06, /* Indirect Cursor Control (0x00) */
203 TVPIRBRC = 0x07, /* Byte Router Control (0xe4) */
204 TVPIRLAC = 0x0f, /* Latch Control (0x06) */
205 TVPIRTCC = 0x18, /* True Color Control (0x80) */
206 TVPIRMXC = 0x19, /* Multiplex Control (0x98) */
207 TVPIRCLS = 0x1a, /* Clock Selection (0x07) */
208 TVPIRPPG = 0x1c, /* Palette Page (0x00) */
209 TVPIRGEC = 0x1d, /* General Control (0x00) */
210 TVPIRMIC = 0x1e, /* Miscellaneous Control (0x00) */
211 TVPIRPLA = 0x2c, /* PLL Address */
212 TVPIRPPD = 0x2d, /* Pixel Clock PLL Data */
213 TVPIRMPD = 0x2e, /* Memory Clock PLL Data */
214 TVPIRLPD = 0x2f, /* Loop Clock PLL Data */
215 TVPIRCKL = 0x30, /* Color-Key Overlay Low */
216 TVPIRCKH = 0x31, /* Color-Key Overlay High */
217 TVPIRCRL = 0x32, /* Color-Key Red Low */
218 TVPIRCRH = 0x33, /* Color-Key Red High */
219 TVPIRCGL = 0x34, /* Color-Key Green Low */
220 TVPIRCGH = 0x35, /* Color-Key Green High */
221 TVPIRCBL = 0x36, /* Color-Key Blue Low */
222 TVPIRCBH = 0x37, /* Color-Key Blue High */
223 TVPIRCKC = 0x38, /* Color-Key Control (0x00) */
224 TVPIRMLC = 0x39, /* MCLK/Loop Clock Control (0x18) */
225 TVPIRSEN = 0x3a, /* Sense Test (0x00) */
226 TVPIRTMD = 0x3b, /* Test Mode Data */
227 TVPIRRML = 0x3c, /* CRC Remainder LSB [RO] */
228 TVPIRRMM = 0x3d, /* CRC Remainder MSB [RO] */
229 TVPIRRMS = 0x3e, /* CRC Bit Select [WO] */
230 TVPIRDID = 0x3f, /* Device ID [RO] (0x30) */
231 TVPIRRES = 0xff /* Software Reset [WO] */
232 };
233
234 struct initvalues {
235 __u8 addr, value;
236 };
237
238 static struct initvalues ibm_initregs[] __initdata = {
239 { CLKCTL, 0x21 },
240 { SYNCCTL, 0x00 },
241 { HSYNCPOS, 0x00 },
242 { PWRMNGMT, 0x00 },
243 { DACOP, 0x02 },
244 { PALETCTL, 0x00 },
245 { SYSCLKCTL, 0x01 },
246
247 /*
248 * Note that colors in X are correct only if all video data is
249 * passed through the palette in the DAC. That is, "indirect
250 * color" must be configured. This is the case for the IBM DAC
251 * used in the 2MB and 4MB cards, at least.
252 */
253 { BPP8, 0x00 },
254 { BPP16, 0x01 },
255 { BPP24, 0x00 },
256 { BPP32, 0x00 },
257
258 { PIXCTL1, 0x05 },
259 { PIXCTL2, 0x00 },
260 { SYSCLKN, 0x08 },
261 { SYSCLKM, 0x4f },
262 { SYSCLKP, 0x00 },
263 { SYSCLKC, 0x00 },
264 { CURSCTL, 0x00 },
265 { CURSACCTL, 0x01 },
266 { CURSACATTR, 0xa8 },
267 { CURS1R, 0xff },
268 { CURS1G, 0xff },
269 { CURS1B, 0xff },
270 { CURS2R, 0xff },
271 { CURS2G, 0xff },
272 { CURS2B, 0xff },
273 { CURS3R, 0xff },
274 { CURS3G, 0xff },
275 { CURS3B, 0xff },
276 { BORDR, 0xff },
277 { BORDG, 0xff },
278 { BORDB, 0xff },
279 { MISCTL1, 0x01 },
280 { MISCTL2, 0x45 },
281 { MISCTL3, 0x00 },
282 { KEYCTL, 0x00 }
283 };
284
285 static struct initvalues tvp_initregs[] __initdata = {
286 { TVPIRICC, 0x00 },
287 { TVPIRBRC, 0xe4 },
288 { TVPIRLAC, 0x06 },
289 { TVPIRTCC, 0x80 },
290 { TVPIRMXC, 0x4d },
291 { TVPIRCLS, 0x05 },
292 { TVPIRPPG, 0x00 },
293 { TVPIRGEC, 0x00 },
294 { TVPIRMIC, 0x08 },
295 { TVPIRCKL, 0xff },
296 { TVPIRCKH, 0xff },
297 { TVPIRCRL, 0xff },
298 { TVPIRCRH, 0xff },
299 { TVPIRCGL, 0xff },
300 { TVPIRCGH, 0xff },
301 { TVPIRCBL, 0xff },
302 { TVPIRCBH, 0xff },
303 { TVPIRCKC, 0x00 },
304 { TVPIRPLA, 0x00 },
305 { TVPIRPPD, 0xc0 },
306 { TVPIRPPD, 0xd5 },
307 { TVPIRPPD, 0xea },
308 { TVPIRPLA, 0x00 },
309 { TVPIRMPD, 0xb9 },
310 { TVPIRMPD, 0x3a },
311 { TVPIRMPD, 0xb1 },
312 { TVPIRPLA, 0x00 },
313 { TVPIRLPD, 0xc1 },
314 { TVPIRLPD, 0x3d },
315 { TVPIRLPD, 0xf3 },
316 };
317
318 struct imstt_regvals {
319 __u32 pitch;
320 __u16 hes, heb, hsb, ht, ves, veb, vsb, vt, vil;
321 __u8 pclk_m, pclk_n, pclk_p;
322 /* Values of the tvp which change depending on colormode x resolution */
323 __u8 mlc[3]; /* Memory Loop Config 0x39 */
324 __u8 lckl_p[3]; /* P value of LCKL PLL */
325 };
326
327 struct imstt_cursor {
328 struct timer_list timer;
329 int enable;
330 int on;
331 int vbl_cnt;
332 int blink_rate;
333 __u16 x, y, width, height;
334 };
335
336 struct fb_info_imstt {
337 struct fb_info info;
338 struct fb_fix_screeninfo fix;
339 struct display disp;
340 struct display_switch dispsw;
341 union {
342 #ifdef FBCON_HAS_CFB16
343 __u16 cfb16[16];
344 #endif
345 #ifdef FBCON_HAS_CFB24
346 __u32 cfb24[16];
347 #endif
348 #ifdef FBCON_HAS_CFB32
349 __u32 cfb32[16];
350 #endif
351 } fbcon_cmap;
352 struct {
353 __u8 red, green, blue;
354 } palette[256];
355 struct imstt_regvals init;
356 struct imstt_cursor cursor;
357 __u8 *frame_buffer_phys, *frame_buffer;
358 __u32 *dc_regs_phys, *dc_regs;
359 __u8 *cmap_regs_phys, *cmap_regs;
360 __u32 total_vram;
361 __u32 ramdac;
362 };
363
364 enum {
365 IBM = 0,
366 TVP = 1
367 };
368
369 #define USE_NV_MODES 1
370 #define INIT_BPP 8
371 #define INIT_XRES 640
372 #define INIT_YRES 480
373 #define CURSOR_BLINK_RATE 20
374 #define CURSOR_DRAW_DELAY 2
375
376 static int currcon = 0;
377 static char fontname[40] __initdata = { 0 };
378 static char curblink __initdata = 1;
379 static char noaccel __initdata = 0;
380 #if defined(CONFIG_PPC)
381 static signed char init_vmode __initdata = -1, init_cmode __initdata = -1;
382 #endif
383 static struct fb_info_imstt *fb_info_imstt_p[FB_MAX] = { 0, 0, 0, 0, 0, 0, 0, 0 };
384
385 static struct imstt_regvals tvp_reg_init_2 = {
386 512,
387 0x0002, 0x0006, 0x0026, 0x0028, 0x0003, 0x0016, 0x0196, 0x0197, 0x0196,
388 0xec, 0x2a, 0xf3,
389 { 0x3c, 0x3b, 0x39 }, { 0xf3, 0xf3, 0xf3 }
390 };
391
392 static struct imstt_regvals tvp_reg_init_6 = {
393 640,
394 0x0004, 0x0009, 0x0031, 0x0036, 0x0003, 0x002a, 0x020a, 0x020d, 0x020a,
395 0xef, 0x2e, 0xb2,
396 { 0x39, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
397 };
398
399 static struct imstt_regvals tvp_reg_init_12 = {
400 800,
401 0x0005, 0x000e, 0x0040, 0x0042, 0x0003, 0x018, 0x270, 0x271, 0x270,
402 0xf6, 0x2e, 0xf2,
403 { 0x3a, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
404 };
405
406 static struct imstt_regvals tvp_reg_init_13 = {
407 832,
408 0x0004, 0x0011, 0x0045, 0x0048, 0x0003, 0x002a, 0x029a, 0x029b, 0x0000,
409 0xfe, 0x3e, 0xf1,
410 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
411 };
412
413 static struct imstt_regvals tvp_reg_init_17 = {
414 1024,
415 0x0006, 0x0210, 0x0250, 0x0053, 0x1003, 0x0021, 0x0321, 0x0324, 0x0000,
416 0xfc, 0x3a, 0xf1,
417 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
418 };
419
420 static struct imstt_regvals tvp_reg_init_18 = {
421 1152,
422 0x0009, 0x0011, 0x059, 0x5b, 0x0003, 0x0031, 0x0397, 0x039a, 0x0000,
423 0xfd, 0x3a, 0xf1,
424 { 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
425 };
426
427 static struct imstt_regvals tvp_reg_init_19 = {
428 1280,
429 0x0009, 0x0016, 0x0066, 0x0069, 0x0003, 0x0027, 0x03e7, 0x03e8, 0x03e7,
430 0xf7, 0x36, 0xf0,
431 { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
432 };
433
434 static struct imstt_regvals tvp_reg_init_20 = {
435 1280,
436 0x0009, 0x0018, 0x0068, 0x006a, 0x0003, 0x0029, 0x0429, 0x042a, 0x0000,
437 0xf0, 0x2d, 0xf0,
438 { 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
439 };
440
441 static __u32
442 getclkMHz (struct fb_info_imstt *p)
443 {
444 __u32 clk_m, clk_n, clk_p;
445
446 clk_m = p->init.pclk_m;
447 clk_n = p->init.pclk_n;
448 clk_p = p->init.pclk_p;
449
450 return 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1));
451 }
452
453 static void
454 setclkMHz (struct fb_info_imstt *p, __u32 MHz)
455 {
456 __u32 clk_m, clk_n, clk_p, x, stage, spilled;
457
458 clk_m = clk_n = clk_p = 0;
459 stage = spilled = 0;
460 for (;;) {
461 switch (stage) {
462 case 0:
463 clk_m++;
464 break;
465 case 1:
466 clk_n++;
467 break;
468 }
469 x = 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1));
470 if (x == MHz)
471 break;
472 if (x > MHz) {
473 spilled = 1;
474 stage = 1;
475 } else if (spilled && x < MHz) {
476 stage = 0;
477 }
478 }
479
480 p->init.pclk_m = clk_m;
481 p->init.pclk_n = clk_n;
482 p->init.pclk_p = clk_p;
483 }
484
485 static struct imstt_regvals *
486 compute_imstt_regvals_ibm (struct fb_info_imstt *p, int xres, int yres)
487 {
488 struct imstt_regvals *init = &p->init;
489 __u32 MHz, hes, heb, veb, htp, vtp;
490
491 switch (xres) {
492 case 640:
493 hes = 0x0008; heb = 0x0012; veb = 0x002a; htp = 10; vtp = 2;
494 MHz = 30 /* .25 */ ;
495 break;
496 case 832:
497 hes = 0x0005; heb = 0x0020; veb = 0x0028; htp = 8; vtp = 3;
498 MHz = 57 /* .27_ */ ;
499 break;
500 case 1024:
501 hes = 0x000a; heb = 0x001c; veb = 0x0020; htp = 8; vtp = 3;
502 MHz = 80;
503 break;
504 case 1152:
505 hes = 0x0012; heb = 0x0022; veb = 0x0031; htp = 4; vtp = 3;
506 MHz = 101 /* .6_ */ ;
507 break;
508 case 1280:
509 hes = 0x0012; heb = 0x002f; veb = 0x0029; htp = 4; vtp = 1;
510 MHz = yres == 960 ? 126 : 135;
511 break;
512 case 1600:
513 hes = 0x0018; heb = 0x0040; veb = 0x002a; htp = 4; vtp = 3;
514 MHz = 200;
515 break;
516 default:
517 return 0;
518 }
519
520 setclkMHz(p, MHz);
521
522 init->hes = hes;
523 init->heb = heb;
524 init->hsb = init->heb + (xres >> 3);
525 init->ht = init->hsb + htp;
526 init->ves = 0x0003;
527 init->veb = veb;
528 init->vsb = init->veb + yres;
529 init->vt = init->vsb + vtp;
530 init->vil = init->vsb;
531
532 init->pitch = xres;
533
534 return init;
535 }
536
537 static struct imstt_regvals *
538 compute_imstt_regvals_tvp (struct fb_info_imstt *p, int xres, int yres)
539 {
540 struct imstt_regvals *init;
541
542 switch (xres) {
543 case 512:
544 init = &tvp_reg_init_2;
545 break;
546 case 640:
547 init = &tvp_reg_init_6;
548 break;
549 case 800:
550 init = &tvp_reg_init_12;
551 break;
552 case 832:
553 init = &tvp_reg_init_13;
554 break;
555 case 1024:
556 init = &tvp_reg_init_17;
557 break;
558 case 1152:
559 init = &tvp_reg_init_18;
560 break;
561 case 1280:
562 init = yres == 960 ? &tvp_reg_init_19 : &tvp_reg_init_20;
563 break;
564 default:
565 return 0;
566 }
567 p->init = *init;
568
569 return init;
570 }
571
572 static struct imstt_regvals *
573 compute_imstt_regvals (struct fb_info_imstt *p, u_int xres, u_int yres)
574 {
575 if (p->ramdac == IBM)
576 return compute_imstt_regvals_ibm(p, xres, yres);
577 else
578 return compute_imstt_regvals_tvp(p, xres, yres);
579 }
580
581 static void
582 set_imstt_regvals_ibm (struct fb_info_imstt *p, u_int bpp)
583 {
584 struct imstt_regvals *init = &p->init;
585 __u8 pformat = (bpp >> 3) + 2;
586
587 p->cmap_regs[PIDXHI] = 0; eieio();
588 p->cmap_regs[PIDXLO] = PIXM0; eieio();
589 p->cmap_regs[PIDXDATA] = init->pclk_m; eieio();
590 p->cmap_regs[PIDXLO] = PIXN0; eieio();
591 p->cmap_regs[PIDXDATA] = init->pclk_n; eieio();
592 p->cmap_regs[PIDXLO] = PIXP0; eieio();
593 p->cmap_regs[PIDXDATA] = init->pclk_p; eieio();
594 p->cmap_regs[PIDXLO] = PIXC0; eieio();
595 p->cmap_regs[PIDXDATA] = 0x02; eieio();
596
597 p->cmap_regs[PIDXLO] = PIXFMT; eieio();
598 p->cmap_regs[PIDXDATA] = pformat; eieio();
599 }
600
601 static void
602 set_imstt_regvals_tvp (struct fb_info_imstt *p, u_int bpp)
603 {
604 struct imstt_regvals *init = &p->init;
605 __u8 tcc, mxc, lckl_n, mic;
606 __u8 mlc, lckl_p;
607
608 switch (bpp) {
609 case 8:
610 tcc = 0x80;
611 mxc = 0x4d;
612 lckl_n = 0xc1;
613 mlc = init->mlc[0];
614 lckl_p = init->lckl_p[0];
615 break;
616 case 16:
617 tcc = 0x44;
618 mxc = 0x55;
619 lckl_n = 0xe1;
620 mlc = init->mlc[1];
621 lckl_p = init->lckl_p[1];
622 break;
623 case 24:
624 tcc = 0x5e;
625 mxc = 0x5d;
626 lckl_n = 0xf1;
627 mlc = init->mlc[2];
628 lckl_p = init->lckl_p[2];
629 break;
630 case 32:
631 tcc = 0x46;
632 mxc = 0x5d;
633 lckl_n = 0xf1;
634 mlc = init->mlc[2];
635 lckl_p = init->lckl_p[2];
636 break;
637 }
638 mic = 0x08;
639
640 p->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
641 p->cmap_regs[TVPIDATA] = 0x00; eieio();
642 p->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
643 p->cmap_regs[TVPIDATA] = init->pclk_m; eieio();
644 p->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
645 p->cmap_regs[TVPIDATA] = init->pclk_n; eieio();
646 p->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
647 p->cmap_regs[TVPIDATA] = init->pclk_p; eieio();
648
649 p->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
650 p->cmap_regs[TVPIDATA] = tcc; eieio();
651 p->cmap_regs[TVPADDRW] = TVPIRMXC; eieio();
652 p->cmap_regs[TVPIDATA] = mxc; eieio();
653 p->cmap_regs[TVPADDRW] = TVPIRMIC; eieio();
654 p->cmap_regs[TVPIDATA] = mic; eieio();
655
656 p->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
657 p->cmap_regs[TVPIDATA] = 0x00; eieio();
658 p->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
659 p->cmap_regs[TVPIDATA] = lckl_n; eieio();
660
661 p->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
662 p->cmap_regs[TVPIDATA] = 0x15; eieio();
663 p->cmap_regs[TVPADDRW] = TVPIRMLC; eieio();
664 p->cmap_regs[TVPIDATA] = mlc; eieio();
665
666 p->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
667 p->cmap_regs[TVPIDATA] = 0x2a; eieio();
668 p->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
669 p->cmap_regs[TVPIDATA] = lckl_p; eieio();
670 }
671
672 static void
673 set_imstt_regvals (struct fb_info_imstt *p, u_int bpp)
674 {
675 struct imstt_regvals *init = &p->init;
676 __u32 ctl, pitch, byteswap, scr;
677
678 if (p->ramdac == IBM)
679 set_imstt_regvals_ibm(p, bpp);
680 else
681 set_imstt_regvals_tvp(p, bpp);
682
683 /*
684 * From what I (jsk) can gather poking around with MacsBug,
685 * bits 8 and 9 in the SCR register control endianness
686 * correction (byte swapping). These bits must be set according
687 * to the color depth as follows:
688 * Color depth Bit 9 Bit 8
689 * ========== ===== =====
690 * 8bpp 0 0
691 * 16bpp 0 1
692 * 32bpp 1 1
693 */
694 switch (bpp) {
695 case 8:
696 ctl = 0x17b1;
697 pitch = init->pitch >> 2;
698 byteswap = 0x000;
699 break;
700 case 16:
701 ctl = 0x17b3;
702 pitch = init->pitch >> 1;
703 byteswap = 0x100;
704 break;
705 case 24:
706 ctl = 0x17b9;
707 pitch = init->pitch - (p->init.pitch >> 2);
708 byteswap = 0x200;
709 break;
710 case 32:
711 ctl = 0x17b5;
712 pitch = init->pitch;
713 byteswap = 0x300;
714 break;
715 }
716 if (p->ramdac == TVP)
717 ctl -= 0x30;
718
719 out_le32(&p->dc_regs[HES], init->hes);
720 out_le32(&p->dc_regs[HEB], init->heb);
721 out_le32(&p->dc_regs[HSB], init->hsb);
722 out_le32(&p->dc_regs[HT], init->ht);
723 out_le32(&p->dc_regs[VES], init->ves);
724 out_le32(&p->dc_regs[VEB], init->veb);
725 out_le32(&p->dc_regs[VSB], init->vsb);
726 out_le32(&p->dc_regs[VT], init->vt);
727 out_le32(&p->dc_regs[VIL], init->vil);
728 out_le32(&p->dc_regs[HCIV], 1);
729 out_le32(&p->dc_regs[VCIV], 1);
730 out_le32(&p->dc_regs[TCDR], 4);
731 out_le32(&p->dc_regs[RRCIV], 1);
732 out_le32(&p->dc_regs[RRSC], 0x980);
733 out_le32(&p->dc_regs[RRCR], 0x11);
734
735 if (p->ramdac == IBM) {
736 out_le32(&p->dc_regs[HRIR], 0x0100);
737 out_le32(&p->dc_regs[CMR], 0x00ff);
738 out_le32(&p->dc_regs[SRGCTL], 0x0073);
739 } else {
740 out_le32(&p->dc_regs[HRIR], 0x0200);
741 out_le32(&p->dc_regs[CMR], 0x01ff);
742 out_le32(&p->dc_regs[SRGCTL], 0x0003);
743 }
744
745 switch (p->total_vram) {
746 case 0x200000:
747 scr = 0x059d | byteswap;
748 break;
749 /* case 0x400000:
750 case 0x800000: */
751 default:
752 pitch >>= 1;
753 scr = 0x150dd | byteswap;
754 break;
755 }
756
757 out_le32(&p->dc_regs[SCR], scr);
758 out_le32(&p->dc_regs[SPR], pitch);
759 out_le32(&p->dc_regs[STGCTL], ctl);
760 }
761
762 static inline void
763 set_offset (struct display *disp, struct fb_info_imstt *p)
764 {
765 __u32 off = disp->var.yoffset * (disp->line_length >> 3)
766 + ((disp->var.xoffset * (disp->var.bits_per_pixel >> 3)) >> 3);
767 out_le32(&p->dc_regs[SSR], off);
768 }
769
770 static inline void
771 set_555 (struct fb_info_imstt *p)
772 {
773 if (p->ramdac == IBM) {
774 p->cmap_regs[PIDXHI] = 0; eieio();
775 p->cmap_regs[PIDXLO] = BPP16; eieio();
776 p->cmap_regs[PIDXDATA] = 0x01; eieio();
777 } else {
778 p->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
779 p->cmap_regs[TVPIDATA] = 0x44; eieio();
780 }
781 }
782
783 static inline void
784 set_565 (struct fb_info_imstt *p)
785 {
786 if (p->ramdac == IBM) {
787 p->cmap_regs[PIDXHI] = 0; eieio();
788 p->cmap_regs[PIDXLO] = BPP16; eieio();
789 p->cmap_regs[PIDXDATA] = 0x03; eieio();
790 } else {
791 p->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
792 p->cmap_regs[TVPIDATA] = 0x45; eieio();
793 }
794 }
795
796 static void
797 imstt_set_cursor (struct fb_info_imstt *p, int on)
798 {
799 struct imstt_cursor *c = &p->cursor;
800
801 if (p->ramdac == IBM) {
802 p->cmap_regs[PIDXHI] = 0; eieio();
803 if (!on) {
804 p->cmap_regs[PIDXLO] = CURSCTL; eieio();
805 p->cmap_regs[PIDXDATA] = 0x00; eieio();
806 } else {
807 p->cmap_regs[PIDXLO] = CURSXHI; eieio();
808 p->cmap_regs[PIDXDATA] = c->x >> 8; eieio();
809 p->cmap_regs[PIDXLO] = CURSXLO; eieio();
810 p->cmap_regs[PIDXDATA] = c->x & 0xff; eieio();
811 p->cmap_regs[PIDXLO] = CURSYHI; eieio();
812 p->cmap_regs[PIDXDATA] = c->y >> 8; eieio();
813 p->cmap_regs[PIDXLO] = CURSYLO; eieio();
814 p->cmap_regs[PIDXDATA] = c->y & 0xff; eieio();
815 p->cmap_regs[PIDXLO] = CURSCTL; eieio();
816 p->cmap_regs[PIDXDATA] = 0x02; eieio();
817 }
818 } else {
819 if (!on) {
820 p->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
821 p->cmap_regs[TVPIDATA] = 0x00; eieio();
822 } else {
823 __u16 x = c->x + 0x40, y = c->y + 0x40;
824
825 p->cmap_regs[TVPCXPOH] = x >> 8; eieio();
826 p->cmap_regs[TVPCXPOL] = x & 0xff; eieio();
827 p->cmap_regs[TVPCYPOH] = y >> 8; eieio();
828 p->cmap_regs[TVPCYPOL] = y & 0xff; eieio();
829 p->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
830 p->cmap_regs[TVPIDATA] = 0x02; eieio();
831 }
832 }
833 }
834
835 static void
836 imsttfbcon_cursor (struct display *disp, int mode, int x, int y)
837 {
838 struct fb_info_imstt *p = (struct fb_info_imstt *)disp->fb_info;
839 struct imstt_cursor *c = &p->cursor;
840
841 x *= fontwidth(disp);
842 y *= fontheight(disp);
843
844 if (c->x == x && c->y == y && (mode == CM_ERASE) == !c->enable)
845 return;
846
847 c->enable = 0;
848 if (c->on)
849 imstt_set_cursor(p, 0);
850 c->x = x - disp->var.xoffset;
851 c->y = y - disp->var.yoffset;
852
853 switch (mode) {
854 case CM_ERASE:
855 c->on = 0;
856 break;
857 case CM_DRAW:
858 case CM_MOVE:
859 if (c->on)
860 imstt_set_cursor(p, c->on);
861 else
862 c->vbl_cnt = CURSOR_DRAW_DELAY;
863 c->enable = 1;
864 break;
865 }
866 }
867
868 static int
869 imsttfbcon_set_font (struct display *disp, int width, int height)
870 {
871 struct fb_info_imstt *p = (struct fb_info_imstt *)disp->fb_info;
872 struct imstt_cursor *c = &p->cursor;
873 u_int x, y;
874 __u8 fgc;
875
876 if (width > 32 || height > 32)
877 return -EINVAL;
878
879 c->height = height;
880 c->width = width;
881
882 fgc = ~attr_bgcol_ec(disp, disp->conp);
883
884 if (p->ramdac == IBM) {
885 p->cmap_regs[PIDXHI] = 1; eieio();
886 for (x = 0; x < 0x100; x++) {
887 p->cmap_regs[PIDXLO] = x; eieio();
888 p->cmap_regs[PIDXDATA] = 0x00; eieio();
889 }
890 p->cmap_regs[PIDXHI] = 1; eieio();
891 for (y = 0; y < height; y++)
892 for (x = 0; x < width >> 2; x++) {
893 p->cmap_regs[PIDXLO] = x + y * 8; eieio();
894 p->cmap_regs[PIDXDATA] = 0xff; eieio();
895 }
896 p->cmap_regs[PIDXHI] = 0; eieio();
897 p->cmap_regs[PIDXLO] = CURS1R; eieio();
898 p->cmap_regs[PIDXDATA] = fgc; eieio();
899 p->cmap_regs[PIDXLO] = CURS1G; eieio();
900 p->cmap_regs[PIDXDATA] = fgc; eieio();
901 p->cmap_regs[PIDXLO] = CURS1B; eieio();
902 p->cmap_regs[PIDXDATA] = fgc; eieio();
903 p->cmap_regs[PIDXLO] = CURS2R; eieio();
904 p->cmap_regs[PIDXDATA] = fgc; eieio();
905 p->cmap_regs[PIDXLO] = CURS2G; eieio();
906 p->cmap_regs[PIDXDATA] = fgc; eieio();
907 p->cmap_regs[PIDXLO] = CURS2B; eieio();
908 p->cmap_regs[PIDXDATA] = fgc; eieio();
909 p->cmap_regs[PIDXLO] = CURS3R; eieio();
910 p->cmap_regs[PIDXDATA] = fgc; eieio();
911 p->cmap_regs[PIDXLO] = CURS3G; eieio();
912 p->cmap_regs[PIDXDATA] = fgc; eieio();
913 p->cmap_regs[PIDXLO] = CURS3B; eieio();
914 p->cmap_regs[PIDXDATA] = fgc; eieio();
915 } else {
916 p->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
917 p->cmap_regs[TVPIDATA] &= 0x03; eieio();
918 p->cmap_regs[TVPADDRW] = 0; eieio();
919 for (x = 0; x < 0x200; x++) {
920 p->cmap_regs[TVPCRDAT] = 0x00; eieio();
921 }
922 for (x = 0; x < 0x200; x++) {
923 p->cmap_regs[TVPCRDAT] = 0xff; eieio();
924 }
925 p->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
926 p->cmap_regs[TVPIDATA] &= 0x03; eieio();
927 for (y = 0; y < height; y++)
928 for (x = 0; x < width >> 3; x++) {
929 p->cmap_regs[TVPADDRW] = x + y * 8; eieio();
930 p->cmap_regs[TVPCRDAT] = 0xff; eieio();
931 }
932 p->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
933 p->cmap_regs[TVPIDATA] |= 0x08; eieio();
934 for (y = 0; y < height; y++)
935 for (x = 0; x < width >> 3; x++) {
936 p->cmap_regs[TVPADDRW] = x + y * 8; eieio();
937 p->cmap_regs[TVPCRDAT] = 0xff; eieio();
938 }
939 p->cmap_regs[TVPCADRW] = 0x00; eieio();
940 for (x = 0; x < 12; x++) {
941 p->cmap_regs[TVPCDATA] = fgc; eieio();
942 }
943 }
944
945 return 1;
946 }
947
948 static void
949 imstt_cursor_timer_handler (unsigned long dev_addr)
950 {
951 struct fb_info_imstt *p = (struct fb_info_imstt *)dev_addr;
952 struct imstt_cursor *c = &p->cursor;
953
954 if (!c->enable)
955 goto out;
956
957 if (c->vbl_cnt && --c->vbl_cnt == 0) {
958 c->on ^= 1;
959 imstt_set_cursor(p, c->on);
960 c->vbl_cnt = c->blink_rate;
961 }
962
963 out:
964 c->timer.expires = jiffies + (HZ / 50);
965 add_timer(&c->timer);
966 }
967
968 static void __init
969 imstt_cursor_init (struct fb_info_imstt *p)
970 {
971 struct imstt_cursor *c = &p->cursor;
972
973 imsttfbcon_set_font(&p->disp, fontwidth(&p->disp), fontheight(&p->disp));
974
975 c->enable = 1;
976 c->on = 1;
977 c->x = c->y = 0;
978 c->blink_rate = 0;
979 c->vbl_cnt = CURSOR_DRAW_DELAY;
980
981 if (curblink) {
982 c->blink_rate = CURSOR_BLINK_RATE;
983 init_timer(&c->timer);
984 c->timer.expires = jiffies + (HZ / 50);
985 c->timer.data = (unsigned long)p;
986 c->timer.function = imstt_cursor_timer_handler;
987 add_timer(&c->timer);
988 }
989 }
990
991 static void
992 imsttfbcon_bmove (struct display *disp, int sy, int sx, int dy, int dx, int height, int width)
993 {
994 struct fb_info_imstt *p = (struct fb_info_imstt *)disp->fb_info;
995 __u32 Bpp, line_pitch,
996 fb_offset_old, fb_offset_new,
997 sp, dp_octl, cnt, bltctl;
998
999 Bpp = disp->var.bits_per_pixel >> 3,
1000
1001 sy *= fontheight(disp);
1002 sx *= fontwidth(disp);
1003 sx *= Bpp;
1004 dy *= fontheight(disp);
1005 dx *= fontwidth(disp);
1006 dx *= Bpp;
1007 height *= fontheight(disp);
1008 height--;
1009 width *= fontwidth(disp);
1010 width *= Bpp;
1011 width--;
1012
1013 line_pitch = disp->line_length;
1014 bltctl = 0x05;
1015 sp = line_pitch << 16;
1016 cnt = height << 16;
1017
1018 if (sy < dy) {
1019 sy += height;
1020 dy += height;
1021 sp |= -(line_pitch) & 0xffff;
1022 dp_octl = -(line_pitch) & 0xffff;
1023 } else {
1024 sp |= line_pitch;
1025 dp_octl = line_pitch;
1026 }
1027 if (sx < dx) {
1028 sx += width;
1029 dx += width;
1030 bltctl |= 0x80;
1031 cnt |= -(width) & 0xffff;
1032 } else {
1033 cnt |= width;
1034 }
1035 fb_offset_old = sy * line_pitch + sx;
1036 fb_offset_new = dy * line_pitch + dx;
1037
1038 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1039 out_le32(&p->dc_regs[S1SA], fb_offset_old);
1040 out_le32(&p->dc_regs[SP], sp);
1041 out_le32(&p->dc_regs[DSA], fb_offset_new);
1042 out_le32(&p->dc_regs[CNT], cnt);
1043 out_le32(&p->dc_regs[DP_OCTL], dp_octl);
1044 out_le32(&p->dc_regs[BLTCTL], bltctl);
1045 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1046 while(in_le32(&p->dc_regs[SSTATUS]) & 0x40);
1047 }
1048
1049 static void
1050 imsttfbcon_clear (struct vc_data *conp, struct display *disp,
1051 int sy, int sx, int height, int width)
1052 {
1053 struct fb_info_imstt *p = (struct fb_info_imstt *)disp->fb_info;
1054 __u32 Bpp, line_pitch, bgc;
1055
1056 bgc = attr_bgcol_ec(disp, conp);
1057 bgc |= (bgc << 8);
1058 bgc |= (bgc << 16);
1059
1060 Bpp = disp->var.bits_per_pixel >> 3,
1061 line_pitch = disp->line_length;
1062
1063 sy *= fontheight(disp);
1064 sy *= line_pitch;
1065 sx *= fontwidth(disp);
1066 sx *= Bpp;
1067 height *= fontheight(disp);
1068 height--;
1069 width *= fontwidth(disp);
1070 width *= Bpp;
1071 width--;
1072
1073 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1074 out_le32(&p->dc_regs[DSA], sy + sx);
1075 out_le32(&p->dc_regs[CNT], (height << 16) | width);
1076 out_le32(&p->dc_regs[DP_OCTL], line_pitch);
1077 out_le32(&p->dc_regs[BI], 0xffffffff);
1078 out_le32(&p->dc_regs[MBC], 0xffffffff);
1079 out_le32(&p->dc_regs[CLR], bgc);
1080 out_le32(&p->dc_regs[BLTCTL], 0x200000);
1081 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1082 while(in_le32(&p->dc_regs[SSTATUS]) & 0x40);
1083 }
1084
1085 static void
1086 imsttfbcon_revc (struct display *disp, int sx, int sy)
1087 {
1088 struct fb_info_imstt *p = (struct fb_info_imstt *)disp->fb_info;
1089 __u32 Bpp, line_pitch, height, width;
1090
1091 Bpp = disp->var.bits_per_pixel >> 3,
1092 line_pitch = disp->line_length;
1093
1094 height = fontheight(disp);
1095 width = fontwidth(disp) * Bpp;
1096 sy *= height;
1097 sy *= line_pitch;
1098 sx *= width;
1099 height--;
1100 width--;
1101
1102 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1103 out_le32(&p->dc_regs[DSA], sy + sx);
1104 out_le32(&p->dc_regs[S1SA], sy + sx);
1105 out_le32(&p->dc_regs[CNT], (height << 16) | width);
1106 out_le32(&p->dc_regs[DP_OCTL], line_pitch);
1107 out_le32(&p->dc_regs[SP], line_pitch);
1108 out_le32(&p->dc_regs[BLTCTL], 0x40005);
1109 while(in_le32(&p->dc_regs[SSTATUS]) & 0x80);
1110 while(in_le32(&p->dc_regs[SSTATUS]) & 0x40);
1111 }
1112
1113 #ifdef FBCON_HAS_CFB8
1114 static struct display_switch fbcon_imstt8 = {
1115 fbcon_cfb8_setup, imsttfbcon_bmove, imsttfbcon_clear, fbcon_cfb8_putc,
1116 fbcon_cfb8_putcs, imsttfbcon_revc, imsttfbcon_cursor, imsttfbcon_set_font, fbcon_cfb8_clear_margins,
1117 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1118 };
1119 #endif
1120 #ifdef FBCON_HAS_CFB16
1121 static struct display_switch fbcon_imstt16 = {
1122 fbcon_cfb16_setup, imsttfbcon_bmove, imsttfbcon_clear, fbcon_cfb16_putc,
1123 fbcon_cfb16_putcs, imsttfbcon_revc, imsttfbcon_cursor, imsttfbcon_set_font, fbcon_cfb16_clear_margins,
1124 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1125 };
1126 #endif
1127 #ifdef FBCON_HAS_CFB24
1128 static struct display_switch fbcon_imstt24 = {
1129 fbcon_cfb24_setup, imsttfbcon_bmove, imsttfbcon_clear, fbcon_cfb24_putc,
1130 fbcon_cfb24_putcs, imsttfbcon_revc, imsttfbcon_cursor, imsttfbcon_set_font, fbcon_cfb24_clear_margins,
1131 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1132 };
1133 #endif
1134 #ifdef FBCON_HAS_CFB32
1135 static struct display_switch fbcon_imstt32 = {
1136 fbcon_cfb32_setup, imsttfbcon_bmove, imsttfbcon_clear, fbcon_cfb32_putc,
1137 fbcon_cfb32_putcs, imsttfbcon_revc, imsttfbcon_cursor, imsttfbcon_set_font, fbcon_cfb32_clear_margins,
1138 FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1139 };
1140 #endif
1141
1142 #ifdef CONFIG_FB_COMPAT_XPMAC
1143 #include <asm/vc_ioctl.h>
1144
1145 extern struct vc_mode display_info;
1146 extern struct fb_info *console_fb_info;
1147
1148 static void
1149 set_display_info (struct display *disp)
1150 {
1151 display_info.width = disp->var.xres;
1152 display_info.height = disp->var.yres;
1153 display_info.depth = disp->var.bits_per_pixel;
1154 display_info.pitch = disp->line_length;
1155
1156 switch (disp->var.xres) {
1157 case 512:
1158 display_info.mode = 2;
1159 break;
1160 case 640:
1161 display_info.mode = 6;
1162 break;
1163 case 800:
1164 display_info.mode = 12;
1165 break;
1166 case 832:
1167 display_info.mode = 13;
1168 break;
1169 case 1024:
1170 display_info.mode = 17;
1171 break;
1172 case 1152:
1173 display_info.mode = 18;
1174 break;
1175 case 1280:
1176 display_info.mode = disp->var.yres == 960 ? 19 : 20;
1177 break;
1178 default:
1179 display_info.mode = 0;
1180 }
1181 }
1182 #endif
1183
1184 static int
1185 imsttfb_getcolreg (u_int regno, u_int *red, u_int *green,
1186 u_int *blue, u_int *transp, struct fb_info *info)
1187 {
1188 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1189
1190 if (regno > 255)
1191 return 1;
1192 *red = (p->palette[regno].red << 8) | p->palette[regno].red;
1193 *green = (p->palette[regno].green << 8) | p->palette[regno].green;
1194 *blue = (p->palette[regno].blue << 8) | p->palette[regno].blue;
1195 *transp = 0;
1196
1197 return 0;
1198 }
1199
1200 static int
1201 imsttfb_setcolreg (u_int regno, u_int red, u_int green, u_int blue,
1202 u_int transp, struct fb_info *info)
1203 {
1204 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1205 u_int bpp = fb_display[currcon].var.bits_per_pixel;
1206 u_int i;
1207
1208 if (regno > 255)
1209 return 1;
1210
1211 red >>= 8;
1212 green >>= 8;
1213 blue >>= 8;
1214
1215 p->palette[regno].red = red;
1216 p->palette[regno].green = green;
1217 p->palette[regno].blue = blue;
1218
1219 /* PADDRW/PDATA are the same as TVPPADDRW/TVPPDATA */
1220 if (0 && bpp == 16) /* screws up X */
1221 p->cmap_regs[PADDRW] = regno << 3;
1222 else
1223 p->cmap_regs[PADDRW] = regno;
1224 eieio();
1225
1226 p->cmap_regs[PDATA] = red; eieio();
1227 p->cmap_regs[PDATA] = green; eieio();
1228 p->cmap_regs[PDATA] = blue; eieio();
1229
1230 if (regno < 16)
1231 switch (bpp) {
1232 #ifdef FBCON_HAS_CFB16
1233 case 16:
1234 p->fbcon_cmap.cfb16[regno] = (regno << (fb_display[currcon].var.green.length == 5 ? 10 : 11)) | (regno << 5) | regno;
1235 break;
1236 #endif
1237 #ifdef FBCON_HAS_CFB24
1238 case 24:
1239 p->fbcon_cmap.cfb24[regno] = (regno << 16) | (regno << 8) | regno;
1240 break;
1241 #endif
1242 #ifdef FBCON_HAS_CFB32
1243 case 32:
1244 i = (regno << 8) | regno;
1245 p->fbcon_cmap.cfb32[regno] = (i << 16) | i;
1246 break;
1247 #endif
1248 }
1249
1250 return 0;
1251 }
1252
1253 static void
1254 do_install_cmap (int con, struct fb_info *info)
1255 {
1256 if (fb_display[con].cmap.len)
1257 fb_set_cmap(&fb_display[con].cmap, 1, imsttfb_setcolreg, info);
1258 else {
1259 u_int size = fb_display[con].var.bits_per_pixel == 16 ? 32 : 256;
1260 fb_set_cmap(fb_default_cmap(size), 1, imsttfb_setcolreg, info);
1261 }
1262 }
1263
1264 static int
1265 imsttfb_open (struct fb_info *info, int user)
1266 {
1267 MOD_INC_USE_COUNT;
1268 return 0;
1269 }
1270
1271 static int
1272 imsttfb_release (struct fb_info *info, int user)
1273 {
1274 MOD_DEC_USE_COUNT;
1275 return 0;
1276 }
1277
1278 static int
1279 imsttfb_get_fix (struct fb_fix_screeninfo *fix, int con, struct fb_info *info)
1280 {
1281 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1282 struct fb_var_screeninfo *var = &fb_display[con].var;
1283
1284 *fix = p->fix;
1285 fix->visual = var->bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR
1286 : FB_VISUAL_DIRECTCOLOR;
1287 fix->line_length = var->xres * (var->bits_per_pixel >> 3);
1288
1289 return 0;
1290 }
1291
1292 static int
1293 imsttfb_get_var (struct fb_var_screeninfo *var, int con, struct fb_info *info)
1294 {
1295 *var = fb_display[con].var;
1296
1297 return 0;
1298 }
1299
1300 static void
1301 set_dispsw (struct display *disp, struct fb_info_imstt *p)
1302 {
1303 u_int accel = disp->var.accel_flags & FB_ACCELF_TEXT;
1304
1305 if (disp->conp && disp->conp->vc_sw && disp->conp->vc_sw->con_cursor)
1306 disp->conp->vc_sw->con_cursor(disp->conp, CM_ERASE);
1307
1308 p->dispsw = fbcon_dummy;
1309 disp->dispsw = &p->dispsw;
1310 disp->dispsw_data = 0;
1311 switch (disp->var.bits_per_pixel) {
1312 case 8:
1313 disp->var.red.offset = 0;
1314 disp->var.red.length = 8;
1315 disp->var.green.offset = 0;
1316 disp->var.green.length = 8;
1317 disp->var.blue.offset = 0;
1318 disp->var.blue.length = 8;
1319 disp->var.transp.offset = 0;
1320 disp->var.transp.length = 0;
1321 #ifdef FBCON_HAS_CFB8
1322 p->dispsw = accel ? fbcon_imstt8 : fbcon_cfb8;
1323 #endif
1324 break;
1325 case 16: /* RGB 555 or 565 */
1326 if (disp->var.green.length != 6)
1327 disp->var.red.offset = 10;
1328 disp->var.red.length = 5;
1329 disp->var.green.offset = 5;
1330 if (disp->var.green.length != 6)
1331 disp->var.green.length = 5;
1332 disp->var.blue.offset = 0;
1333 disp->var.blue.length = 5;
1334 disp->var.transp.offset = 0;
1335 disp->var.transp.length = 0;
1336 #ifdef FBCON_HAS_CFB16
1337 p->dispsw = accel ? fbcon_imstt16 : fbcon_cfb16;
1338 disp->dispsw_data = p->fbcon_cmap.cfb16;
1339 #endif
1340 break;
1341 case 24: /* RGB 888 */
1342 disp->var.red.offset = 16;
1343 disp->var.red.length = 8;
1344 disp->var.green.offset = 8;
1345 disp->var.green.length = 8;
1346 disp->var.blue.offset = 0;
1347 disp->var.blue.length = 8;
1348 disp->var.transp.offset = 0;
1349 disp->var.transp.length = 0;
1350 #ifdef FBCON_HAS_CFB24
1351 p->dispsw = accel ? fbcon_imstt24 : fbcon_cfb24;
1352 disp->dispsw_data = p->fbcon_cmap.cfb24;
1353 #endif
1354 break;
1355 case 32: /* RGBA 8888 */
1356 disp->var.red.offset = 16;
1357 disp->var.red.length = 8;
1358 disp->var.green.offset = 8;
1359 disp->var.green.length = 8;
1360 disp->var.blue.offset = 0;
1361 disp->var.blue.length = 8;
1362 disp->var.transp.offset = 24;
1363 disp->var.transp.length = 8;
1364 #ifdef FBCON_HAS_CFB32
1365 p->dispsw = accel ? fbcon_imstt32 : fbcon_cfb32;
1366 disp->dispsw_data = p->fbcon_cmap.cfb32;
1367 #endif
1368 break;
1369 }
1370
1371 if (accel && p->ramdac != IBM) {
1372 p->dispsw.cursor = 0;
1373 p->dispsw.set_font = 0;
1374 }
1375
1376 #ifdef CONFIG_FB_COMPAT_XPMAC
1377 set_display_info(disp);
1378 #endif
1379 }
1380
1381 static void
1382 set_disp (struct display *disp, struct fb_info_imstt *p)
1383 {
1384 u_int accel = disp->var.accel_flags & FB_ACCELF_TEXT;
1385
1386 disp->fb_info = &p->info;
1387
1388 set_dispsw(disp, p);
1389
1390 disp->visual = disp->var.bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR
1391 : FB_VISUAL_DIRECTCOLOR;
1392 disp->screen_base = (__u8 *)p->frame_buffer;
1393 disp->visual = p->fix.visual;
1394 disp->type = p->fix.type;
1395 disp->type_aux = p->fix.type_aux;
1396 disp->line_length = disp->var.xres * (disp->var.bits_per_pixel >> 3);
1397 disp->can_soft_blank = 1;
1398 disp->inverse = 0;
1399 disp->ypanstep = 1;
1400 disp->ywrapstep = 0;
1401 if (accel) {
1402 disp->scrollmode = SCROLL_YNOMOVE;
1403 if (disp->var.yres == disp->var.yres_virtual) {
1404 __u32 vram = (p->total_vram - (PAGE_SIZE << 2));
1405 disp->var.yres_virtual = ((vram << 3) / disp->var.bits_per_pixel) / disp->var.xres_virtual;
1406 if (disp->var.yres_virtual < disp->var.yres)
1407 disp->var.yres_virtual = disp->var.yres;
1408 }
1409 } else {
1410 disp->scrollmode = SCROLL_YREDRAW;
1411 }
1412
1413 disp->var.activate = 0;
1414 disp->var.red.msb_right = 0;
1415 disp->var.green.msb_right = 0;
1416 disp->var.blue.msb_right = 0;
1417 disp->var.transp.msb_right = 0;
1418 disp->var.height = -1;
1419 disp->var.width = -1;
1420 disp->var.vmode = FB_VMODE_NONINTERLACED;
1421 disp->var.left_margin = disp->var.right_margin = 16;
1422 disp->var.upper_margin = disp->var.lower_margin = 16;
1423 disp->var.hsync_len = disp->var.vsync_len = 8;
1424 }
1425
1426 static int
1427 imsttfb_set_var (struct fb_var_screeninfo *var, int con, struct fb_info *info)
1428 {
1429 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1430 struct display *disp;
1431 u_int oldbpp, oldxres, oldyres, oldgreenlen, oldaccel;
1432
1433 disp = &fb_display[con];
1434
1435 if ((var->bits_per_pixel != 8 && var->bits_per_pixel != 16
1436 && var->bits_per_pixel != 24 && var->bits_per_pixel != 32)
1437 || var->xres_virtual < var->xres || var->yres_virtual < var->yres
1438 || var->nonstd
1439 || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1440 return -EINVAL;
1441
1442 if ((var->xres * var->yres) * (var->bits_per_pixel >> 3) > p->total_vram
1443 || (var->xres_virtual * var->yres_virtual) * (var->bits_per_pixel >> 3) > p->total_vram)
1444 return -EINVAL;
1445
1446 if (!((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW))
1447 return 0;
1448
1449 if (!compute_imstt_regvals(p, var->xres, var->yres))
1450 return -EINVAL;
1451
1452 oldbpp = disp->var.bits_per_pixel;
1453 oldxres = disp->var.xres;
1454 oldyres = disp->var.yres;
1455 oldgreenlen = disp->var.green.length;
1456 oldaccel = disp->var.accel_flags;
1457
1458 disp->var.bits_per_pixel = var->bits_per_pixel;
1459 disp->var.xres = var->xres;
1460 disp->var.yres = var->yres;
1461 disp->var.xres_virtual = var->xres_virtual;
1462 disp->var.yres_virtual = var->yres_virtual;
1463 disp->var.green.length = var->green.length;
1464 disp->var.accel_flags = var->accel_flags;
1465
1466 set_disp(disp, p);
1467
1468 if (info->changevar)
1469 (*info->changevar)(con);
1470
1471 if (con == currcon) {
1472 if (oldgreenlen != disp->var.green.length) {
1473 if (disp->var.green.length == 6)
1474 set_565(p);
1475 else
1476 set_555(p);
1477 }
1478 if (oldxres != disp->var.xres || oldyres != disp->var.yres || oldbpp != disp->var.bits_per_pixel)
1479 set_imstt_regvals(p, disp->var.bits_per_pixel);
1480
1481 }
1482 disp->var.pixclock = 1000000 / getclkMHz(p);
1483
1484 if (oldbpp != disp->var.bits_per_pixel) {
1485 int err = fb_alloc_cmap(&disp->cmap, 0, 0);
1486 if (err)
1487 return err;
1488 do_install_cmap(con, info);
1489 }
1490 *var = disp->var;
1491
1492 return 0;
1493 }
1494
1495 static int
1496 imsttfb_pan_display (struct fb_var_screeninfo *var, int con, struct fb_info *info)
1497 {
1498 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1499 struct display *disp = &fb_display[con];
1500
1501 if (var->xoffset + disp->var.xres > disp->var.xres_virtual
1502 || var->yoffset + disp->var.yres > disp->var.yres_virtual)
1503 return -EINVAL;
1504
1505 disp->var.xoffset = var->xoffset;
1506 disp->var.yoffset = var->yoffset;
1507 if (con == currcon)
1508 set_offset(disp, p);
1509
1510 return 0;
1511 }
1512
1513 static int
1514 imsttfb_get_cmap (struct fb_cmap *cmap, int kspc, int con, struct fb_info *info)
1515 {
1516 if (con == currcon) /* current console? */
1517 return fb_get_cmap(cmap, kspc, imsttfb_getcolreg, info);
1518 else if (fb_display[con].cmap.len) /* non default colormap? */
1519 fb_copy_cmap(&fb_display[con].cmap, cmap, kspc ? 0 : 2);
1520 else {
1521 u_int size = fb_display[con].var.bits_per_pixel == 16 ? 32 : 256;
1522 fb_copy_cmap(fb_default_cmap(size), cmap, kspc ? 0 : 2);
1523 }
1524
1525 return 0;
1526 }
1527
1528 static int
1529 imsttfb_set_cmap (struct fb_cmap *cmap, int kspc, int con, struct fb_info *info)
1530 {
1531 int err;
1532
1533 if (!fb_display[con].cmap.len) { /* no colormap allocated? */
1534 int size = fb_display[con].var.bits_per_pixel == 16 ? 32 : 256;
1535 if ((err = fb_alloc_cmap(&fb_display[con].cmap, size, 0)))
1536 return err;
1537 }
1538 if (con == currcon) /* current console? */
1539 return fb_set_cmap(cmap, kspc, imsttfb_setcolreg, info);
1540 else
1541 fb_copy_cmap(cmap, &fb_display[con].cmap, kspc ? 0 : 1);
1542
1543 return 0;
1544 }
1545
1546 #define FBIMSTT_SETREG 0x545401
1547 #define FBIMSTT_GETREG 0x545402
1548 #define FBIMSTT_SETCMAPREG 0x545403
1549 #define FBIMSTT_GETCMAPREG 0x545404
1550 #define FBIMSTT_SETIDXREG 0x545405
1551 #define FBIMSTT_GETIDXREG 0x545406
1552
1553 static int
1554 imsttfb_ioctl (struct inode *inode, struct file *file, u_int cmd,
1555 u_long arg, int con, struct fb_info *info)
1556 {
1557 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1558 __u8 idx[2];
1559 __u32 reg[2];
1560
1561 switch (cmd) {
1562 case FBIMSTT_SETREG:
1563 if (copy_from_user(reg, (void *)arg, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1564 return -EFAULT;
1565 out_le32(&p->dc_regs[reg[0]], reg[1]);
1566 return 0;
1567 case FBIMSTT_GETREG:
1568 if (copy_from_user(reg, (void *)arg, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1569 return -EFAULT;
1570 reg[1] = in_le32(&p->dc_regs[reg[0]]);
1571 if (copy_to_user((void *)(arg + 4), &reg[1], 4))
1572 return -EFAULT;
1573 return 0;
1574 case FBIMSTT_SETCMAPREG:
1575 if (copy_from_user(reg, (void *)arg, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1576 return -EFAULT;
1577 out_le32(&((u_int *)p->cmap_regs)[reg[0]], reg[1]);
1578 return 0;
1579 case FBIMSTT_GETCMAPREG:
1580 if (copy_from_user(reg, (void *)arg, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
1581 return -EFAULT;
1582 reg[1] = in_le32(&((u_int *)p->cmap_regs)[reg[0]]);
1583 if (copy_to_user((void *)(arg + 4), &reg[1], 4))
1584 return -EFAULT;
1585 return 0;
1586 case FBIMSTT_SETIDXREG:
1587 if (copy_from_user(idx, (void *)arg, 2))
1588 return -EFAULT;
1589 p->cmap_regs[PIDXHI] = 0; eieio();
1590 p->cmap_regs[PIDXLO] = idx[0]; eieio();
1591 p->cmap_regs[PIDXDATA] = idx[1]; eieio();
1592 return 0;
1593 case FBIMSTT_GETIDXREG:
1594 if (copy_from_user(idx, (void *)arg, 1))
1595 return -EFAULT;
1596 p->cmap_regs[PIDXHI] = 0; eieio();
1597 p->cmap_regs[PIDXLO] = idx[0]; eieio();
1598 idx[1] = p->cmap_regs[PIDXDATA];
1599 if (copy_to_user((void *)(arg + 1), &idx[1], 1))
1600 return -EFAULT;
1601 return 0;
1602 default:
1603 return -ENOIOCTLCMD;
1604 }
1605 }
1606
1607 static struct fb_ops imsttfb_ops = {
1608 imsttfb_open,
1609 imsttfb_release,
1610 imsttfb_get_fix,
1611 imsttfb_get_var,
1612 imsttfb_set_var,
1613 imsttfb_get_cmap,
1614 imsttfb_set_cmap,
1615 imsttfb_pan_display,
1616 imsttfb_ioctl
1617 };
1618
1619 static int
1620 imsttfbcon_switch (int con, struct fb_info *info)
1621 {
1622 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1623 struct display *old = &fb_display[currcon], *new = &fb_display[con];
1624
1625 if (old->cmap.len)
1626 fb_get_cmap(&old->cmap, 1, imsttfb_getcolreg, info);
1627
1628 if (old->conp && old->conp->vc_sw && old->conp->vc_sw->con_cursor)
1629 old->conp->vc_sw->con_cursor(old->conp, CM_ERASE);
1630
1631 currcon = con;
1632
1633 if (old->var.xres != new->var.xres
1634 || old->var.yres != new->var.yres
1635 || old->var.bits_per_pixel != new->var.bits_per_pixel
1636 || old->var.green.length != new->var.green.length
1637 || old->var.accel_flags != new->var.accel_flags) {
1638 set_dispsw(new, p);
1639 if (!compute_imstt_regvals(p, new->var.xres, new->var.yres))
1640 return -1;
1641 if (new->var.bits_per_pixel == 16) {
1642 if (new->var.green.length == 6)
1643 set_565(p);
1644 else
1645 set_555(p);
1646 }
1647 set_imstt_regvals(p, new->var.bits_per_pixel);
1648 }
1649 set_offset(new, p);
1650
1651 imsttfbcon_set_font(new, fontwidth(new), fontheight(new));
1652
1653 do_install_cmap(con, info);
1654
1655 return 0;
1656 }
1657
1658 static int
1659 imsttfbcon_updatevar (int con, struct fb_info *info)
1660 {
1661 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1662 struct display *disp = &fb_display[con];
1663
1664 if (con != currcon)
1665 goto out;
1666
1667 if (p->ramdac == IBM)
1668 imsttfbcon_cursor(disp, CM_ERASE, p->cursor.x, p->cursor.y);
1669
1670 set_offset(disp, p);
1671
1672 out:
1673 return 0;
1674 }
1675
1676 static void
1677 imsttfbcon_blank (int blank, struct fb_info *info)
1678 {
1679 struct fb_info_imstt *p = (struct fb_info_imstt *)info;
1680 __u32 ctrl;
1681
1682 ctrl = in_le32(&p->dc_regs[STGCTL]);
1683 if (blank > 0) {
1684 switch (blank - 1) {
1685 case VESA_NO_BLANKING:
1686 case VESA_POWERDOWN:
1687 ctrl &= ~0x00000380;
1688 if (p->ramdac == IBM) {
1689 p->cmap_regs[PIDXHI] = 0; eieio();
1690 p->cmap_regs[PIDXLO] = MISCTL2; eieio();
1691 p->cmap_regs[PIDXDATA] = 0x55; eieio();
1692 p->cmap_regs[PIDXLO] = MISCTL1; eieio();
1693 p->cmap_regs[PIDXDATA] = 0x11; eieio();
1694 p->cmap_regs[PIDXLO] = SYNCCTL; eieio();
1695 p->cmap_regs[PIDXDATA] = 0x0f; eieio();
1696 p->cmap_regs[PIDXLO] = PWRMNGMT;eieio();
1697 p->cmap_regs[PIDXDATA] = 0x1f; eieio();
1698 p->cmap_regs[PIDXLO] = CLKCTL; eieio();
1699 p->cmap_regs[PIDXDATA] = 0xc0;
1700 }
1701 break;
1702 case VESA_VSYNC_SUSPEND:
1703 ctrl &= ~0x00000020;
1704 break;
1705 case VESA_HSYNC_SUSPEND:
1706 ctrl &= ~0x00000010;
1707 break;
1708 }
1709 } else {
1710 if (p->ramdac == IBM) {
1711 ctrl |= 0x000017b0;
1712 p->cmap_regs[PIDXHI] = 0; eieio();
1713 p->cmap_regs[PIDXLO] = CLKCTL; eieio();
1714 p->cmap_regs[PIDXDATA] = 0x01; eieio();
1715 p->cmap_regs[PIDXLO] = PWRMNGMT;eieio();
1716 p->cmap_regs[PIDXDATA] = 0x00; eieio();
1717 p->cmap_regs[PIDXLO] = SYNCCTL; eieio();
1718 p->cmap_regs[PIDXDATA] = 0x00; eieio();
1719 p->cmap_regs[PIDXLO] = MISCTL1; eieio();
1720 p->cmap_regs[PIDXDATA] = 0x01; eieio();
1721 p->cmap_regs[PIDXLO] = MISCTL2; eieio();
1722 p->cmap_regs[PIDXDATA] = 0x45; eieio();
1723 } else
1724 ctrl |= 0x00001780;
1725 }
1726 out_le32(&p->dc_regs[STGCTL], ctrl);
1727 }
1728
1729 static void __init
1730 init_imstt(struct fb_info_imstt *p)
1731 {
1732 __u32 i, tmp;
1733 __u32 *ip, *end;
1734
1735 tmp = in_le32(&p->dc_regs[PRC]);
1736 if (p->ramdac == IBM)
1737 p->total_vram = (tmp & 0x0004) ? 0x400000 : 0x200000;
1738 else
1739 p->total_vram = 0x800000;
1740
1741 ip = (__u32 *)p->frame_buffer;
1742 end = (__u32 *)(p->frame_buffer + p->total_vram);
1743 while (ip < end)
1744 *ip++ = 0;
1745
1746 /* initialize the card */
1747 tmp = in_le32(&p->dc_regs[STGCTL]);
1748 out_le32(&p->dc_regs[STGCTL], tmp & ~0x1);
1749 out_le32(&p->dc_regs[SSR], 0);
1750
1751 /* set default values for DAC registers */
1752 if (p->ramdac == IBM) {
1753 p->cmap_regs[PPMASK] = 0xff; eieio();
1754 p->cmap_regs[PIDXHI] = 0; eieio();
1755 for (i = 0; i < sizeof(ibm_initregs) / sizeof(*ibm_initregs); i++) {
1756 p->cmap_regs[PIDXLO] = ibm_initregs[i].addr; eieio();
1757 p->cmap_regs[PIDXDATA] = ibm_initregs[i].value; eieio();
1758 }
1759 } else {
1760 for (i = 0; i < sizeof(tvp_initregs) / sizeof(*tvp_initregs); i++) {
1761 p->cmap_regs[TVPADDRW] = tvp_initregs[i].addr; eieio();
1762 p->cmap_regs[TVPIDATA] = tvp_initregs[i].value; eieio();
1763 }
1764 }
1765
1766 #if USE_NV_MODES && defined(CONFIG_PPC)
1767 {
1768 int vmode = init_vmode, cmode = init_cmode;
1769
1770 if (vmode == -1) {
1771 vmode = nvram_read_byte(NV_VMODE);
1772 if (vmode <= 0 || vmode > VMODE_MAX)
1773 vmode = VMODE_640_480_67;
1774 }
1775 if (cmode == -1) {
1776 cmode = nvram_read_byte(NV_CMODE);
1777 if (cmode < CMODE_8 || cmode > CMODE_32)
1778 cmode = CMODE_8;
1779 }
1780 if (mac_vmode_to_var(vmode, cmode, &p->disp.var)) {
1781 p->disp.var.xres = p->disp.var.xres_virtual = INIT_XRES;
1782 p->disp.var.yres = p->disp.var.yres_virtual = INIT_YRES;
1783 p->disp.var.bits_per_pixel = INIT_BPP;
1784 }
1785 }
1786 #else
1787 p->disp.var.xres = p->disp.var.xres_virtual = INIT_XRES;
1788 p->disp.var.yres = p->disp.var.yres_virtual = INIT_YRES;
1789 p->disp.var.bits_per_pixel = INIT_BPP;
1790 #endif
1791
1792 if ((p->disp.var.xres * p->disp.var.yres) * (p->disp.var.bits_per_pixel >> 3) > p->total_vram
1793 || !(compute_imstt_regvals(p, p->disp.var.xres, p->disp.var.yres))) {
1794 printk("imsttfb: %ux%ux%u not supported\n", p->disp.var.xres, p->disp.var.yres, p->disp.var.bits_per_pixel);
1795 kfree(p);
1796 return;
1797 }
1798
1799 sprintf(p->fix.id, "IMS TT (%s)", p->ramdac == IBM ? "IBM" : "TVP");
1800 p->fix.smem_start = p->frame_buffer_phys;
1801 p->fix.smem_len = p->total_vram;
1802 p->fix.mmio_start = p->dc_regs_phys;
1803 p->fix.mmio_len = 0x1000;
1804 p->fix.accel = FB_ACCEL_IMS_TWINTURBO;
1805 p->fix.type = FB_TYPE_PACKED_PIXELS;
1806 p->fix.visual = p->disp.var.bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR
1807 : FB_VISUAL_DIRECTCOLOR;
1808 p->fix.line_length = p->disp.var.xres * (p->disp.var.bits_per_pixel >> 3);
1809 p->fix.xpanstep = 8;
1810 p->fix.ypanstep = 1;
1811 p->fix.ywrapstep = 0;
1812
1813 p->disp.var.accel_flags = noaccel ? 0 : FB_ACCELF_TEXT;
1814 set_disp(&p->disp, p);
1815
1816 if (!noaccel && p->ramdac == IBM)
1817 imstt_cursor_init(p);
1818 if (p->disp.var.green.length == 6)
1819 set_565(p);
1820 else
1821 set_555(p);
1822 set_imstt_regvals(p, p->disp.var.bits_per_pixel);
1823
1824 p->disp.var.pixclock = 1000000 / getclkMHz(p);
1825
1826 strcpy(p->info.modename, p->fix.id);
1827 strcpy(p->info.fontname, fontname);
1828 p->info.node = -1;
1829 p->info.fbops = &imsttfb_ops;
1830 p->info.disp = &p->disp;
1831 p->info.changevar = 0;
1832 p->info.switch_con = &imsttfbcon_switch;
1833 p->info.updatevar = &imsttfbcon_updatevar;
1834 p->info.blank = &imsttfbcon_blank;
1835 p->info.flags = FBINFO_FLAG_DEFAULT;
1836
1837 for (i = 0; i < 16; i++) {
1838 u_int j = color_table[i];
1839 p->palette[i].red = default_red[j];
1840 p->palette[i].green = default_grn[j];
1841 p->palette[i].blue = default_blu[j];
1842 }
1843
1844 if (register_framebuffer(&p->info) < 0) {
1845 kfree(p);
1846 return;
1847 }
1848
1849 i = GET_FB_IDX(p->info.node);
1850 tmp = (in_le32(&p->dc_regs[SSTATUS]) & 0x0f00) >> 8;
1851 printk("fb%u: %s frame buffer; %uMB vram; chip version %u\n",
1852 i, p->fix.id, p->total_vram >> 20, tmp);
1853
1854 fb_info_imstt_p[i] = p;
1855 #ifdef CONFIG_FB_COMPAT_XPMAC
1856 strncpy(display_info.name, "IMS,tt128mb", sizeof(display_info.name));
1857 display_info.fb_address = (__u32)p->frame_buffer_phys;
1858 display_info.cmap_adr_address = (__u32)&p->cmap_regs_phys[PADDRW];
1859 display_info.cmap_data_address = (__u32)&p->cmap_regs_phys[PDATA];
1860 display_info.disp_reg_address = (__u32)p->dc_regs_phys;
1861 if (!console_fb_info)
1862 console_fb_info = &p->info;
1863 #endif /* CONFIG_FB_COMPAT_XPMAC */
1864 }
1865
1866 #if defined(CONFIG_FB_OF) && !defined(MODULE)
1867 void __init
1868 imsttfb_of_init(struct device_node *dp)
1869 {
1870 struct fb_info_imstt *p;
1871 int i;
1872 __u32 addr = 0;
1873 __u8 bus, devfn;
1874 __u16 cmd;
1875
1876 for (i = 0; i < dp->n_addrs; i++) {
1877 if (dp->addrs[i].size >= 0x02000000)
1878 addr = dp->addrs[i].address;
1879 }
1880 if (!addr)
1881 return;
1882
1883 if (!pci_device_loc(dp, &bus, &devfn)) {
1884 if (!pcibios_read_config_word(bus, devfn, PCI_COMMAND, &cmd) && !(cmd & PCI_COMMAND_MEMORY)) {
1885 cmd |= PCI_COMMAND_MEMORY;
1886 pcibios_write_config_word(bus, devfn, PCI_COMMAND, cmd);
1887 }
1888 }
1889
1890 p = kmalloc(sizeof(struct fb_info_imstt), GFP_ATOMIC);
1891 if (!p)
1892 return;
1893 memset(p, 0, sizeof(struct fb_info_imstt));
1894
1895 if (dp->name[11] == '8' || (dp->name[6] == '3' && dp->name[7] == 'd'))
1896 p->ramdac = TVP;
1897 else
1898 p->ramdac = IBM;
1899
1900 p->frame_buffer_phys = (__u8 *)addr;
1901 p->frame_buffer = (__u8 *)ioremap(addr, p->ramdac == IBM ? 0x400000 : 0x800000);
1902 p->dc_regs_phys = (__u32 *)(addr + 0x800000);
1903 p->dc_regs = (__u32 *)ioremap(addr + 0x800000, 0x1000);
1904 p->cmap_regs_phys = (__u8 *)(addr + 0x840000);
1905 p->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000);
1906
1907 init_imstt(p);
1908 }
1909 #endif
1910
1911 int __init
1912 imsttfb_init(void)
1913 {
1914 int i;
1915 #if defined(CONFIG_FB_OF) && !defined(MODULE)
1916 /* We don't want to be called like this. */
1917 /* We rely on Open Firmware (offb) instead. */
1918 #elif defined(CONFIG_PCI)
1919 struct pci_dev *pdev;
1920 struct fb_info_imstt *p;
1921 __u32 addr;
1922 __u16 cmd;
1923
1924 for (pdev = pci_devices; pdev; pdev = pdev->next) {
1925 if (!(((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
1926 && (pdev->vendor == PCI_VENDOR_ID_IMS)))
1927 continue;
1928
1929 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1930 if (!(cmd & PCI_COMMAND_MEMORY)) {
1931 cmd |= PCI_COMMAND_MEMORY;
1932 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1933 }
1934
1935 addr = pdev->resource[0].start;
1936 if (!addr)
1937 continue;
1938
1939 p = kmalloc(sizeof(struct fb_info_imstt), GFP_ATOMIC);
1940 if (!p)
1941 continue;
1942 memset(p, 0, sizeof(struct fb_info_imstt));
1943
1944 printk("imsttfb: device=%04x\n", pdev->device);
1945
1946 switch (pdev->device) {
1947 case 0x9128: /* IMS,tt128mbA */
1948 p->ramdac = IBM;
1949 break;
1950 case 0x9135: /* IMS,tt3d */
1951 default:
1952 p->ramdac = TVP;
1953 break;
1954 }
1955
1956 p->frame_buffer_phys = (__u8 *)addr;
1957 p->frame_buffer = (__u8 *)ioremap(addr, p->ramdac == IBM ? 0x400000 : 0x800000);
1958 p->dc_regs_phys = (__u32 *)(addr + 0x800000);
1959 p->dc_regs = (__u32 *)ioremap(addr + 0x800000, 0x1000);
1960 p->cmap_regs_phys = (__u8 *)(addr + 0x840000);
1961 p->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000);
1962
1963 init_imstt(p);
1964 }
1965 #endif /* CONFIG_PCI */
1966 for (i = 0; i < FB_MAX; i++) {
1967 if (fb_info_imstt_p[i])
1968 return 0;
1969 }
1970 return -ENXIO;
1971 }
1972
1973 #ifndef MODULE
1974 int __init
1975 imsttfb_setup(char *options)
1976 {
1977 char *this_opt;
1978
1979 if (!options || !*options)
1980 return 0;
1981
1982 for (this_opt = strtok(options, ","); this_opt;
1983 this_opt = strtok(NULL, ",")) {
1984 if (!strncmp(this_opt, "font:", 5)) {
1985 char *p;
1986 int i;
1987
1988 p = this_opt + 5;
1989 for (i = 0; i < sizeof(fontname) - 1; i++)
1990 if (!*p || *p == ' ' || *p == ',')
1991 break;
1992 memcpy(fontname, this_opt + 5, i);
1993 fontname[i] = 0;
1994 } else if (!strncmp(this_opt, "noblink", 7)) {
1995 curblink = 0;
1996 } else if (!strncmp(this_opt, "noaccel", 7)) {
1997 noaccel = 1;
1998 }
1999 #if defined(CONFIG_PPC)
2000 else if (!strncmp(this_opt, "vmode:", 6)) {
2001 int vmode = simple_strtoul(this_opt+6, NULL, 0);
2002 if (vmode > 0 && vmode <= VMODE_MAX)
2003 init_vmode = vmode;
2004 } else if (!strncmp(this_opt, "cmode:", 6)) {
2005 int cmode = simple_strtoul(this_opt+6, NULL, 0);
2006 switch (cmode) {
2007 case CMODE_8:
2008 case 8:
2009 init_cmode = CMODE_8;
2010 break;
2011 case CMODE_16:
2012 case 15:
2013 case 16:
2014 init_cmode = CMODE_16;
2015 break;
2016 case CMODE_32:
2017 case 24:
2018 case 32:
2019 init_cmode = CMODE_32;
2020 break;
2021 }
2022 }
2023 #endif
2024 }
2025 return 0;
2026 }
2027
2028 #else /* MODULE */
2029
2030 int __init
2031 init_module (void)
2032 {
2033
2034 return imsttfb_init();
2035 }
2036
2037 void
2038 cleanup_module (void)
2039 {
2040 struct fb_info_imstt *p;
2041 __u32 i;
2042
2043 for (i = 0; i < FB_MAX; i++) {
2044 p = fb_info_imstt_p[i];
2045 if (!p)
2046 continue;
2047 iounmap(p->cmap_regs);
2048 iounmap(p->dc_regs);
2049 iounmap(p->frame_buffer);
2050 kfree(p);
2051 }
2052 }
2053
2054 #include "macmodes.c"
2055 #endif /* MODULE */
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