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Import 2.3.15pre2
[davej-history.git] / drivers / pci / pci.c
blob8e42297646c3539ca99f56985bcc2efef5254245
1 /*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
10 */
11
12 #include <linux/config.h>
13 #include <linux/types.h>
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/malloc.h>
19
20 #include <asm/page.h>
21
22 #undef DEBUG
23
24 #ifdef DEBUG
25 #define DBG(x...) printk(x)
26 #else
27 #define DBG(x...)
28 #endif
29
30 extern void pci_namedevice(struct pci_dev *);
31
32 struct pci_bus pci_root;
33 struct pci_dev *pci_devices = NULL;
34 int pci_reverse __initdata = 0;
35
36 static struct pci_dev **pci_last_dev_p = &pci_devices;
37
38 struct pci_dev *
39 pci_find_slot(unsigned int bus, unsigned int devfn)
40 {
41 struct pci_dev *dev;
42
43 for(dev=pci_devices; dev; dev=dev->next)
44 if (dev->bus->number == bus && dev->devfn == devfn)
45 break;
46 return dev;
47 }
48
49
50 struct pci_dev *
51 pci_find_device(unsigned int vendor, unsigned int device, struct pci_dev *from)
52 {
53 struct pci_dev *next;
54
55 next = pci_devices;
56 if (from)
57 next = from->next;
58
59 while (next) {
60 struct pci_dev *dev = next;
61 next = next->next;
62 if (vendor != PCI_ANY_ID && dev->vendor != vendor)
63 continue;
64 if (device != PCI_ANY_ID && dev->device != device)
65 continue;
66
67 return dev;
68 }
69 return NULL;
70 }
71
72
73 struct pci_dev *
74 pci_find_class(unsigned int class, struct pci_dev *from)
75 {
76 if (!from)
77 from = pci_devices;
78 else
79 from = from->next;
80 while (from && from->class != class)
81 from = from->next;
82 return from;
83 }
84
85
86 int
87 pci_read_config_byte(struct pci_dev *dev, u8 where, u8 *val)
88 {
89 return pcibios_read_config_byte(dev->bus->number, dev->devfn, where, val);
90 }
91
92 int
93 pci_read_config_word(struct pci_dev *dev, u8 where, u16 *val)
94 {
95 return pcibios_read_config_word(dev->bus->number, dev->devfn, where, val);
96 }
97
98 int
99 pci_read_config_dword(struct pci_dev *dev, u8 where, u32 *val)
100 {
101 return pcibios_read_config_dword(dev->bus->number, dev->devfn, where, val);
102 }
103
104 int
105 pci_write_config_byte(struct pci_dev *dev, u8 where, u8 val)
106 {
107 return pcibios_write_config_byte(dev->bus->number, dev->devfn, where, val);
108 }
109
110 int
111 pci_write_config_word(struct pci_dev *dev, u8 where, u16 val)
112 {
113 return pcibios_write_config_word(dev->bus->number, dev->devfn, where, val);
114 }
115
116 int
117 pci_write_config_dword(struct pci_dev *dev, u8 where, u32 val)
118 {
119 return pcibios_write_config_dword(dev->bus->number, dev->devfn, where, val);
120 }
121
122
123 void
124 pci_set_master(struct pci_dev *dev)
125 {
126 u16 cmd;
127 u8 lat;
128
129 pci_read_config_word(dev, PCI_COMMAND, &cmd);
130 if (! (cmd & PCI_COMMAND_MASTER)) {
131 printk("PCI: Enabling bus mastering for device %02x:%02x\n",
132 dev->bus->number, dev->devfn);
133 cmd |= PCI_COMMAND_MASTER;
134 pci_write_config_word(dev, PCI_COMMAND, cmd);
135 }
136 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
137 if (lat < 16) {
138 printk("PCI: Increasing latency timer of device %02x:%02x to 64\n",
139 dev->bus->number, dev->devfn);
140 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
141 }
142 }
143
144 /*
145 * Translate the low bits of the PCI base
146 * to the resource type
147 */
148 static inline unsigned int pci_resource_flags(unsigned int flags)
149 {
150 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
151 return IORESOURCE_IO | flags;
152
153 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
154 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
155
156 return IORESOURCE_MEM;
157 }
158
159 void __init pci_read_bases(struct pci_dev *dev, unsigned int howmany)
160 {
161 unsigned int reg;
162 u32 l;
163
164 for(reg=0; reg < howmany; reg++) {
165 struct resource *res = dev->resource + reg;
166 unsigned int mask, newval, size;
167
168 res->name = dev->name;
169 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (reg << 2), &l);
170 if (l == 0xffffffff)
171 continue;
172
173 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + (reg << 2), 0xffffffff);
174 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (reg << 2), &newval);
175 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + (reg << 2), l);
176
177 mask = PCI_BASE_ADDRESS_MEM_MASK;
178 if (l & PCI_BASE_ADDRESS_SPACE_IO)
179 mask = PCI_BASE_ADDRESS_IO_MASK;
180
181 newval &= mask;
182 if (!newval)
183 continue;
184
185 res->start = l & mask;
186 l &= ~mask;
187 res->flags = l | pci_resource_flags(l);
188
189 size = 1;
190 do {
191 size <<= 1;
192 } while (!(size & newval));
193
194 /* 64-bit decode? */
195 if ((l & (PCI_BASE_ADDRESS_MEM_TYPE_MASK | PCI_BASE_ADDRESS_SPACE)) == PCI_BASE_ADDRESS_MEM_TYPE_64) {
196 unsigned int high;
197 reg++;
198 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (reg << 2), &high);
199 if (high) {
200 #if BITS_PER_LONG == 64
201 res->start |= ((unsigned long) high) << 32;
202 #else
203 printk("PCI: Unable to handle 64-bit address for device %02x:%02x\n",
204 dev->bus->number, dev->devfn);
205 res->flags = 0;
206 res->start = 0;
207 res->end = 0;
208 continue;
209 #endif
210 }
211 }
212 res->end = res->start + size - 1;
213 request_resource((l & PCI_BASE_ADDRESS_SPACE_IO) ? &ioport_resource : &iomem_resource, res);
214 }
215 }
216
217
218 unsigned int __init pci_scan_bus(struct pci_bus *bus)
219 {
220 unsigned int devfn, l, max, class;
221 unsigned char cmd, irq, tmp, hdr_type, is_multi = 0;
222 struct pci_dev *dev, **bus_last;
223 struct pci_bus *child;
224
225 DBG("pci_scan_bus for bus %d\n", bus->number);
226 bus_last = &bus->devices;
227 max = bus->secondary;
228 for (devfn = 0; devfn < 0xff; ++devfn) {
229 if (PCI_FUNC(devfn) && !is_multi) {
230 /* not a multi-function device */
231 continue;
232 }
233 if (pcibios_read_config_byte(bus->number, devfn, PCI_HEADER_TYPE, &hdr_type))
234 continue;
235 if (!PCI_FUNC(devfn))
236 is_multi = hdr_type & 0x80;
237
238 if (pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID, &l) ||
239 /* some broken boards return 0 if a slot is empty: */
240 l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff || l == 0xffff0000)
241 continue;
242
243 dev = kmalloc(sizeof(*dev), GFP_ATOMIC);
244 if(dev==NULL)
245 {
246 printk(KERN_ERR "pci: out of memory.\n");
247 continue;
248 }
249 memset(dev, 0, sizeof(*dev));
250 dev->bus = bus;
251 dev->devfn = devfn;
252 dev->vendor = l & 0xffff;
253 dev->device = (l >> 16) & 0xffff;
254 pci_namedevice(dev);
255
256 /* non-destructively determine if device can be a master: */
257 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND, &cmd);
258 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
259 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND, &tmp);
260 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
261 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND, cmd);
262
263 pcibios_read_config_dword(bus->number, devfn, PCI_CLASS_REVISION, &class);
264 class >>= 8; /* upper 3 bytes */
265 dev->class = class;
266 class >>= 8;
267 dev->hdr_type = hdr_type;
268
269 switch (hdr_type & 0x7f) { /* header type */
270 case PCI_HEADER_TYPE_NORMAL: /* standard header */
271 if (class == PCI_CLASS_BRIDGE_PCI)
272 goto bad;
273 /*
274 * If the card generates interrupts, read IRQ number
275 * (some architectures change it during pcibios_fixup())
276 */
277 pcibios_read_config_byte(bus->number, dev->devfn, PCI_INTERRUPT_PIN, &irq);
278 if (irq)
279 pcibios_read_config_byte(bus->number, dev->devfn, PCI_INTERRUPT_LINE, &irq);
280 dev->irq = irq;
281 /*
282 * read base address registers, again pcibios_fixup() can
283 * tweak these
284 */
285 pci_read_bases(dev, 6);
286 pcibios_read_config_dword(bus->number, devfn, PCI_ROM_ADDRESS, &l);
287 dev->rom_address = (l == 0xffffffff) ? 0 : l;
288 break;
289 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
290 if (class != PCI_CLASS_BRIDGE_PCI)
291 goto bad;
292 pci_read_bases(dev, 2);
293 pcibios_read_config_dword(bus->number, devfn, PCI_ROM_ADDRESS1, &l);
294 dev->rom_address = (l == 0xffffffff) ? 0 : l;
295 break;
296 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
297 if (class != PCI_CLASS_BRIDGE_CARDBUS)
298 goto bad;
299 pci_read_bases(dev, 1);
300 break;
301 default: /* unknown header */
302 bad:
303 printk(KERN_ERR "PCI: %02x:%02x [%04x/%04x/%06x] has unknown header type %02x, ignoring.\n",
304 bus->number, dev->devfn, dev->vendor, dev->device, class, hdr_type);
305 continue;
306 }
307
308 DBG("PCI: %02x:%02x [%04x/%04x]\n", bus->number, dev->devfn, dev->vendor, dev->device);
309
310 /*
311 * Put it into the global PCI device chain. It's used to
312 * find devices once everything is set up.
313 */
314 if (!pci_reverse) {
315 *pci_last_dev_p = dev;
316 pci_last_dev_p = &dev->next;
317 } else {
318 dev->next = pci_devices;
319 pci_devices = dev;
320 }
321
322 /*
323 * Now insert it into the list of devices held
324 * by the parent bus.
325 */
326 *bus_last = dev;
327 bus_last = &dev->sibling;
328
329 #if 0
330 /*
331 * Setting of latency timer in case it was less than 32 was
332 * a great idea, but it confused several broken devices. Grrr.
333 */
334 pcibios_read_config_byte(bus->number, dev->devfn, PCI_LATENCY_TIMER, &tmp);
335 if (tmp < 32)
336 pcibios_write_config_byte(bus->number, dev->devfn, PCI_LATENCY_TIMER, 32);
337 #endif
338 }
339
340 /*
341 * After performing arch-dependent fixup of the bus, look behind
342 * all PCI-to-PCI bridges on this bus.
343 */
344 pcibios_fixup_bus(bus);
345 for(dev=bus->devices; dev; dev=dev->sibling)
346 /*
347 * If it's a bridge, scan the bus behind it.
348 */
349 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
350 unsigned int buses;
351 unsigned int devfn = dev->devfn;
352 unsigned short cr;
353
354 /*
355 * Insert it into the tree of buses.
356 */
357 child = kmalloc(sizeof(*child), GFP_ATOMIC);
358 if(child==NULL)
359 {
360 printk(KERN_ERR "pci: out of memory for bridge.\n");
361 continue;
362 }
363 memset(child, 0, sizeof(*child));
364 child->next = bus->children;
365 bus->children = child;
366 child->self = dev;
367 child->parent = bus;
368
369 /*
370 * Set up the primary, secondary and subordinate
371 * bus numbers.
372 */
373 child->number = child->secondary = ++max;
374 child->primary = bus->secondary;
375 child->subordinate = 0xff;
376 /*
377 * Clear all status bits and turn off memory,
378 * I/O and master enables.
379 */
380 pcibios_read_config_word(bus->number, devfn, PCI_COMMAND, &cr);
381 pcibios_write_config_word(bus->number, devfn, PCI_COMMAND, 0x0000);
382 pcibios_write_config_word(bus->number, devfn, PCI_STATUS, 0xffff);
383 /*
384 * Read the existing primary/secondary/subordinate bus
385 * number configuration to determine if the PCI bridge
386 * has already been configured by the system. If so,
387 * do not modify the configuration, merely note it.
388 */
389 pcibios_read_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, &buses);
390 if ((buses & 0xFFFFFF) != 0)
391 {
392 unsigned int cmax;
393
394 child->primary = buses & 0xFF;
395 child->secondary = (buses >> 8) & 0xFF;
396 child->subordinate = (buses >> 16) & 0xFF;
397 child->number = child->secondary;
398 cmax = pci_scan_bus(child);
399 if (cmax > max) max = cmax;
400 }
401 else
402 {
403 /*
404 * Configure the bus numbers for this bridge:
405 */
406 buses &= 0xff000000;
407 buses |=
408 (((unsigned int)(child->primary) << 0) |
409 ((unsigned int)(child->secondary) << 8) |
410 ((unsigned int)(child->subordinate) << 16));
411 pcibios_write_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, buses);
412 /*
413 * Now we can scan all subordinate buses:
414 */
415 max = pci_scan_bus(child);
416 /*
417 * Set the subordinate bus number to its real
418 * value:
419 */
420 child->subordinate = max;
421 buses = (buses & 0xff00ffff)
422 | ((unsigned int)(child->subordinate) << 16);
423 pcibios_write_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, buses);
424 }
425 pcibios_write_config_word(bus->number, devfn, PCI_COMMAND, cr);
426 }
427
428 /*
429 * We've scanned the bus and so we know all about what's on
430 * the other side of any bridges that may be on this bus plus
431 * any devices.
432 *
433 * Return how far we've got finding sub-buses.
434 */
435 DBG("PCI: pci_scan_bus returning with max=%02x\n", max);
436 return max;
437 }
438
439 struct pci_bus * __init pci_scan_peer_bridge(int bus)
440 {
441 struct pci_bus *b;
442
443 b = kmalloc(sizeof(*b), GFP_KERNEL);
444 memset(b, 0, sizeof(*b));
445 b->next = pci_root.next;
446 pci_root.next = b;
447 b->number = b->secondary = bus;
448 b->subordinate = pci_scan_bus(b);
449 return b;
450 }
451
452 void __init pci_init(void)
453 {
454 pcibios_init();
455
456 if (!pci_present()) {
457 printk("PCI: No PCI bus detected\n");
458 return;
459 }
460
461 printk("PCI: Probing PCI hardware\n");
462
463 memset(&pci_root, 0, sizeof(pci_root));
464 pci_root.subordinate = pci_scan_bus(&pci_root);
465
466 /* give BIOS a chance to apply platform specific fixes: */
467 pcibios_fixup();
468
469 #ifdef CONFIG_PCI_QUIRKS
470 pci_quirks_init();
471 #endif
472 }
473
474 static int __init pci_setup(char *str)
475 {
476 while (str) {
477 char *k = strchr(str, ',');
478 if (k)
479 *k++ = 0;
480 if (*str && (str = pcibios_setup(str)) && *str) {
481 if (!strcmp(str, "reverse"))
482 pci_reverse = 1;
483 else printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
484 }
485 str = k;
486 }
487 return 1;
488 }
489
490 __setup("pci=", pci_setup);
Copy of Dave Jones history.git as used by http://archive.org/details/git-history-of-linux