drivers/block/trm290.c

   1 /*
   2  *  linux/drivers/block/trm290.c        Version 1.01  December 5, 1997
   3  *
   4  *  Copyright (c) 1997-1998  Mark Lord
   5  *  May be copied or modified under the terms of the GNU General Public License
   6  */
   7
   8 /*
   9  * This module provides support for the bus-master IDE DMA function
  10  * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
  11  * including a "Precision Instruments" board.  The TRM290 pre-dates
  12  * the sff-8038 standard (ide-dma.c) by a few months, and differs
  13  * significantly enough to warrant separate routines for some functions,
  14  * while re-using others from ide-dma.c.
  15  *
  16  * EXPERIMENTAL!  It works for me (a sample of one).
  17  *
  18  * Works reliably for me in DMA mode (READs only),
  19  * DMA WRITEs are disabled by default (see #define below);
  20  *
  21  * DMA is not enabled automatically for this chipset,
  22  * but can be turned on manually (with "hdparm -d1") at run time.
  23  *
  24  * I need volunteers with "spare" drives for further testing
  25  * and development, and maybe to help figure out the peculiarities.
  26  * Even knowing the registers (below), some things behave strangely.
  27  */
  28
  29 #define TRM290_NO_DMA_WRITES    /* DMA writes seem unreliable sometimes */
  30
  31 /*
  32  * TRM-290 PCI-IDE2 Bus Master Chip
  33  * ================================
  34  * The configuration registers are addressed in normal I/O port space
  35  * and are used as follows:
  36  *
  37  * trm290_base depends on jumper settings, and is probed for by ide-dma.c
  38  *
  39  * trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
  40  *      bit7 must always be written as "1"
  41  *      bits6-2 undefined
  42  *      bit1 1=legacy_compatible_mode, 0=native_pci_mode
  43  *      bit0 1=test_mode, 0=normal(default)
  44  *
  45  * trm290_base+2 when READ: status register (byte, read-only)
  46  *      bits7-2 undefined
  47  *      bit1 channel0 busmaster interrupt status 0=none, 1=asserted
  48  *      bit0 channel0 interrupt status 0=none, 1=asserted
  49  *
  50  * trm290_base+3 Interrupt mask register
  51  *      bits7-5 undefined
  52  *      bit4 legacy_header: 1=present, 0=absent
  53  *      bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
  54  *      bit2 channel1 interrupt status 0=none, 1=asserted (read only)
  55  *      bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
  56  *      bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
  57  *
  58  * trm290_base+1 "CPR" Config Pointer Register (byte)
  59  *      bit7 1=autoincrement CPR bits 2-0 after each access of CDR
  60  *      bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
  61  *      bit5 0=enabled master burst access (default), 1=disable  (write only)
  62  *      bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
  63  *      bit3 0=primary IDE channel, 1=secondary IDE channel
  64  *      bits2-0 register index for accesses through CDR port
  65  *
  66  * trm290_base+0 "CDR" Config Data Register (word)
  67  *      two sets of seven config registers,
  68  *      selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
  69  *      each index defined below:
  70  *
  71  * Index-0 Base address register for command block (word)
  72  *      defaults: 0x1f0 for primary, 0x170 for secondary
  73  *
  74  * Index-1 general config register (byte)
  75  *      bit7 1=DMA enable, 0=DMA disable
  76  *      bit6 1=activate IDE_RESET, 0=no action (default)
  77  *      bit5 1=enable IORDY, 0=disable IORDY (default)
  78  *      bit4 0=16-bit data port(default), 1=8-bit (XT) data port
  79  *      bit3 interrupt polarity: 1=active_low, 0=active_high(default)
  80  *      bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
  81  *      bit1 bus_master_mode(?): 1=enable, 0=disable(default)
  82  *      bit0 enable_io_ports: 1=enable(default), 0=disable
  83  *
  84  * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
  85  *      bits7-0 bits7-0 of readahead count
  86  *
  87  * Index-3 read-ahead config register (byte, write only)
  88  *      bit7 1=enable_readahead, 0=disable_readahead(default)
  89  *      bit6 1=clear_FIFO, 0=no_action
  90  *      bit5 undefined
  91  *      bit4 mode4 timing control: 1=enable, 0=disable(default)
  92  *      bit3 undefined
  93  *      bit2 undefined
  94  *      bits1-0 bits9-8 of read-ahead count
  95  *
  96  * Index-4 base address register for control block (word)
  97  *      defaults: 0x3f6 for primary, 0x376 for secondary
  98  *
  99  * Index-5 data port timings (shared by both drives) (byte)
 100  *      standard PCI "clk" (clock) counts, default value = 0xf5
 101  *
 102  *      bits7-6 setup time:  00=1clk, 01=2clk, 10=3clk, 11=4clk
 103  *      bits5-3 hold time:      000=1clk, 001=2clk, 010=3clk,
 104  *                              011=4clk, 100=5clk, 101=6clk,
 105  *                              110=8clk, 111=12clk
 106  *      bits2-0 active time:    000=2clk, 001=3clk, 010=4clk,
 107  *                              011=5clk, 100=6clk, 101=8clk,
 108  *                              110=12clk, 111=16clk
 109  *
 110  * Index-6 command/control port timings (shared by both drives) (byte)
 111  *      same layout as Index-5, default value = 0xde
 112  *
 113  * Suggested CDR programming for PIO mode0 (600ns):
 114  *      0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde  ; primary
 115  *      0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde  ; secondary
 116  *
 117  * Suggested CDR programming for PIO mode3 (180ns):
 118  *      0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde  ; primary
 119  *      0x0170,0x21,0xff,0x80,0x0376,0x09,0xde  ; secondary
 120  *
 121  * Suggested CDR programming for PIO mode4 (120ns):
 122  *      0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde  ; primary
 123  *      0x0170,0x21,0xff,0x80,0x0376,0x00,0xde  ; secondary
 124  *
 125  */
 126
 127 #include <linux/types.h>
 128 #include <linux/kernel.h>
 129 #include <linux/mm.h>
 130 #include <linux/ioport.h>
 131 #include <linux/interrupt.h>
 132 #include <linux/blkdev.h>
 133 #include <linux/init.h>
 134 #include <linux/hdreg.h>
 135 #include <linux/pci.h>
 136 #include <linux/delay.h>
 137 #include <linux/ide.h>
 138
 139 #include <asm/io.h>
 140
 141 static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
 142 {
 143         ide_hwif_t *hwif = HWIF(drive);
 144         unsigned int reg;
 145         unsigned long flags;
 146
 147         /* select PIO or DMA */
 148         reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);
 149
 150         __save_flags(flags);    /* local CPU only */
 151         __cli();                /* local CPU only */
 152
 153         if (reg != hwif->select_data) {
 154                 hwif->select_data = reg;
 155                 outb(0x51|(hwif->channel<<3), hwif->config_data+1);     /* set PIO/DMA */
 156                 outw(reg & 0xff, hwif->config_data);
 157         }
 158
 159         /* enable IRQ if not probing */
 160         if (drive->present) {
 161                 reg = inw(hwif->config_data+3) & 0x13;
 162                 reg &= ~(1 << hwif->channel);
 163                 outw(reg, hwif->config_data+3);
 164         }
 165
 166         __restore_flags(flags); /* local CPU only */
 167 }
 168
 169 static void trm290_selectproc (ide_drive_t *drive)
 170 {
 171         trm290_prepare_drive(drive, drive->using_dma);
 172 }
 173
 174 static int trm290_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
 175 {
 176         ide_hwif_t *hwif = HWIF(drive);
 177         unsigned int count, reading = 2, writing = 0;
 178
 179         switch (func) {
 180                 case ide_dma_write:
 181                         reading = 0;
 182                         writing = 1;
 183 #ifdef TRM290_NO_DMA_WRITES
 184                         break;  /* always use PIO for writes */
 185 #endif
 186                 case ide_dma_read:
 187                         if (!(count = ide_build_dmatable(drive, func)))
 188                                 break;          /* try PIO instead of DMA */
 189                         trm290_prepare_drive(drive, 1); /* select DMA xfer */
 190                         outl(virt_to_bus(hwif->dmatable)|reading|writing, hwif->dma_base);
 191                         drive->waiting_for_dma = 1;
 192                         outw((count * 2) - 1, hwif->dma_base+2); /* start DMA */
 193                         if (drive->media != ide_disk)
 194                                 return 0;
 195                         ide_set_handler(drive, &ide_dma_intr, WAIT_CMD);
 196                         OUT_BYTE(reading ? WIN_READDMA : WIN_WRITEDMA, IDE_COMMAND_REG);
 197                         return 0;
 198                 case ide_dma_begin:
 199                         return 0;
 200                 case ide_dma_end:
 201                         drive->waiting_for_dma = 0;
 202                         return (inw(hwif->dma_base+2) != 0x00ff);
 203                 case ide_dma_test_irq:
 204                         return (inw(hwif->dma_base+2) == 0x00ff);
 205                 default:
 206                         return ide_dmaproc(func, drive);
 207         }
 208         trm290_prepare_drive(drive, 0); /* select PIO xfer */
 209         return 1;
 210 }
 211
 212 /*
 213  * Invoked from ide-dma.c at boot time.
 214  */
 215 void __init ide_init_trm290 (ide_hwif_t *hwif)
 216 {
 217         unsigned int cfgbase = 0;
 218         unsigned long flags;
 219         byte reg;
 220         struct pci_dev *dev = hwif->pci_dev;
 221
 222         hwif->chipset = ide_trm290;
 223         cfgbase = dev->resource[4].start;
 224         if ((dev->class & 5) && cfgbase)
 225         {
 226                 hwif->config_data = cfgbase & PCI_BASE_ADDRESS_IO_MASK;
 227                 printk("TRM290: chip config base at 0x%04lx\n", hwif->config_data);
 228         } else {
 229                 hwif->config_data = 0x3df0;
 230                 printk("TRM290: using default config base at 0x%04lx\n", hwif->config_data);
 231         }
 232
 233         __save_flags(flags);    /* local CPU only */
 234         __cli();                /* local CPU only */
 235         /* put config reg into first byte of hwif->select_data */
 236         outb(0x51|(hwif->channel<<3), hwif->config_data+1);
 237         hwif->select_data = 0x21;                       /* select PIO as default */
 238         outb(hwif->select_data, hwif->config_data);
 239         reg = inb(hwif->config_data+3);                 /* get IRQ info */
 240         reg = (reg & 0x10) | 0x03;                      /* mask IRQs for both ports */
 241         outb(reg, hwif->config_data+3);
 242         __restore_flags(flags); /* local CPU only */
 243
 244         if ((reg & 0x10))
 245                 hwif->irq = hwif->channel ? 15 : 14;    /* legacy mode */
 246         else if (!hwif->irq && hwif->mate && hwif->mate->irq)
 247                 hwif->irq = hwif->mate->irq;            /* sharing IRQ with mate */
 248         ide_setup_dma(hwif, (hwif->config_data + 4) ^ (hwif->channel ? 0x0080 : 0x0000), 3);
 249         hwif->dmaproc = &trm290_dmaproc;
 250         hwif->selectproc = &trm290_selectproc;
 251         hwif->autodma = 0;                              /* play it safe for now */
 252 #if 1
 253         {
 254                 /*
 255                  * My trm290-based card doesn't seem to work with all possible values
 256                  * for the control basereg, so this kludge ensures that we use only
 257                  * values that are known to work.  Ugh.         -ml
 258                  */
 259                 unsigned short old, compat = hwif->channel ? 0x374 : 0x3f4;
 260                 static unsigned short next_offset = 0;
 261
 262                 outb(0x54|(hwif->channel<<3), hwif->config_data+1);
 263                 old = inw(hwif->config_data) & ~1;
 264                 if (old != compat && inb(old+2) == 0xff) {
 265                         compat += (next_offset += 0x400);       /* leave lower 10 bits untouched */
 266                         hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2;        /* FIXME: should do a check_region */
 267                         outw(compat|1, hwif->config_data);
 268                         printk("%s: control basereg workaround: old=0x%04x, new=0x%04x\n", hwif->name, old, inw(hwif->config_data) & ~1);
 269                 }
 270         }
 271 #endif
 272 }