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Import 2.3.15pre2
[davej-history.git] / drivers / block / ide-pci.c
blobcfca595920f7d4acdc91dc29ceb20448f7d68ece
1 /*
2 * linux/drivers/block/ide-pci.c Version 1.04 July 27, 1999
3 *
4 * Copyright (c) 1998-1999 Andre Hedrick
5 *
6 * Copyright (c) 1995-1998 Mark Lord
7 * May be copied or modified under the terms of the GNU General Public License
8 */
9
10 /*
11 * This module provides support for automatic detection and
12 * configuration of all PCI IDE interfaces present in a system.
13 */
14
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/timer.h>
19 #include <linux/mm.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/ide.h>
24
25 #include <asm/io.h>
26 #include <asm/irq.h>
27
28 #define DEVID_PIIXa ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0})
29 #define DEVID_PIIXb ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1})
30 #define DEVID_PIIX3 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1})
31 #define DEVID_PIIX4 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB})
32 #define DEVID_VIA_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561})
33 #define DEVID_VP_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1})
34 #define DEVID_PDC20246 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246})
35 #define DEVID_PDC20262 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262})
36 #define DEVID_RZ1000 ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1000})
37 #define DEVID_RZ1001 ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1001})
38 #define DEVID_SAMURAI ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE})
39 #define DEVID_CMD640 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_640})
40 #define DEVID_CMD643 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643})
41 #define DEVID_CMD646 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646})
42 #define DEVID_SIS5513 ((ide_pci_devid_t){PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513})
43 #define DEVID_OPTI621 ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C621})
44 #define DEVID_OPTI621V ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558})
45 #define DEVID_OPTI621X ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C825})
46 #define DEVID_TRM290 ((ide_pci_devid_t){PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290})
47 #define DEVID_NS87410 ((ide_pci_devid_t){PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87410})
48 #define DEVID_NS87415 ((ide_pci_devid_t){PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415})
49 #define DEVID_HT6565 ((ide_pci_devid_t){PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565})
50 #define DEVID_AEC6210 ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF})
51 #define DEVID_W82C105 ((ide_pci_devid_t){PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105})
52 #define DEVID_UM8886A ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A})
53 #define DEVID_UM8886BF ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF})
54 #define DEVID_HPT34X ((ide_pci_devid_t){PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343})
55 #define DEVID_HPT366 ((ide_pci_devid_t){PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366})
56 #define DEVID_ALI15X3 ((ide_pci_devid_t){PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229})
57 #define DEVID_CY82C693 ((ide_pci_devid_t){PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693})
58 #define DEVID_HINT ((ide_pci_devid_t){0x3388, 0x8013})
59 #define DEVID_CX5530 ((ide_pci_devid_t){PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE})
60
61 #define IDE_IGNORE ((void *)-1)
62
63 #ifdef CONFIG_BLK_DEV_TRM290
64 extern void ide_init_trm290(ide_hwif_t *);
65 #define INIT_TRM290 &ide_init_trm290
66 #else
67 #define INIT_TRM290 IDE_IGNORE
68 #endif
69
70 #ifdef CONFIG_BLK_DEV_OPTI621
71 extern void ide_init_opti621(ide_hwif_t *);
72 #define INIT_OPTI621 &ide_init_opti621
73 #else
74 #define INIT_OPTI621 NULL
75 #endif
76
77 #ifdef CONFIG_BLK_DEV_NS87415
78 extern void ide_init_ns87415(ide_hwif_t *);
79 #define INIT_NS87415 &ide_init_ns87415
80 #else
81 #define INIT_NS87415 IDE_IGNORE
82 #endif
83
84 #ifdef CONFIG_BLK_DEV_CMD646
85 extern void ide_init_cmd646(ide_hwif_t *);
86 #define INIT_CMD646 &ide_init_cmd646
87 #else
88 #ifdef __sparc_v9__
89 #define INIT_CMD646 IDE_IGNORE
90 #else
91 #define INIT_CMD646 NULL
92 #endif
93 #endif
94
95 #ifdef CONFIG_BLK_DEV_SL82C105
96 extern void ide_init_sl82c105(ide_hwif_t *);
97 #define INIT_W82C105 &ide_init_sl82c105
98 #else
99 #define INIT_W82C105 IDE_IGNORE
100 #endif
101
102 #ifdef CONFIG_BLK_DEV_RZ1000
103 extern void ide_init_rz1000(ide_hwif_t *);
104 #define INIT_RZ1000 &ide_init_rz1000
105 #else
106 #define INIT_RZ1000 IDE_IGNORE
107 #endif
108
109 #ifdef CONFIG_BLK_DEV_VIA82C586
110 extern unsigned int pci_init_via82c568(struct pci_dev *, const char *);
111 extern void ide_init_via82c586(ide_hwif_t *);
112 extern void ide_dmacapable_via82c586(ide_hwif_t *, unsigned long dmabase);
113 #define PCI_VIA82C586 &pci_init_via82c568
114 #define INIT_VIA82C586 &ide_init_via82c586
115 #define DMA_VIA82C586 &ide_dmacapable_via82c586
116 #else
117 #define PCI_VIA82C586 NULL
118 #define INIT_VIA82C586 NULL
119 #define DMA_VIA82C586 NULL
120 #endif
121
122 #ifdef CONFIG_BLK_DEV_ALI15X3
123 extern unsigned int pci_init_ali15x3(struct pci_dev *, const char *);
124 extern void ide_init_ali15x3(ide_hwif_t *);
125 #define PCI_ALI15X3 &pci_init_ali15x3
126 #define INIT_ALI15X3 &ide_init_ali15x3
127 #else
128 #define PCI_ALI15X3 NULL
129 #define INIT_ALI15X3 NULL
130 #endif
131
132 #ifdef CONFIG_BLK_DEV_CY82C693
133 extern void ide_init_cy82c693(ide_hwif_t *);
134 #define INIT_CY82C693 &ide_init_cy82c693
135 #else
136 #define INIT_CY82C693 NULL
137 #endif
138
139 #ifdef CONFIG_BLK_DEV_PDC202XX
140 extern unsigned int pci_init_pdc202xx(struct pci_dev *, const char *);
141 extern void ide_init_pdc202xx(ide_hwif_t *);
142 #define PCI_PDC202XX &pci_init_pdc202xx
143 #define INIT_PDC202XX &ide_init_pdc202xx
144 #else
145 #define PCI_PDC202XX NULL
146 #define INIT_PDC202XX NULL
147 #endif
148
149 #ifdef CONFIG_BLK_DEV_PIIX
150 extern void ide_init_piix(ide_hwif_t *);
151 #define INIT_PIIX &ide_init_piix
152 #else
153 #define INIT_PIIX NULL
154 #endif
155
156 #ifdef CONFIG_BLK_DEV_AEC6210
157 extern unsigned int pci_init_aec6210(struct pci_dev *, const char *);
158 #define PCI_AEC6210 &pci_init_aec6210
159 #else
160 #define PCI_AEC6210 NULL
161 #endif
162
163 #ifdef CONFIG_BLK_DEV_HPT34X
164 extern unsigned int pci_init_hpt34x(struct pci_dev *, const char *);
165 extern void ide_init_hpt34x(ide_hwif_t *);
166 #define PCI_HPT34X &pci_init_hpt34x
167 #define INIT_HPT34X &ide_init_hpt34x
168 #else
169 #define PCI_HPT34X NULL
170 #define INIT_HPT34X NULL
171 #endif
172
173 #ifdef CONFIG_BLK_DEV_HPT366
174 extern unsigned int pci_init_hpt366(struct pci_dev *, const char *);
175 extern void ide_init_hpt366(ide_hwif_t *);
176 #define PCI_HPT366 &pci_init_hpt366
177 #define INIT_HPT366 &ide_init_hpt366
178 #else
179 #define PCI_HPT366 NULL
180 #define INIT_HPT366 IDE_IGNORE
181 #endif
182
183 #ifdef CONFIG_BLK_DEV_SIS5513
184 extern unsigned int pci_init_sis5513(struct pci_dev *, const char *);
185 extern void ide_init_sis5513(ide_hwif_t *);
186 #define PCI_SIS5513 &pci_init_sis5513
187 #define INIT_SIS5513 &ide_init_sis5513
188 #else
189 #define PCI_SIS5513 NULL
190 #define INIT_SIS5513 NULL
191 #endif
192
193 #define INIT_SAMURAI NULL
194 #define INIT_CX5530 NULL
195
196 typedef struct ide_pci_enablebit_s {
197 byte reg; /* byte pci reg holding the enable-bit */
198 byte mask; /* mask to isolate the enable-bit */
199 byte val; /* value of masked reg when "enabled" */
200 } ide_pci_enablebit_t;
201
202 typedef struct ide_pci_device_s {
203 ide_pci_devid_t devid;
204 const char *name;
205 unsigned int (*init_chipset)(struct pci_dev *dev, const char *name);
206 void (*init_hwif)(ide_hwif_t *hwif);
207 void (*dma_init)(ide_hwif_t *hwif, unsigned long dmabase);
208 ide_pci_enablebit_t enablebits[2];
209 byte bootable;
210 byte sixtysix;
211 unsigned int extra;
212 } ide_pci_device_t;
213
214 static ide_pci_device_t ide_pci_chipsets[] __initdata = {
215 {DEVID_PIIXa, "PIIX", NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
216 {DEVID_PIIXb, "PIIX", NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
217 {DEVID_PIIX3, "PIIX3", NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
218 {DEVID_PIIX4, "PIIX4", NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0, 0 },
219 {DEVID_VIA_IDE, "VIA_IDE", NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
220 {DEVID_VP_IDE, "VP_IDE", PCI_VIA82C586, INIT_VIA82C586, DMA_VIA82C586, {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, ON_BOARD, 0, 0 },
221 {DEVID_PDC20246,"PDC20246", PCI_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 0, 16 },
222 {DEVID_PDC20262,"PDC20262", PCI_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 1, 48 },
223 {DEVID_RZ1000, "RZ1000", NULL, INIT_RZ1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
224 {DEVID_RZ1001, "RZ1001", NULL, INIT_RZ1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
225 {DEVID_SAMURAI, "SAMURAI", NULL, INIT_SAMURAI, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
226 {DEVID_CMD640, "CMD640", NULL, IDE_IGNORE, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
227 {DEVID_NS87410, "NS87410", NULL, NULL, NULL, {{0x43,0x08,0x08}, {0x47,0x08,0x08}}, ON_BOARD, 0, 0 },
228 {DEVID_SIS5513, "SIS5513", PCI_SIS5513, INIT_SIS5513, NULL, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, ON_BOARD, 1, 0 },
229 {DEVID_CMD643, "CMD643", NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
230 {DEVID_CMD646, "CMD646", NULL, INIT_CMD646, NULL, {{0x00,0x00,0x00}, {0x51,0x80,0x80}}, ON_BOARD, 0, 0 },
231 {DEVID_HT6565, "HT6565", NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
232 {DEVID_OPTI621, "OPTI621", NULL, INIT_OPTI621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0, 0 },
233 {DEVID_OPTI621X,"OPTI621X", NULL, INIT_OPTI621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0, 0 },
234 {DEVID_TRM290, "TRM290", NULL, INIT_TRM290, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
235 {DEVID_NS87415, "NS87415", NULL, INIT_NS87415, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
236 {DEVID_AEC6210, "AEC6210", PCI_AEC6210, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0, 0 },
237 {DEVID_W82C105, "W82C105", NULL, INIT_W82C105, NULL, {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, ON_BOARD, 0, 0 },
238 {DEVID_UM8886A, "UM8886A", NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
239 {DEVID_UM8886BF,"UM8886BF", NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
240 {DEVID_HPT34X, "HPT34X", PCI_HPT34X, INIT_HPT34X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, NEVER_BOARD, 0, 16 },
241 {DEVID_HPT366, "HPT366", PCI_HPT366, INIT_HPT366, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 1, 256 },
242 {DEVID_ALI15X3, "ALI15X3", PCI_ALI15X3, INIT_ALI15X3, NULL, {{0x09,0x20,0x20}, {0x09,0x10,0x10}}, ON_BOARD, 0, 0 },
243 {DEVID_CY82C693,"CY82C693", NULL, INIT_CY82C693, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
244 {DEVID_HINT, "HINT_IDE", NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
245 {DEVID_CX5530, "CX5530", NULL, INIT_CX5530, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
246 {IDE_PCI_DEVID_NULL, "PCI_IDE", NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 }};
247
248 static byte hpt363_shared_irq = 0;
249
250 /*
251 * This allows offboard ide-pci cards the enable a BIOS, verify interrupt
252 * settings of split-mirror pci-config space, place chipset into init-mode,
253 * and/or preserve an interrupt if the card is not native ide support.
254 */
255 static unsigned int __init ide_special_settings (struct pci_dev *dev, const char *name)
256 {
257 switch(dev->device) {
258 case PCI_DEVICE_ID_TTI_HPT343:
259 {
260 unsigned short pcicmd = 0;
261
262 pci_write_config_byte(dev, 0x80, 0x00);
263 pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
264 if (!(pcicmd & PCI_COMMAND_MEMORY)) {
265 /*
266 * FIXME - this is too ugly, and looks senseless.
267 * Why not just use resource[4]?
268 *
269 * This was a cleaner/quicker way to get the ioports
270 * that the are not decode do to a flaw in the chipset
271 * design.
272 */
273
274 int i;
275 unsigned long hpt34xIoBase = dev->resource[4].start;
276
277 dev->resource[0].start = (hpt34xIoBase + 0x20);
278 dev->resource[1].start = (hpt34xIoBase + 0x34);
279 dev->resource[2].start = (hpt34xIoBase + 0x28);
280 dev->resource[3].start = (hpt34xIoBase + 0x3c);
281 for(i=0; i<4; i++)
282 dev->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
283 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
284 } else {
285 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
286 }
287 }
288 case PCI_DEVICE_ID_TTI_HPT366:
289 case PCI_DEVICE_ID_PROMISE_20246:
290 case PCI_DEVICE_ID_PROMISE_20262:
291 case PCI_DEVICE_ID_ARTOP_ATP850UF:
292 return dev->irq;
293 default:
294 break;
295 }
296 return 0;
297 }
298
299 /*
300 * Match a PCI IDE port against an entry in ide_hwifs[],
301 * based on io_base port if possible.
302 */
303 static ide_hwif_t __init *ide_match_hwif (unsigned long io_base, byte bootable, const char *name)
304 {
305 int h;
306 ide_hwif_t *hwif;
307
308 /*
309 * Look for a hwif with matching io_base specified using
310 * parameters to ide_setup().
311 */
312 for (h = 0; h < MAX_HWIFS; ++h) {
313 hwif = &ide_hwifs[h];
314 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
315 if (hwif->chipset == ide_generic)
316 return hwif; /* a perfect match */
317 }
318 }
319 /*
320 * Look for a hwif with matching io_base default value.
321 * If chipset is "ide_unknown", then claim that hwif slot.
322 * Otherwise, some other chipset has already claimed it.. :(
323 */
324 for (h = 0; h < MAX_HWIFS; ++h) {
325 hwif = &ide_hwifs[h];
326 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
327 if (hwif->chipset == ide_unknown)
328 return hwif; /* match */
329 printk("%s: port 0x%04lx already claimed by %s\n", name, io_base, hwif->name);
330 return NULL; /* already claimed */
331 }
332 }
333 /*
334 * Okay, there is no hwif matching our io_base,
335 * so we'll just claim an unassigned slot.
336 * Give preference to claiming other slots before claiming ide0/ide1,
337 * just in case there's another interface yet-to-be-scanned
338 * which uses ports 1f0/170 (the ide0/ide1 defaults).
339 *
340 * Unless there is a bootable card that does not use the standard
341 * ports 1f0/170 (the ide0/ide1 defaults). The (bootable) flag.
342 */
343 if (bootable) {
344 for (h = 0; h < MAX_HWIFS; ++h) {
345 hwif = &ide_hwifs[h];
346 if (hwif->chipset == ide_unknown)
347 return hwif; /* pick an unused entry */
348 }
349 } else {
350 for (h = 2; h < MAX_HWIFS; ++h) {
351 hwif = ide_hwifs + h;
352 if (hwif->chipset == ide_unknown)
353 return hwif; /* pick an unused entry */
354 }
355 }
356 for (h = 0; h < 2; ++h) {
357 hwif = ide_hwifs + h;
358 if (hwif->chipset == ide_unknown)
359 return hwif; /* pick an unused entry */
360 }
361 printk("%s: too many IDE interfaces, no room in table\n", name);
362 return NULL;
363 }
364
365 static int __init ide_setup_pci_baseregs (struct pci_dev *dev, const char *name)
366 {
367 byte reg, progif = 0;
368
369 /*
370 * Place both IDE interfaces into PCI "native" mode:
371 */
372 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) {
373 if ((progif & 0xa) != 0xa) {
374 printk("%s: device not capable of full native PCI mode\n", name);
375 return 1;
376 }
377 printk("%s: placing both ports into native PCI mode\n", name);
378 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
379 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) {
380 printk("%s: rewrite of PROGIF failed, wanted 0x%04x, got 0x%04x\n", name, progif|5, progif);
381 return 1;
382 }
383 }
384 /*
385 * Setup base registers for IDE command/control spaces for each interface:
386 */
387 for (reg = 0; reg < 4; reg++) {
388 struct resource *res = dev->resource + reg;
389 if (!(res->flags & PCI_BASE_ADDRESS_SPACE_IO))
390 continue;
391 if (!res->start) {
392 printk("%s: Missing I/O address #%d\n", name, reg);
393 return 1;
394 }
395 }
396 return 0;
397 }
398
399 /*
400 * ide_setup_pci_device() looks at the primary/secondary interfaces
401 * on a PCI IDE device and, if they are enabled, prepares the IDE driver
402 * for use with them. This generic code works for most PCI chipsets.
403 *
404 * One thing that is not standardized is the location of the
405 * primary/secondary interface "enable/disable" bits. For chipsets that
406 * we "know" about, this information is in the ide_pci_device_t struct;
407 * for all other chipsets, we just assume both interfaces are enabled.
408 */
409 static void __init ide_setup_pci_device (struct pci_dev *dev, ide_pci_device_t *d)
410 {
411 unsigned int port, at_least_one_hwif_enabled = 0, autodma = 0, pciirq = 0;
412 unsigned short pcicmd = 0, tried_config = 0;
413 byte tmp = 0;
414 ide_hwif_t *hwif, *mate = NULL;
415
416 #ifdef CONFIG_IDEDMA_AUTO
417 autodma = 1;
418 #endif
419 check_if_enabled:
420 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) {
421 printk("%s: error accessing PCI regs\n", d->name);
422 return;
423 }
424 if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */
425 /*
426 * PnP BIOS was *supposed* to have set this device up for us,
427 * but we can do it ourselves, so long as the BIOS has assigned an IRQ
428 * (or possibly the device is using a "legacy header" for IRQs).
429 * Maybe the user deliberately *disabled* the device,
430 * but we'll eventually ignore it again if no drives respond.
431 */
432 if (tried_config++
433 || ide_setup_pci_baseregs(dev, d->name)
434 || pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) {
435 printk("%s: device disabled (BIOS)\n", d->name);
436 return;
437 }
438 autodma = 0; /* default DMA off if we had to configure it here */
439 goto check_if_enabled;
440 }
441 if (tried_config)
442 printk("%s: device enabled (Linux)\n", d->name);
443 /*
444 * Can we trust the reported IRQ?
445 */
446 pciirq = dev->irq;
447 if ((dev->class & ~(0xfa)) != ((PCI_CLASS_STORAGE_IDE << 8) | 5)) {
448 printk("%s: not 100%% native mode: will probe irqs later\n", d->name);
449 /*
450 * This allows offboard ide-pci cards the enable a BIOS,
451 * verify interrupt settings of split-mirror pci-config
452 * space, place chipset into init-mode, and/or preserve
453 * an interrupt if the card is not native ide support.
454 */
455 pciirq = (d->init_chipset) ? d->init_chipset(dev, d->name) : ide_special_settings(dev, d->name);
456 } else if (tried_config) {
457 printk("%s: will probe irqs later\n", d->name);
458 pciirq = 0;
459 } else if (!pciirq) {
460 printk("%s: bad irq (%d): will probe later\n", d->name, pciirq);
461 pciirq = 0;
462 } else {
463 #ifdef __sparc__
464 printk("%s: 100%% native mode on irq %s\n",
465 d->name, __irq_itoa(pciirq));
466 #else
467 printk("%s: 100%% native mode on irq %d\n", d->name, pciirq);
468 #endif
469 }
470 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X)) {
471 /*
472 * Since there are two cards that report almost identically,
473 * the only discernable difference is the values
474 * reported in pcicmd.
475 * Booting-BIOS card or HPT363 :: pcicmd == 0x07
476 * Non-bootable card or HPT343 :: pcicmd == 0x05
477 */
478 if (pcicmd & PCI_COMMAND_MEMORY) {
479 printk("%s: is IDE Express HPT363.\n", d->name);
480 d->bootable = OFF_BOARD;
481 }
482 }
483 /*
484 * Set up the IDE ports
485 */
486 for (port = 0; port <= 1; ++port) {
487 unsigned long base = 0, ctl = 0;
488 ide_pci_enablebit_t *e = &(d->enablebits[port]);
489 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || (tmp & e->mask) != e->val))
490 continue; /* port not enabled */
491 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) && (port))
492 return;
493 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE || (dev->class & (port ? 4 : 1)) != 0) {
494 /* FIXME! This really should check that it really gets the IO/MEM part right! */
495 ctl = dev->resource[(2*port)+1].start;
496 base = dev->resource[2*port].start;
497 }
498 if ((ctl && !base) || (base && !ctl)) {
499 printk("%s: inconsistent baseregs (BIOS) for port %d, skipping\n", d->name, port);
500 continue;
501 }
502 if (!ctl)
503 ctl = port ? 0x374 : 0x3f4; /* use default value */
504 if (!base)
505 base = port ? 0x170 : 0x1f0; /* use default value */
506 if ((hwif = ide_match_hwif(base, d->bootable, d->name)) == NULL)
507 continue; /* no room in ide_hwifs[] */
508 if (hwif->io_ports[IDE_DATA_OFFSET] != base) {
509 ide_init_hwif_ports(&hwif->hw, base, (ctl + 2), NULL);
510 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
511 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
512 }
513 hwif->chipset = ide_pci;
514 hwif->pci_dev = dev;
515 hwif->pci_devid = d->devid;
516 hwif->channel = port;
517 if (!hwif->irq)
518 hwif->irq = pciirq;
519 if (mate) {
520 hwif->mate = mate;
521 mate->mate = hwif;
522 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210)) {
523 hwif->serialized = 1;
524 mate->serialized = 1;
525 }
526 }
527 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) ||
528 IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886BF)) {
529 hwif->irq = hwif->channel ? 15 : 14;
530 goto bypass_umc_dma;
531 }
532 if ((!d->sixtysix) && (hwif->udma_four))
533 hwif->udma_four = 0;
534 #ifdef CONFIG_BLK_DEV_IDEDMA
535 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_SIS5513) ||
536 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X))
537 autodma = 0;
538 if (autodma)
539 hwif->autodma = 1;
540 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20246) ||
541 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20262) ||
542 IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210) ||
543 #ifdef CONFIG_BLK_DEV_HPT34X
544 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X) ||
545 #endif /* CONFIG_BLK_DEV_HPT34X */
546 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) ||
547 IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) ||
548 ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 0x80))) {
549 unsigned long dma_base = ide_get_or_set_dma_base(hwif, (!mate && d->extra) ? d->extra : 0, d->name);
550 if (dma_base && !(pcicmd & PCI_COMMAND_MASTER)) {
551 /*
552 * Set up BM-DMA capability (PnP BIOS should have done this)
553 */
554 hwif->autodma = 0; /* default DMA off if we had to configure it here */
555 (void) pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_MASTER);
556 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || !(pcicmd & PCI_COMMAND_MASTER)) {
557 printk("%s: %s error updating PCICMD\n", hwif->name, d->name);
558 dma_base = 0;
559 }
560 }
561 if (dma_base) {
562 if (d->dma_init) {
563 d->dma_init(hwif, dma_base);
564 } else {
565 ide_setup_dma(hwif, dma_base, 8);
566 }
567 } else {
568 printk("%s: %s Bus-Master DMA disabled (BIOS)\n", hwif->name, d->name);
569 }
570 }
571 #endif /* CONFIG_BLK_DEV_IDEDMA */
572 bypass_umc_dma:
573 if (d->init_hwif) /* Call chipset-specific routine for each enabled hwif */
574 d->init_hwif(hwif);
575 mate = hwif;
576 at_least_one_hwif_enabled = 1;
577 }
578 if (!at_least_one_hwif_enabled)
579 printk("%s: neither IDE port enabled (BIOS)\n", d->name);
580 }
581
582 __initfunc(static void hpt366_device_order_fixup (struct pci_dev *dev, ide_pci_device_t *d))
583 {
584 struct pci_dev *dev2;
585 ide_pci_device_t *d2;
586 unsigned char pin1 = 0, pin2 = 0;
587
588 d2 = d;
589 if (PCI_FUNC(dev->devfn) & 1)
590 return;
591
592 for (dev2=pci_devices; dev2; dev2=dev2->next) {
593 if ((dev2->vendor == dev->vendor) &&
594 (dev2->device == dev->device) &&
595 (PCI_FUNC(dev2->devfn) & 1))
596 break;
597 }
598 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
599 if (dev2) {
600 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
601 hpt363_shared_irq = (pin1 != pin2) ? 1 : 0;
602 }
603
604 if (hpt363_shared_irq) {
605 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
606 d->name, pin1, pin2);
607 }
608
609 printk("%s: IDE controller on PCI bus %02x dev %02x\n",
610 d->name, dev->bus->number, dev->devfn);
611 ide_setup_pci_device(dev, d);
612
613 if (dev2) {
614 printk("%s: IDE controller on PCI bus %02x dev %02x\n",
615 d2->name, dev2->bus->number, dev2->devfn);
616 ide_setup_pci_device(dev2, d2);
617 }
618 }
619
620 /*
621 * ide_scan_pcibus() gets invoked at boot time from ide.c.
622 * It finds all PCI IDE controllers and calls ide_setup_pci_device for them.
623 */
624 void __init ide_scan_pcibus (void)
625 {
626 struct pci_dev *dev;
627 ide_pci_devid_t devid;
628 ide_pci_device_t *d;
629
630 if (!pci_present())
631 return;
632 for(dev = pci_devices; dev; dev=dev->next) {
633 devid.vid = dev->vendor;
634 devid.did = dev->device;
635 for (d = ide_pci_chipsets; d->devid.vid && !IDE_PCI_DEVID_EQ(d->devid, devid); ++d);
636 if (d->init_hwif == IDE_IGNORE)
637 printk("%s: ignored by ide_scan_pci_device() (uses own driver)\n", d->name);
638 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_OPTI621V) && !(PCI_FUNC(dev->devfn) & 1))
639 continue; /* OPTI Viper-M uses same devid for functions 0 and 1 */
640 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) && (!(PCI_FUNC(dev->devfn) & 1) || !((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)))
641 continue; /* CY82C693 is more than only a IDE controller */
642 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) && !(PCI_FUNC(dev->devfn) & 1))
643 continue; /* UM8886A/BF pair */
644 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366))
645 hpt366_device_order_fixup(dev, d);
646 else if (!IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL) || (dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
647 if (IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL))
648 printk("%s: unknown IDE controller on PCI bus %02x device %02x, VID=%04x, DID=%04x\n",
649 d->name, dev->bus->number, dev->devfn, devid.vid, devid.did);
650 else
651 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d->name, dev->bus->number, dev->devfn);
652 ide_setup_pci_device(dev, d);
653 }
654 }
655 }
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