include/asm-alpha/pci.h

   1 #ifndef __ALPHA_PCI_H
   2 #define __ALPHA_PCI_H
   3
   4 #ifdef __KERNEL__
   5
   6 #include <linux/spinlock.h>
   7 #include <asm/scatterlist.h>
   8 #include <asm/machvec.h>
   9
  10 /*
  11  * The following structure is used to manage multiple PCI busses.
  12  */
  13
  14 struct pci_dev;
  15 struct pci_bus;
  16 struct resource;
  17 struct pci_iommu_arena;
  18
  19 /* A controler.  Used to manage multiple PCI busses.  */
  20
  21 struct pci_controler {
  22         struct pci_controler *next;
  23         struct pci_bus *bus;
  24         struct resource *io_space;
  25         struct resource *mem_space;
  26
  27         /* The following are for reporting to userland.  The invariant is
  28            that if we report a BWX-capable dense memory, we do not report
  29            a sparse memory at all, even if it exists.  */
  30         unsigned long sparse_mem_base;
  31         unsigned long dense_mem_base;
  32         unsigned long sparse_io_base;
  33         unsigned long dense_io_base;
  34
  35         /* This one's for the kernel only.  It's in KSEG somewhere.  */
  36         unsigned long config_space_base;
  37
  38         unsigned int index;
  39         unsigned int first_busno;
  40         unsigned int last_busno;
  41
  42         struct pci_iommu_arena *sg_pci;
  43         struct pci_iommu_arena *sg_isa;
  44 };
  45
  46 /* Override the logic in pci_scan_bus for skipping already-configured
  47    bus numbers.  */
  48
  49 #define pcibios_assign_all_busses()     1
  50
  51 #define PCIBIOS_MIN_IO          alpha_mv.min_io_address
  52 #define PCIBIOS_MIN_MEM         alpha_mv.min_mem_address
  53
  54 extern void pcibios_set_master(struct pci_dev *dev);
  55
  56 extern inline void pcibios_penalize_isa_irq(int irq)
  57 {
  58         /* We don't do dynamic PCI IRQ allocation */
  59 }
  60
  61 /* IOMMU controls.  */
  62
  63 /* Allocate and map kernel buffer using consistant mode DMA for PCI
  64    device.  Returns non-NULL cpu-view pointer to the buffer if
  65    successful and sets *DMA_ADDRP to the pci side dma address as well,
  66    else DMA_ADDRP is undefined.  */
  67
  68 extern void *pci_alloc_consistent(struct pci_dev *, long, dma_addr_t *);
  69
  70 /* Free and unmap a consistant DMA buffer.  CPU_ADDR and DMA_ADDR must
  71    be values that were returned from pci_alloc_consistant.  SIZE must
  72    be the same as what as passed into pci_alloc_consistant.
  73    References to the memory and mappings assosciated with CPU_ADDR or
  74    DMA_ADDR past this call are illegal.  */
  75
  76 extern void pci_free_consistent(struct pci_dev *, long, void *, dma_addr_t);
  77
  78 /* Map a single buffer of the indicate size for PCI DMA in streaming
  79    mode.  The 32-bit PCI bus mastering address to use is returned.
  80    Once the device is given the dma address, the device owns this memory
  81    until either pci_unmap_single or pci_dma_sync_single is performed.  */
  82
  83 extern dma_addr_t pci_map_single(struct pci_dev *, void *, long, int);
  84
  85 /* Unmap a single streaming mode DMA translation.  The DMA_ADDR and
  86    SIZE must match what was provided for in a previous pci_map_single
  87    call.  All other usages are undefined.  After this call, reads by
  88    the cpu to the buffer are guarenteed to see whatever the device
  89    wrote there.  */
  90
  91 extern void pci_unmap_single(struct pci_dev *, dma_addr_t, long, int);
  92
  93 /* Map a set of buffers described by scatterlist in streaming mode for
  94    PCI DMA.  This is the scather-gather version of the above
  95    pci_map_single interface.  Here the scatter gather list elements
  96    are each tagged with the appropriate PCI dma address and length.
  97    They are obtained via sg_dma_{address,length}(SG).
  98
  99    NOTE: An implementation may be able to use a smaller number of DMA
 100    address/length pairs than there are SG table elements.  (for
 101    example via virtual mapping capabilities) The routine returns the
 102    number of addr/length pairs actually used, at most nents.
 103
 104    Device ownership issues as mentioned above for pci_map_single are
 105    the same here.  */
 106
 107 extern int pci_map_sg(struct pci_dev *, struct scatterlist *, int, int);
 108
 109 /* Unmap a set of streaming mode DMA translations.  Again, cpu read
 110    rules concerning calls here are the same as for pci_unmap_single()
 111    above.  */
 112
 113 extern void pci_unmap_sg(struct pci_dev *, struct scatterlist *, int, int);
 114
 115 /* Make physical memory consistant for a single streaming mode DMA
 116    translation after a transfer.
 117
 118    If you perform a pci_map_single() but wish to interrogate the
 119    buffer using the cpu, yet do not wish to teardown the PCI dma
 120    mapping, you must call this function before doing so.  At the next
 121    point you give the PCI dma address back to the card, the device
 122    again owns the buffer.  */
 123
 124 extern inline void
 125 pci_dma_sync_single(struct pci_dev *dev, dma_addr_t dma_addr, long size,
 126                     int direction)
 127 {
 128         /* Nothing to do.  */
 129 }
 130
 131 /* Make physical memory consistant for a set of streaming mode DMA
 132    translations after a transfer.  The same as pci_dma_sync_single but
 133    for a scatter-gather list, same rules and usage.  */
 134
 135 extern inline void
 136 pci_dma_sync_sg(struct pci_dev *dev, struct scatterlist *sg, int nents,
 137                 int direction)
 138 {
 139         /* Nothing to do.  */
 140 }
 141
 142 /* Return whether the given PCI device DMA address mask can
 143    be supported properly.  For example, if your device can
 144    only drive the low 24-bits during PCI bus mastering, then
 145    you would pass 0x00ffffff as the mask to this function.  */
 146
 147 extern int pci_dma_supported(struct pci_dev *hwdev, dma_addr_t mask);
 148
 149 #endif /* __KERNEL__ */
 150
 151 /* Values for the `which' argument to sys_pciconfig_iobase.  */
 152 #define IOBASE_HOSE             0
 153 #define IOBASE_SPARSE_MEM       1
 154 #define IOBASE_DENSE_MEM        2
 155 #define IOBASE_SPARSE_IO        3
 156 #define IOBASE_DENSE_IO         4
 157 #define IOBASE_ROOT_BUS         5
 158 #define IOBASE_FROM_HOSE        0x10000
 159
 160 #endif /* __ALPHA_PCI_H */