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Import 2.4.0-test5pre3
[davej-history.git] / drivers / net / hamradio / soundmodem / sm_wss.c
blob19840c491bd7766124d5d56c1bdd0b551319eea6
1 /*****************************************************************************/
2
3 /*
4 * sm_wss.c -- soundcard radio modem driver, WSS (half duplex) driver
5 *
6 * Copyright (C) 1996 Thomas Sailer (sailer@ife.ee.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Please note that the GPL allows you to use the driver, NOT the radio.
23 * In order to use the radio, you need a license from the communications
24 * authority of your country.
25 *
26 */
27
28 #include <linux/ptrace.h>
29 #include <linux/sched.h>
30 #include <linux/interrupt.h>
31 #include <asm/io.h>
32 #include <asm/dma.h>
33 #include <linux/ioport.h>
34 #include <linux/soundmodem.h>
35 #include "sm.h"
36 #include "smdma.h"
37
38 /* --------------------------------------------------------------------- */
39
40 /*
41 * currently this module is supposed to support both module styles, i.e.
42 * the old one present up to about 2.1.9, and the new one functioning
43 * starting with 2.1.21. The reason is I have a kit allowing to compile
44 * this module also under 2.0.x which was requested by several people.
45 * This will go in 2.2
46 */
47 #include <linux/version.h>
48
49 #if LINUX_VERSION_CODE >= 0x20100
50 #include <asm/uaccess.h>
51 #else
52 #include <asm/segment.h>
53 #include <linux/mm.h>
54
55 #undef put_user
56 #undef get_user
57
58 #define put_user(x,ptr) ({ __put_user((unsigned long)(x),(ptr),sizeof(*(ptr))); 0; })
59 #define get_user(x,ptr) ({ x = ((__typeof__(*(ptr)))__get_user((ptr),sizeof(*(ptr)))); 0; })
60
61 extern inline int copy_from_user(void *to, const void *from, unsigned long n)
62 {
63 int i = verify_area(VERIFY_READ, from, n);
64 if (i)
65 return i;
66 memcpy_fromfs(to, from, n);
67 return 0;
68 }
69
70 extern inline int copy_to_user(void *to, const void *from, unsigned long n)
71 {
72 int i = verify_area(VERIFY_WRITE, to, n);
73 if (i)
74 return i;
75 memcpy_tofs(to, from, n);
76 return 0;
77 }
78 #endif
79
80 /* --------------------------------------------------------------------- */
81
82 struct sc_state_wss {
83 unsigned char revwss, revid, revv, revcid;
84 unsigned char fmt[2];
85 unsigned char crystal;
86 };
87
88 #define SCSTATE ((struct sc_state_wss *)(&sm->hw))
89
90 /* --------------------------------------------------------------------- */
91
92 #define WSS_CONFIG(iobase) (iobase+0)
93 #define WSS_STATUS(iobase) (iobase+3)
94 #define WSS_CODEC_IA(iobase) (iobase+4)
95 #define WSS_CODEC_ID(iobase) (iobase+5)
96 #define WSS_CODEC_STATUS(iobase) (iobase+6)
97 #define WSS_CODEC_DATA(iobase) (iobase+7)
98
99 #define WSS_EXTENT 8
100
101 #define CS423X_HOTFIX
102
103 /* --------------------------------------------------------------------- */
104
105 static void write_codec(struct net_device *dev, unsigned char idx,
106 unsigned char data)
107 {
108 int timeout = 900000;
109
110 /* wait until codec ready */
111 while (timeout > 0 && inb(WSS_CODEC_IA(dev->base_addr)) & 0x80)
112 timeout--;
113 outb(idx, WSS_CODEC_IA(dev->base_addr));
114 outb(data, WSS_CODEC_ID(dev->base_addr));
115 }
116
117
118 /* --------------------------------------------------------------------- */
119
120 static unsigned char read_codec(struct net_device *dev, unsigned char idx)
121 {
122 int timeout = 900000;
123
124 /* wait until codec ready */
125 while (timeout > 0 && inb(WSS_CODEC_IA(dev->base_addr)) & 0x80)
126 timeout--;
127 outb(idx & 0x1f, WSS_CODEC_IA(dev->base_addr));
128 return inb(WSS_CODEC_ID(dev->base_addr));
129 }
130
131 /* --------------------------------------------------------------------- */
132
133 extern void inline wss_ack_int(struct net_device *dev)
134 {
135 outb(0, WSS_CODEC_STATUS(dev->base_addr));
136 }
137
138 /* --------------------------------------------------------------------- */
139
140 static int wss_srate_tab[16] = {
141 8000, 5510, 16000, 11025, 27420, 18900, 32000, 22050,
142 -1, 37800, -1, 44100, 48000, 33075, 9600, 6620
143 };
144
145 static int wss_srate_index(int srate)
146 {
147 int i;
148
149 for (i = 0; i < (sizeof(wss_srate_tab)/sizeof(wss_srate_tab[0])); i++)
150 if (srate == wss_srate_tab[i] && wss_srate_tab[i] > 0)
151 return i;
152 return -1;
153 }
154
155 /* --------------------------------------------------------------------- */
156
157 static int wss_set_codec_fmt(struct net_device *dev, struct sm_state *sm, unsigned char fmt,
158 unsigned char fmt2, char fdx, char fullcalib)
159 {
160 unsigned long time;
161 unsigned long flags;
162
163 save_flags(flags);
164 cli();
165 /* Clock and data format register */
166 write_codec(dev, 0x48, fmt);
167 if (SCSTATE->crystal) {
168 write_codec(dev, 0x5c, fmt2 & 0xf0);
169 /* MCE and interface config reg */
170 write_codec(dev, 0x49, (fdx ? 0 : 0x4) | (fullcalib ? 0x18 : 0));
171 } else
172 /* MCE and interface config reg */
173 write_codec(dev, 0x49, fdx ? 0x8 : 0xc);
174 outb(0xb, WSS_CODEC_IA(dev->base_addr)); /* leave MCE */
175 if (SCSTATE->crystal && !fullcalib)
176 return 0;
177 /*
178 * wait for ACI start
179 */
180 time = 1000;
181 while (!(read_codec(dev, 0x0b) & 0x20))
182 if (!(--time)) {
183 printk(KERN_WARNING "%s: ad1848 auto calibration timed out (1)\n",
184 sm_drvname);
185 restore_flags(flags);
186 return -1;
187 }
188 /*
189 * wait for ACI end
190 */
191 sti();
192 time = jiffies + HZ/4;
193 while ((read_codec(dev, 0x0b) & 0x20) && ((signed)(jiffies - time) < 0));
194 restore_flags(flags);
195 if ((signed)(jiffies - time) >= 0) {
196 printk(KERN_WARNING "%s: ad1848 auto calibration timed out (2)\n",
197 sm_drvname);
198 return -1;
199 }
200 return 0;
201 }
202
203 /* --------------------------------------------------------------------- */
204
205 static int wss_init_codec(struct net_device *dev, struct sm_state *sm, char fdx,
206 unsigned char src_l, unsigned char src_r,
207 int igain_l, int igain_r,
208 int ogain_l, int ogain_r)
209 {
210 unsigned char tmp, reg0, reg1, reg6, reg7;
211 static const signed char irqtab[16] =
212 { -1, -1, 0x10, -1, -1, -1, -1, 0x08, -1, 0x10, 0x18, 0x20, -1, -1,
213 -1, -1 };
214 static const signed char dmatab[4] = { 1, 2, -1, 3 };
215
216 tmp = inb(WSS_STATUS(dev->base_addr));
217 if ((tmp & 0x3f) != 0x04 && (tmp & 0x3f) != 0x00 &&
218 (tmp & 0x3f) != 0x0f) {
219 printk(KERN_WARNING "sm: WSS card id register not found, "
220 "address 0x%lx, ID register 0x%02x\n",
221 dev->base_addr, (int)tmp);
222 /* return -1; */
223 SCSTATE->revwss = 0;
224 } else {
225 if ((tmp & 0x80) && ((dev->dma == 0) ||
226 ((dev->irq >= 8) && (dev->irq != 9)))) {
227 printk(KERN_ERR "%s: WSS: DMA0 and/or IRQ8..IRQ15 "
228 "(except IRQ9) cannot be used on an 8bit "
229 "card\n", sm_drvname);
230 return -1;
231 }
232 if (dev->irq > 15 || irqtab[dev->irq] == -1) {
233 printk(KERN_ERR "%s: WSS: invalid interrupt %d\n",
234 sm_drvname, (int)dev->irq);
235 return -1;
236 }
237 if (dev->dma > 3 || dmatab[dev->dma] == -1) {
238 printk(KERN_ERR "%s: WSS: invalid dma channel %d\n",
239 sm_drvname, (int)dev->dma);
240 return -1;
241 }
242 tmp = irqtab[dev->irq] | dmatab[dev->dma];
243 /* irq probe */
244 outb((tmp & 0x38) | 0x40, WSS_CONFIG(dev->base_addr));
245 if (!(inb(WSS_STATUS(dev->base_addr)) & 0x40)) {
246 outb(0, WSS_CONFIG(dev->base_addr));
247 printk(KERN_ERR "%s: WSS: IRQ%d is not free!\n",
248 sm_drvname, dev->irq);
249 }
250 outb(tmp, WSS_CONFIG(dev->base_addr));
251 SCSTATE->revwss = inb(WSS_STATUS(dev->base_addr)) & 0x3f;
252 }
253 /*
254 * initialize the codec
255 */
256 if (igain_l < 0)
257 igain_l = 0;
258 if (igain_r < 0)
259 igain_r = 0;
260 if (ogain_l > 0)
261 ogain_l = 0;
262 if (ogain_r > 0)
263 ogain_r = 0;
264 reg0 = (src_l << 6) & 0xc0;
265 reg1 = (src_r << 6) & 0xc0;
266 if (reg0 == 0x80 && igain_l >= 20) {
267 reg0 |= 0x20;
268 igain_l -= 20;
269 }
270 if (reg1 == 0x80 && igain_r >= 20) {
271 reg1 |= 0x20;
272 igain_r -= 20;
273 }
274 if (igain_l > 23)
275 igain_l = 23;
276 if (igain_r > 23)
277 igain_r = 23;
278 reg0 |= igain_l * 2 / 3;
279 reg1 |= igain_r * 2 / 3;
280 reg6 = (ogain_l < -95) ? 0x80 : (ogain_l * (-2) / 3);
281 reg7 = (ogain_r < -95) ? 0x80 : (ogain_r * (-2) / 3);
282 write_codec(dev, 9, 0);
283 write_codec(dev, 0, 0x45);
284 if (read_codec(dev, 0) != 0x45)
285 goto codec_err;
286 write_codec(dev, 0, 0xaa);
287 if (read_codec(dev, 0) != 0xaa)
288 goto codec_err;
289 write_codec(dev, 12, 0x40); /* enable MODE2 */
290 write_codec(dev, 16, 0);
291 write_codec(dev, 0, 0x45);
292 SCSTATE->crystal = (read_codec(dev, 16) != 0x45);
293 write_codec(dev, 0, 0xaa);
294 SCSTATE->crystal &= (read_codec(dev, 16) != 0xaa);
295 if (SCSTATE->crystal) {
296 SCSTATE->revcid = read_codec(dev, 0x19);
297 SCSTATE->revv = (SCSTATE->revcid >> 5) & 7;
298 SCSTATE->revcid &= 7;
299 write_codec(dev, 0x10, 0x80); /* maximum output level */
300 write_codec(dev, 0x11, 0x02); /* xtal enable and no HPF */
301 write_codec(dev, 0x12, 0x80); /* left line input control */
302 write_codec(dev, 0x13, 0x80); /* right line input control */
303 write_codec(dev, 0x16, 0); /* disable alternative freq sel */
304 write_codec(dev, 0x1a, 0xe0); /* mono IO disable */
305 write_codec(dev, 0x1b, 0x00); /* left out no att */
306 write_codec(dev, 0x1d, 0x00); /* right out no att */
307 }
308
309 if (wss_set_codec_fmt(dev, sm, SCSTATE->fmt[0], SCSTATE->fmt[0], fdx, 1))
310 goto codec_err;
311
312 write_codec(dev, 0, reg0); /* left input control */
313 write_codec(dev, 1, reg1); /* right input control */
314 write_codec(dev, 2, 0x80); /* left aux#1 input control */
315 write_codec(dev, 3, 0x80); /* right aux#1 input control */
316 write_codec(dev, 4, 0x80); /* left aux#2 input control */
317 write_codec(dev, 5, 0x80); /* right aux#2 input control */
318 write_codec(dev, 6, reg6); /* left dac control */
319 write_codec(dev, 7, reg7); /* right dac control */
320 write_codec(dev, 0xa, 0x2); /* pin control register */
321 write_codec(dev, 0xd, 0x0); /* digital mix control */
322 SCSTATE->revid = read_codec(dev, 0xc) & 0xf;
323 /*
324 * print revisions
325 */
326 if (SCSTATE->crystal)
327 printk(KERN_INFO "%s: Crystal CODEC ID %d, Chip revision %d, "
328 " Chip ID %d\n", sm_drvname, (int)SCSTATE->revid,
329 (int)SCSTATE->revv, (int)SCSTATE->revcid);
330 else
331 printk(KERN_INFO "%s: WSS revision %d, CODEC revision %d\n",
332 sm_drvname, (int)SCSTATE->revwss,
333 (int)SCSTATE->revid);
334 return 0;
335 codec_err:
336 outb(0, WSS_CONFIG(dev->base_addr));
337 printk(KERN_ERR "%s: no WSS soundcard found at address 0x%lx\n",
338 sm_drvname, dev->base_addr);
339 return -1;
340 }
341
342 /* --------------------------------------------------------------------- */
343
344 static void setup_dma_wss(struct net_device *dev, struct sm_state *sm, int send)
345 {
346 unsigned long flags;
347 static const unsigned char codecmode[2] = { 0x0e, 0x0d };
348 unsigned char oldcodecmode;
349 long abrt;
350 unsigned char fmt;
351 unsigned int numsamps;
352
353 send = !!send;
354 fmt = SCSTATE->fmt[send];
355 save_flags(flags);
356 cli();
357 /*
358 * perform the final DMA sequence to disable the codec request
359 */
360 oldcodecmode = read_codec(dev, 9);
361 write_codec(dev, 9, 0xc); /* disable codec */
362 wss_ack_int(dev);
363 if (read_codec(dev, 11) & 0x10) {
364 dma_setup(sm, oldcodecmode & 1, dev->dma);
365 abrt = 0;
366 while ((read_codec(dev, 11) & 0x10) || ((++abrt) >= 0x10000));
367 }
368 #ifdef CS423X_HOTFIX
369 if (read_codec(dev, 0x8) != fmt || SCSTATE->crystal)
370 wss_set_codec_fmt(dev, sm, fmt, fmt, 0, 0);
371 #else /* CS423X_HOTFIX */
372 if (read_codec(dev, 0x8) != fmt)
373 wss_set_codec_fmt(dev, sm, fmt, fmt, 0, 0);
374 #endif /* CS423X_HOTFIX */
375 numsamps = dma_setup(sm, send, dev->dma) - 1;
376 write_codec(dev, 15, numsamps & 0xff);
377 write_codec(dev, 14, numsamps >> 8);
378 write_codec(dev, 9, codecmode[send]);
379 restore_flags(flags);
380 }
381
382 /* --------------------------------------------------------------------- */
383
384 static void wss_interrupt(int irq, void *dev_id, struct pt_regs *regs)
385 {
386 struct net_device *dev = (struct net_device *)dev_id;
387 struct sm_state *sm = (struct sm_state *)dev->priv;
388 unsigned int curfrag;
389 unsigned int nums;
390
391 if (!dev || !sm || !sm->mode_rx || !sm->mode_tx ||
392 sm->hdrv.magic != HDLCDRV_MAGIC)
393 return;
394 cli();
395 wss_ack_int(dev);
396 disable_dma(dev->dma);
397 clear_dma_ff(dev->dma);
398 nums = dma_ptr(sm, sm->dma.ptt_cnt > 0, dev->dma, &curfrag) - 1;
399 write_codec(dev, 15, nums & 0xff);
400 write_codec(dev, 14, nums >> 8);
401 enable_dma(dev->dma);
402 sm_int_freq(sm);
403 sti();
404 if (sm->dma.ptt_cnt <= 0) {
405 dma_receive(sm, curfrag);
406 hdlcdrv_arbitrate(dev, &sm->hdrv);
407 if (hdlcdrv_ptt(&sm->hdrv)) {
408 /* starting to transmit */
409 disable_dma(dev->dma);
410 hdlcdrv_transmitter(dev, &sm->hdrv); /* prefill HDLC buffer */
411 dma_start_transmit(sm);
412 setup_dma_wss(dev, sm, 1);
413 dma_transmit(sm);
414 }
415 } else if (dma_end_transmit(sm, curfrag)) {
416 /* stopping transmission */
417 disable_dma(dev->dma);
418 dma_init_receive(sm);
419 setup_dma_wss(dev, sm, 0);
420 } else
421 dma_transmit(sm);
422 sm_output_status(sm);
423 hdlcdrv_transmitter(dev, &sm->hdrv);
424 hdlcdrv_receiver(dev, &sm->hdrv);
425 }
426
427 /* --------------------------------------------------------------------- */
428
429 static int wss_open(struct net_device *dev, struct sm_state *sm)
430 {
431 unsigned int dmasz, u;
432
433 if (sizeof(sm->m) < sizeof(struct sc_state_wss)) {
434 printk(KERN_ERR "sm wss: wss state too big: %d > %d\n",
435 sizeof(struct sc_state_wss), sizeof(sm->m));
436 return -ENODEV;
437 }
438 if (!dev || !sm || !sm->mode_rx || !sm->mode_tx)
439 return -ENXIO;
440 if (dev->base_addr <= 0 || dev->base_addr > 0x1000-WSS_EXTENT ||
441 dev->irq < 2 || dev->irq > 15 || dev->dma > 3)
442 return -ENXIO;
443 if (check_region(dev->base_addr, WSS_EXTENT))
444 return -EACCES;
445 /*
446 * check if a card is available
447 */
448 if (wss_init_codec(dev, sm, 0, 1, 1, 0, 0, -45, -45))
449 return -ENODEV;
450 /*
451 * initialize some variables
452 */
453 dma_init_receive(sm);
454 dmasz = (NUM_FRAGMENTS + 1) * sm->dma.ifragsz;
455 u = NUM_FRAGMENTS * sm->dma.ofragsz;
456 if (u > dmasz)
457 dmasz = u;
458 if (!(sm->dma.ibuf = sm->dma.obuf = kmalloc(dmasz, GFP_KERNEL | GFP_DMA)))
459 return -ENOMEM;
460 dma_init_transmit(sm);
461 dma_init_receive(sm);
462
463 memset(&sm->m, 0, sizeof(sm->m));
464 memset(&sm->d, 0, sizeof(sm->d));
465 if (sm->mode_tx->init)
466 sm->mode_tx->init(sm);
467 if (sm->mode_rx->init)
468 sm->mode_rx->init(sm);
469
470 if (request_dma(dev->dma, sm->hwdrv->hw_name)) {
471 kfree(sm->dma.obuf);
472 return -EBUSY;
473 }
474 if (request_irq(dev->irq, wss_interrupt, SA_INTERRUPT,
475 sm->hwdrv->hw_name, dev)) {
476 free_dma(dev->dma);
477 kfree(sm->dma.obuf);
478 return -EBUSY;
479 }
480 request_region(dev->base_addr, WSS_EXTENT, sm->hwdrv->hw_name);
481 setup_dma_wss(dev, sm, 0);
482 return 0;
483 }
484
485 /* --------------------------------------------------------------------- */
486
487 static int wss_close(struct net_device *dev, struct sm_state *sm)
488 {
489 if (!dev || !sm)
490 return -EINVAL;
491 /*
492 * disable interrupts
493 */
494 disable_dma(dev->dma);
495 write_codec(dev, 9, 0xc); /* disable codec */
496 free_irq(dev->irq, dev);
497 free_dma(dev->dma);
498 release_region(dev->base_addr, WSS_EXTENT);
499 kfree(sm->dma.obuf);
500 return 0;
501 }
502
503 /* --------------------------------------------------------------------- */
504
505 static int wss_sethw(struct net_device *dev, struct sm_state *sm, char *mode)
506 {
507 char *cp = strchr(mode, '.');
508 const struct modem_tx_info **mtp = sm_modem_tx_table;
509 const struct modem_rx_info **mrp;
510 int i, j;
511
512 if (!strcmp(mode, "off")) {
513 sm->mode_tx = NULL;
514 sm->mode_rx = NULL;
515 return 0;
516 }
517 if (cp)
518 *cp++ = '\0';
519 else
520 cp = mode;
521 for (; *mtp; mtp++) {
522 if ((*mtp)->loc_storage > sizeof(sm->m)) {
523 printk(KERN_ERR "%s: insufficient storage for modulator %s (%d)\n",
524 sm_drvname, (*mtp)->name, (*mtp)->loc_storage);
525 continue;
526 }
527 if (!(*mtp)->name || strcmp((*mtp)->name, mode))
528 continue;
529 if ((i = wss_srate_index((*mtp)->srate)) < 0)
530 continue;
531 for (mrp = sm_modem_rx_table; *mrp; mrp++) {
532 if ((*mrp)->loc_storage > sizeof(sm->d)) {
533 printk(KERN_ERR "%s: insufficient storage for demodulator %s (%d)\n",
534 sm_drvname, (*mrp)->name, (*mrp)->loc_storage);
535 continue;
536 }
537 if ((*mrp)->name && !strcmp((*mrp)->name, cp) &&
538 ((j = wss_srate_index((*mrp)->srate)) >= 0)) {
539 sm->mode_tx = *mtp;
540 sm->mode_rx = *mrp;
541 SCSTATE->fmt[0] = j;
542 SCSTATE->fmt[1] = i;
543 sm->dma.ifragsz = (sm->mode_rx->srate + 50)/100;
544 sm->dma.ofragsz = (sm->mode_tx->srate + 50)/100;
545 if (sm->dma.ifragsz < sm->mode_rx->overlap)
546 sm->dma.ifragsz = sm->mode_rx->overlap;
547 /* prefer same data format if possible to minimize switching times */
548 sm->dma.i16bit = sm->dma.o16bit = 2;
549 if (sm->mode_rx->srate == sm->mode_tx->srate) {
550 if (sm->mode_rx->demodulator_s16 && sm->mode_tx->modulator_s16)
551 sm->dma.i16bit = sm->dma.o16bit = 1;
552 else if (sm->mode_rx->demodulator_u8 && sm->mode_tx->modulator_u8)
553 sm->dma.i16bit = sm->dma.o16bit = 0;
554 }
555 if (sm->dma.i16bit == 2) {
556 if (sm->mode_rx->demodulator_s16)
557 sm->dma.i16bit = 1;
558 else if (sm->mode_rx->demodulator_u8)
559 sm->dma.i16bit = 0;
560 }
561 if (sm->dma.o16bit == 2) {
562 if (sm->mode_tx->modulator_s16)
563 sm->dma.o16bit = 1;
564 else if (sm->mode_tx->modulator_u8)
565 sm->dma.o16bit = 0;
566 }
567 if (sm->dma.i16bit == 2 || sm->dma.o16bit == 2) {
568 printk(KERN_INFO "%s: mode %s or %s unusable\n", sm_drvname,
569 sm->mode_rx->name, sm->mode_tx->name);
570 sm->mode_tx = NULL;
571 sm->mode_rx = NULL;
572 return -EINVAL;
573 }
574 #ifdef __BIG_ENDIAN
575 /* big endian 16bit only works on crystal cards... */
576 if (sm->dma.i16bit) {
577 SCSTATE->fmt[0] |= 0xc0;
578 sm->dma.ifragsz <<= 1;
579 }
580 if (sm->dma.o16bit) {
581 SCSTATE->fmt[1] |= 0xc0;
582 sm->dma.ofragsz <<= 1;
583 }
584 #else /* __BIG_ENDIAN */
585 if (sm->dma.i16bit) {
586 SCSTATE->fmt[0] |= 0x40;
587 sm->dma.ifragsz <<= 1;
588 }
589 if (sm->dma.o16bit) {
590 SCSTATE->fmt[1] |= 0x40;
591 sm->dma.ofragsz <<= 1;
592 }
593 #endif /* __BIG_ENDIAN */
594 return 0;
595 }
596 }
597 }
598 return -EINVAL;
599 }
600
601 /* --------------------------------------------------------------------- */
602
603 static int wss_ioctl(struct net_device *dev, struct sm_state *sm, struct ifreq *ifr,
604 struct hdlcdrv_ioctl *hi, int cmd)
605 {
606 struct sm_ioctl bi;
607 int i;
608
609 if (cmd != SIOCDEVPRIVATE)
610 return -ENOIOCTLCMD;
611
612 if (hi->cmd == HDLCDRVCTL_MODEMPARMASK)
613 return HDLCDRV_PARMASK_IOBASE | HDLCDRV_PARMASK_IRQ |
614 HDLCDRV_PARMASK_DMA | HDLCDRV_PARMASK_SERIOBASE |
615 HDLCDRV_PARMASK_PARIOBASE | HDLCDRV_PARMASK_MIDIIOBASE;
616
617 if (copy_from_user(&bi, ifr->ifr_data, sizeof(bi)))
618 return -EFAULT;
619
620 switch (bi.cmd) {
621 default:
622 return -ENOIOCTLCMD;
623
624 case SMCTL_GETMIXER:
625 i = 0;
626 bi.data.mix.sample_rate = sm->mode_rx->srate;
627 bi.data.mix.bit_rate = sm->hdrv.par.bitrate;
628 bi.data.mix.mixer_type = SCSTATE->crystal ?
629 SM_MIXER_CRYSTAL : SM_MIXER_AD1848;
630 if (((SCSTATE->crystal ? 0x2c0c20fflu: 0x20fflu)
631 >> bi.data.mix.reg) & 1) {
632 bi.data.mix.data = read_codec(dev, bi.data.mix.reg);
633 i = 1;
634 }
635 if (copy_to_user(ifr->ifr_data, &bi, sizeof(bi)))
636 return -EFAULT;
637 return i;
638
639 case SMCTL_SETMIXER:
640 if (!capable(CAP_SYS_RAWIO))
641 return -EACCES;
642 if ((bi.data.mix.mixer_type != SM_MIXER_CRYSTAL ||
643 !SCSTATE->crystal) &&
644 (bi.data.mix.mixer_type != SM_MIXER_AD1848 ||
645 bi.data.mix.reg >= 0x10))
646 return -EINVAL;
647 if (!((0x2c0c20fflu >> bi.data.mix.reg) & 1))
648 return -EACCES;
649 write_codec(dev, bi.data.mix.reg, bi.data.mix.data);
650 return 0;
651
652 }
653 if (copy_to_user(ifr->ifr_data, &bi, sizeof(bi)))
654 return -EFAULT;
655 return 0;
656
657 }
658
659 /* --------------------------------------------------------------------- */
660
661 const struct hardware_info sm_hw_wss = {
662 "wss", sizeof(struct sc_state_wss),
663 wss_open, wss_close, wss_ioctl, wss_sethw
664 };
665
666 /* --------------------------------------------------------------------- */
667
668 static void setup_fdx_dma_wss(struct net_device *dev, struct sm_state *sm)
669 {
670 unsigned long flags;
671 unsigned char oldcodecmode, codecdma;
672 long abrt;
673 unsigned int osamps, isamps;
674
675 save_flags(flags);
676 cli();
677 /*
678 * perform the final DMA sequence to disable the codec request
679 */
680 oldcodecmode = read_codec(dev, 9);
681 write_codec(dev, 9, 0); /* disable codec DMA */
682 wss_ack_int(dev);
683 if ((codecdma = read_codec(dev, 11)) & 0x10) {
684 dma_setup(sm, 1, dev->dma);
685 dma_setup(sm, 0, sm->hdrv.ptt_out.dma2);
686 abrt = 0;
687 while (((codecdma = read_codec(dev, 11)) & 0x10) || ((++abrt) >= 0x10000));
688 }
689 wss_set_codec_fmt(dev, sm, SCSTATE->fmt[1], SCSTATE->fmt[0], 1, 1);
690 osamps = dma_setup(sm, 1, dev->dma) - 1;
691 isamps = dma_setup(sm, 0, sm->hdrv.ptt_out.dma2) - 1;
692 write_codec(dev, 15, osamps & 0xff);
693 write_codec(dev, 14, osamps >> 8);
694 if (SCSTATE->crystal) {
695 write_codec(dev, 31, isamps & 0xff);
696 write_codec(dev, 30, isamps >> 8);
697 }
698 write_codec(dev, 9, 3);
699 restore_flags(flags);
700 }
701
702 /* --------------------------------------------------------------------- */
703
704 static void wssfdx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
705 {
706 struct net_device *dev = (struct net_device *)dev_id;
707 struct sm_state *sm = (struct sm_state *)dev->priv;
708 unsigned long flags;
709 unsigned char cry_int_src;
710 unsigned icfrag, ocfrag, isamps, osamps;
711
712 if (!dev || !sm || !sm->mode_rx || !sm->mode_tx ||
713 sm->hdrv.magic != HDLCDRV_MAGIC)
714 return;
715 save_flags(flags);
716 cli();
717 if (SCSTATE->crystal) {
718 /* Crystal has an essentially different interrupt handler! */
719 cry_int_src = read_codec(dev, 0x18);
720 wss_ack_int(dev);
721 if (cry_int_src & 0x10) { /* playback interrupt */
722 disable_dma(dev->dma);
723 clear_dma_ff(dev->dma);
724 osamps = dma_ptr(sm, 1, dev->dma, &ocfrag)-1;
725 write_codec(dev, 15, osamps & 0xff);
726 write_codec(dev, 14, osamps >> 8);
727 enable_dma(dev->dma);
728 }
729 if (cry_int_src & 0x20) { /* capture interrupt */
730 disable_dma(sm->hdrv.ptt_out.dma2);
731 clear_dma_ff(sm->hdrv.ptt_out.dma2);
732 isamps = dma_ptr(sm, 0, sm->hdrv.ptt_out.dma2, &icfrag)-1;
733 write_codec(dev, 31, isamps & 0xff);
734 write_codec(dev, 30, isamps >> 8);
735 enable_dma(sm->hdrv.ptt_out.dma2);
736 }
737 restore_flags(flags);
738 sm_int_freq(sm);
739 sti();
740 if (cry_int_src & 0x10) {
741 if (dma_end_transmit(sm, ocfrag))
742 dma_clear_transmit(sm);
743 dma_transmit(sm);
744 }
745 if (cry_int_src & 0x20) {
746 dma_receive(sm, icfrag);
747 hdlcdrv_arbitrate(dev, &sm->hdrv);
748 }
749 sm_output_status(sm);
750 hdlcdrv_transmitter(dev, &sm->hdrv);
751 hdlcdrv_receiver(dev, &sm->hdrv);
752 return;
753 }
754 wss_ack_int(dev);
755 disable_dma(dev->dma);
756 disable_dma(sm->hdrv.ptt_out.dma2);
757 clear_dma_ff(dev->dma);
758 clear_dma_ff(sm->hdrv.ptt_out.dma2);
759 osamps = dma_ptr(sm, 1, dev->dma, &ocfrag)-1;
760 isamps = dma_ptr(sm, 0, sm->hdrv.ptt_out.dma2, &icfrag)-1;
761 write_codec(dev, 15, osamps & 0xff);
762 write_codec(dev, 14, osamps >> 8);
763 if (SCSTATE->crystal) {
764 write_codec(dev, 31, isamps & 0xff);
765 write_codec(dev, 30, isamps >> 8);
766 }
767 enable_dma(dev->dma);
768 enable_dma(sm->hdrv.ptt_out.dma2);
769 restore_flags(flags);
770 sm_int_freq(sm);
771 sti();
772 if (dma_end_transmit(sm, ocfrag))
773 dma_clear_transmit(sm);
774 dma_transmit(sm);
775 dma_receive(sm, icfrag);
776 hdlcdrv_arbitrate(dev, &sm->hdrv);
777 sm_output_status(sm);
778 hdlcdrv_transmitter(dev, &sm->hdrv);
779 hdlcdrv_receiver(dev, &sm->hdrv);
780 }
781
782 /* --------------------------------------------------------------------- */
783
784 static int wssfdx_open(struct net_device *dev, struct sm_state *sm)
785 {
786 if (!dev || !sm || !sm->mode_rx || !sm->mode_tx)
787 return -ENXIO;
788 if (dev->base_addr <= 0 || dev->base_addr > 0x1000-WSS_EXTENT ||
789 dev->irq < 2 || dev->irq > 15 || dev->dma > 3)
790 return -ENXIO;
791 if (check_region(dev->base_addr, WSS_EXTENT))
792 return -EACCES;
793 /*
794 * check if a card is available
795 */
796 if (wss_init_codec(dev, sm, 1, 1, 1, 0, 0, -45, -45))
797 return -ENODEV;
798 /*
799 * initialize some variables
800 */
801 if (!(sm->dma.ibuf = kmalloc(sm->dma.ifragsz * (NUM_FRAGMENTS+1), GFP_KERNEL | GFP_DMA)))
802 return -ENOMEM;
803 if (!(sm->dma.obuf = kmalloc(sm->dma.ofragsz * NUM_FRAGMENTS, GFP_KERNEL | GFP_DMA))) {
804 kfree(sm->dma.ibuf);
805 return -ENOMEM;
806 }
807 dma_init_transmit(sm);
808 dma_init_receive(sm);
809
810 memset(&sm->m, 0, sizeof(sm->m));
811 memset(&sm->d, 0, sizeof(sm->d));
812 if (sm->mode_tx->init)
813 sm->mode_tx->init(sm);
814 if (sm->mode_rx->init)
815 sm->mode_rx->init(sm);
816
817 if (request_dma(dev->dma, sm->hwdrv->hw_name)) {
818 kfree(sm->dma.ibuf);
819 kfree(sm->dma.obuf);
820 return -EBUSY;
821 }
822 if (request_dma(sm->hdrv.ptt_out.dma2, sm->hwdrv->hw_name)) {
823 kfree(sm->dma.ibuf);
824 kfree(sm->dma.obuf);
825 free_dma(dev->dma);
826 return -EBUSY;
827 }
828 if (request_irq(dev->irq, wssfdx_interrupt, SA_INTERRUPT,
829 sm->hwdrv->hw_name, dev)) {
830 kfree(sm->dma.ibuf);
831 kfree(sm->dma.obuf);
832 free_dma(dev->dma);
833 free_dma(sm->hdrv.ptt_out.dma2);
834 return -EBUSY;
835 }
836 request_region(dev->base_addr, WSS_EXTENT, sm->hwdrv->hw_name);
837 setup_fdx_dma_wss(dev, sm);
838 return 0;
839 }
840
841 /* --------------------------------------------------------------------- */
842
843 static int wssfdx_close(struct net_device *dev, struct sm_state *sm)
844 {
845 if (!dev || !sm)
846 return -EINVAL;
847 /*
848 * disable interrupts
849 */
850 disable_dma(dev->dma);
851 disable_dma(sm->hdrv.ptt_out.dma2);
852 write_codec(dev, 9, 0xc); /* disable codec */
853 free_irq(dev->irq, dev);
854 free_dma(dev->dma);
855 free_dma(sm->hdrv.ptt_out.dma2);
856 release_region(dev->base_addr, WSS_EXTENT);
857 kfree(sm->dma.ibuf);
858 kfree(sm->dma.obuf);
859 return 0;
860 }
861
862 /* --------------------------------------------------------------------- */
863
864 static int wssfdx_sethw(struct net_device *dev, struct sm_state *sm, char *mode)
865 {
866 char *cp = strchr(mode, '.');
867 const struct modem_tx_info **mtp = sm_modem_tx_table;
868 const struct modem_rx_info **mrp;
869 int i;
870
871 if (!strcmp(mode, "off")) {
872 sm->mode_tx = NULL;
873 sm->mode_rx = NULL;
874 return 0;
875 }
876 if (cp)
877 *cp++ = '\0';
878 else
879 cp = mode;
880 for (; *mtp; mtp++) {
881 if ((*mtp)->loc_storage > sizeof(sm->m)) {
882 printk(KERN_ERR "%s: insufficient storage for modulator %s (%d)\n",
883 sm_drvname, (*mtp)->name, (*mtp)->loc_storage);
884 continue;
885 }
886 if (!(*mtp)->name || strcmp((*mtp)->name, mode))
887 continue;
888 if ((i = wss_srate_index((*mtp)->srate)) < 0)
889 continue;
890 for (mrp = sm_modem_rx_table; *mrp; mrp++) {
891 if ((*mrp)->loc_storage > sizeof(sm->d)) {
892 printk(KERN_ERR "%s: insufficient storage for demodulator %s (%d)\n",
893 sm_drvname, (*mrp)->name, (*mrp)->loc_storage);
894 continue;
895 }
896 if ((*mrp)->name && !strcmp((*mrp)->name, cp) &&
897 (*mtp)->srate == (*mrp)->srate) {
898 sm->mode_tx = *mtp;
899 sm->mode_rx = *mrp;
900 SCSTATE->fmt[0] = SCSTATE->fmt[1] = i;
901 sm->dma.ifragsz = sm->dma.ofragsz = (sm->mode_rx->srate + 50)/100;
902 if (sm->dma.ifragsz < sm->mode_rx->overlap)
903 sm->dma.ifragsz = sm->mode_rx->overlap;
904 sm->dma.i16bit = sm->dma.o16bit = 2;
905 if (sm->mode_rx->demodulator_s16) {
906 sm->dma.i16bit = 1;
907 sm->dma.ifragsz <<= 1;
908 #ifdef __BIG_ENDIAN /* big endian 16bit only works on crystal cards... */
909 SCSTATE->fmt[0] |= 0xc0;
910 #else /* __BIG_ENDIAN */
911 SCSTATE->fmt[0] |= 0x40;
912 #endif /* __BIG_ENDIAN */
913 } else if (sm->mode_rx->demodulator_u8)
914 sm->dma.i16bit = 0;
915 if (sm->mode_tx->modulator_s16) {
916 sm->dma.o16bit = 1;
917 sm->dma.ofragsz <<= 1;
918 #ifdef __BIG_ENDIAN /* big endian 16bit only works on crystal cards... */
919 SCSTATE->fmt[1] |= 0xc0;
920 #else /* __BIG_ENDIAN */
921 SCSTATE->fmt[1] |= 0x40;
922 #endif /* __BIG_ENDIAN */
923 } else if (sm->mode_tx->modulator_u8)
924 sm->dma.o16bit = 0;
925 if (sm->dma.i16bit == 2 || sm->dma.o16bit == 2) {
926 printk(KERN_INFO "%s: mode %s or %s unusable\n", sm_drvname,
927 sm->mode_rx->name, sm->mode_tx->name);
928 sm->mode_tx = NULL;
929 sm->mode_rx = NULL;
930 return -EINVAL;
931 }
932 return 0;
933 }
934 }
935 }
936 return -EINVAL;
937 }
938
939 /* --------------------------------------------------------------------- */
940
941 static int wssfdx_ioctl(struct net_device *dev, struct sm_state *sm, struct ifreq *ifr,
942 struct hdlcdrv_ioctl *hi, int cmd)
943 {
944 if (cmd != SIOCDEVPRIVATE)
945 return -ENOIOCTLCMD;
946
947 if (hi->cmd == HDLCDRVCTL_MODEMPARMASK)
948 return HDLCDRV_PARMASK_IOBASE | HDLCDRV_PARMASK_IRQ |
949 HDLCDRV_PARMASK_DMA | HDLCDRV_PARMASK_DMA2 |
950 HDLCDRV_PARMASK_SERIOBASE | HDLCDRV_PARMASK_PARIOBASE |
951 HDLCDRV_PARMASK_MIDIIOBASE;
952
953 return wss_ioctl(dev, sm, ifr, hi, cmd);
954 }
955
956 /* --------------------------------------------------------------------- */
957
958 const struct hardware_info sm_hw_wssfdx = {
959 "wssfdx", sizeof(struct sc_state_wss),
960 wssfdx_open, wssfdx_close, wssfdx_ioctl, wssfdx_sethw
961 };
962
963 /* --------------------------------------------------------------------- */
964
965 #undef SCSTATE
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