2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
23 #include <linux/irq.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/config.h>
29 #include <linux/smp_lock.h>
30 #include <linux/mc146818rtc.h>
36 static spinlock_t ioapic_lock
= SPIN_LOCK_UNLOCKED
;
39 * # of IO-APICs and # of IRQ routing registers
42 int nr_ioapic_registers
[MAX_IO_APICS
];
44 /* I/O APIC entries */
45 struct mpc_config_ioapic mp_ioapics
[MAX_IO_APICS
];
47 /* # of MP IRQ source entries */
48 struct mpc_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
50 /* MP IRQ source entries */
51 int mp_irq_entries
= 0;
54 # define TARGET_CPUS cpu_online_map
56 # define TARGET_CPUS 0x01
59 * Rough estimation of how many shared IRQs there are, can
62 #define MAX_PLUS_SHARED_IRQS NR_IRQS
63 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
66 * This is performance-critical, we want to do it O(1)
68 * the indexing order of this array favors 1:1 mappings
69 * between pins and IRQs.
72 static struct irq_pin_list
{
74 } irq_2_pin
[PIN_MAP_SIZE
];
77 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
78 * shared ISA-space IRQs, so we have to support them. We are super
79 * fast in the common case, and fast for shared ISA-space IRQs.
81 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
83 static int first_free_entry
= NR_IRQS
;
84 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
87 entry
= irq_2_pin
+ entry
->next
;
89 if (entry
->pin
!= -1) {
90 entry
->next
= first_free_entry
;
91 entry
= irq_2_pin
+ entry
->next
;
92 if (++first_free_entry
>= PIN_MAP_SIZE
)
93 panic("io_apic.c: whoops");
99 #define __DO_ACTION(R, ACTION, FINAL) \
103 struct irq_pin_list *entry = irq_2_pin + irq; \
110 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
112 io_apic_modify(entry->apic, reg); \
115 entry = irq_2_pin + entry->next; \
120 #define DO_ACTION(name,R,ACTION, FINAL) \
122 static void name##_IO_APIC_irq (unsigned int irq) \
123 __DO_ACTION(R, ACTION, FINAL)
125 DO_ACTION( __mask
, 0, |= 0x00010000, io_apic_sync(entry
->apic
))/* mask = 1 */
126 DO_ACTION( __unmask
, 0, &= 0xfffeffff, ) /* mask = 0 */
128 static void mask_IO_APIC_irq (unsigned int irq
)
132 spin_lock_irqsave(&ioapic_lock
, flags
);
133 __mask_IO_APIC_irq(irq
);
134 spin_unlock_irqrestore(&ioapic_lock
, flags
);
137 static void unmask_IO_APIC_irq (unsigned int irq
)
141 spin_lock_irqsave(&ioapic_lock
, flags
);
142 __unmask_IO_APIC_irq(irq
);
143 spin_unlock_irqrestore(&ioapic_lock
, flags
);
146 void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
148 struct IO_APIC_route_entry entry
;
151 * Disable it in the IO-APIC irq-routing table:
153 memset(&entry
, 0, sizeof(entry
));
155 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry
) + 0));
156 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry
) + 1));
159 static void clear_IO_APIC (void)
163 for (apic
= 0; apic
< nr_ioapics
; apic
++)
164 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
165 clear_IO_APIC_pin(apic
, pin
);
169 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
170 * specific CPU-side IRQs.
174 int pirq_entries
[MAX_PIRQS
];
175 int pirqs_enabled
= 0;
176 int skip_ioapic_setup
= 0;
178 static int __init
ioapic_setup(char *str
)
180 skip_ioapic_setup
= 1;
184 __setup("noapic", ioapic_setup
);
186 static int __init
ioapic_pirq_setup(char *str
)
189 int ints
[MAX_PIRQS
+1];
191 get_options(str
, ARRAY_SIZE(ints
), ints
);
193 for (i
= 0; i
< MAX_PIRQS
; i
++)
194 pirq_entries
[i
] = -1;
197 printk(KERN_INFO
"PIRQ redirection, working around broken MP-BIOS.\n");
199 if (ints
[0] < MAX_PIRQS
)
202 for (i
= 0; i
< max
; i
++) {
203 printk(KERN_DEBUG
"... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
205 * PIRQs are mapped upside down, usually.
207 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
212 __setup("pirq=", ioapic_pirq_setup
);
215 * Find the IRQ entry number of a certain pin.
217 static int __init
find_irq_entry(int apic
, int pin
, int type
)
221 for (i
= 0; i
< mp_irq_entries
; i
++)
222 if ( (mp_irqs
[i
].mpc_irqtype
== type
) &&
223 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
) &&
224 (mp_irqs
[i
].mpc_dstirq
== pin
))
232 * Find the pin to which IRQ[irq] (ISA) is connected
234 static int __init
find_isa_irq_pin(int irq
, int type
)
238 for (i
= 0; i
< mp_irq_entries
; i
++) {
239 int lbus
= mp_irqs
[i
].mpc_srcbus
;
241 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
242 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
243 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
) &&
244 (mp_irqs
[i
].mpc_irqtype
== type
) &&
245 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
247 return mp_irqs
[i
].mpc_dstirq
;
253 * Find a specific PCI IRQ entry.
254 * Not an __init, possibly needed by modules
256 static int __init
pin_2_irq(int idx
, int apic
, int pin
);
257 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pci_pin
)
259 int apic
, i
, best_guess
= -1;
261 for (i
= 0; i
< mp_irq_entries
; i
++) {
262 int lbus
= mp_irqs
[i
].mpc_srcbus
;
264 for (apic
= 0; apic
< nr_ioapics
; apic
++)
265 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
268 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
269 !mp_irqs
[i
].mpc_irqtype
&&
270 (bus
== mp_bus_id_to_pci_bus
[mp_irqs
[i
].mpc_srcbus
]) &&
271 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
272 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
274 if (!(apic
|| IO_APIC_IRQ(irq
)))
277 if (pci_pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
280 * Use the first all-but-pin matching entry as a
281 * best-guess fuzzy result for broken mptables.
291 * EISA Edge/Level control register, ELCR
293 static int __init
EISA_ELCR(unsigned int irq
)
296 unsigned int port
= 0x4d0 + (irq
>> 3);
297 return (inb(port
) >> (irq
& 7)) & 1;
299 printk(KERN_INFO
"Broken MPtable reports ISA irq %d\n", irq
);
303 /* EISA interrupts are always polarity zero and can be edge or level
304 * trigger depending on the ELCR value. If an interrupt is listed as
305 * EISA conforming in the MP table, that means its trigger type must
306 * be read in from the ELCR */
308 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
309 #define default_EISA_polarity(idx) (0)
311 /* ISA interrupts are always polarity zero edge triggered,
312 * when listed as conforming in the MP table. */
314 #define default_ISA_trigger(idx) (0)
315 #define default_ISA_polarity(idx) (0)
317 /* PCI interrupts are always polarity one level triggered,
318 * when listed as conforming in the MP table. */
320 #define default_PCI_trigger(idx) (1)
321 #define default_PCI_polarity(idx) (1)
323 /* MCA interrupts are always polarity zero level triggered,
324 * when listed as conforming in the MP table. */
326 #define default_MCA_trigger(idx) (1)
327 #define default_MCA_polarity(idx) (0)
329 static int __init
MPBIOS_polarity(int idx
)
331 int bus
= mp_irqs
[idx
].mpc_srcbus
;
335 * Determine IRQ line polarity (high active or low active):
337 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
339 case 0: /* conforms, ie. bus-type dependent polarity */
341 switch (mp_bus_id_to_type
[bus
])
343 case MP_BUS_ISA
: /* ISA pin */
345 polarity
= default_ISA_polarity(idx
);
348 case MP_BUS_EISA
: /* EISA pin */
350 polarity
= default_EISA_polarity(idx
);
353 case MP_BUS_PCI
: /* PCI pin */
355 polarity
= default_PCI_polarity(idx
);
358 case MP_BUS_MCA
: /* MCA pin */
360 polarity
= default_MCA_polarity(idx
);
365 printk(KERN_WARNING
"broken BIOS!!\n");
372 case 1: /* high active */
377 case 2: /* reserved */
379 printk(KERN_WARNING
"broken BIOS!!\n");
383 case 3: /* low active */
388 default: /* invalid */
390 printk(KERN_WARNING
"broken BIOS!!\n");
398 static int __init
MPBIOS_trigger(int idx
)
400 int bus
= mp_irqs
[idx
].mpc_srcbus
;
404 * Determine IRQ trigger mode (edge or level sensitive):
406 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
408 case 0: /* conforms, ie. bus-type dependent */
410 switch (mp_bus_id_to_type
[bus
])
412 case MP_BUS_ISA
: /* ISA pin */
414 trigger
= default_ISA_trigger(idx
);
417 case MP_BUS_EISA
: /* EISA pin */
419 trigger
= default_EISA_trigger(idx
);
422 case MP_BUS_PCI
: /* PCI pin */
424 trigger
= default_PCI_trigger(idx
);
427 case MP_BUS_MCA
: /* MCA pin */
429 trigger
= default_MCA_trigger(idx
);
434 printk(KERN_WARNING
"broken BIOS!!\n");
446 case 2: /* reserved */
448 printk(KERN_WARNING
"broken BIOS!!\n");
457 default: /* invalid */
459 printk(KERN_WARNING
"broken BIOS!!\n");
467 static inline int irq_polarity(int idx
)
469 return MPBIOS_polarity(idx
);
472 static inline int irq_trigger(int idx
)
474 return MPBIOS_trigger(idx
);
477 static int __init
pin_2_irq(int idx
, int apic
, int pin
)
480 int bus
= mp_irqs
[idx
].mpc_srcbus
;
483 * Debugging check, we are in big trouble if this message pops up!
485 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
486 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
488 switch (mp_bus_id_to_type
[bus
])
490 case MP_BUS_ISA
: /* ISA pin */
494 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
497 case MP_BUS_PCI
: /* PCI pin */
500 * PCI IRQs are mapped in order
504 irq
+= nr_ioapic_registers
[i
++];
510 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
517 * PCI IRQ command line redirection. Yes, limits are hardcoded.
519 if ((pin
>= 16) && (pin
<= 23)) {
520 if (pirq_entries
[pin
-16] != -1) {
521 if (!pirq_entries
[pin
-16]) {
522 printk(KERN_DEBUG
"disabling PIRQ%d\n", pin
-16);
524 irq
= pirq_entries
[pin
-16];
525 printk(KERN_DEBUG
"using PIRQ%d -> IRQ %d\n",
533 static inline int IO_APIC_irq_trigger(int irq
)
537 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
538 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
539 idx
= find_irq_entry(apic
,pin
,mp_INT
);
540 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
541 return irq_trigger(idx
);
545 * nonexistent IRQs are edge default
550 int irq_vector
[NR_IRQS
] = { FIRST_DEVICE_VECTOR
, 0 };
552 static int __init
assign_irq_vector(int irq
)
554 static int current_vector
= FIRST_DEVICE_VECTOR
, offset
= 0;
555 if (IO_APIC_VECTOR(irq
) > 0)
556 return IO_APIC_VECTOR(irq
);
559 if (current_vector
== SYSCALL_VECTOR
)
562 if (current_vector
> FIRST_SYSTEM_VECTOR
) {
564 current_vector
= FIRST_DEVICE_VECTOR
+ offset
;
567 if (current_vector
== FIRST_SYSTEM_VECTOR
)
568 panic("ran out of interrupt sources!");
570 IO_APIC_VECTOR(irq
) = current_vector
;
571 return current_vector
;
574 extern void (*interrupt
[NR_IRQS
])(void);
575 static struct hw_interrupt_type ioapic_level_irq_type
;
576 static struct hw_interrupt_type ioapic_edge_irq_type
;
578 void __init
setup_IO_APIC_irqs(void)
580 struct IO_APIC_route_entry entry
;
581 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
583 printk(KERN_DEBUG
"init IO_APIC IRQs\n");
585 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
586 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
589 * add it to the IO-APIC irq-routing table:
591 memset(&entry
,0,sizeof(entry
));
593 entry
.delivery_mode
= dest_LowestPrio
;
594 entry
.dest_mode
= 1; /* logical delivery */
595 entry
.mask
= 0; /* enable IRQ */
596 entry
.dest
.logical
.logical_dest
= TARGET_CPUS
;
598 idx
= find_irq_entry(apic
,pin
,mp_INT
);
601 printk(KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
604 printk(", %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
608 entry
.trigger
= irq_trigger(idx
);
609 entry
.polarity
= irq_polarity(idx
);
611 if (irq_trigger(idx
)) {
614 entry
.dest
.logical
.logical_dest
= TARGET_CPUS
;
617 irq
= pin_2_irq(idx
, apic
, pin
);
618 add_pin_to_irq(irq
, apic
, pin
);
620 if (!apic
&& !IO_APIC_IRQ(irq
))
623 if (IO_APIC_IRQ(irq
)) {
624 vector
= assign_irq_vector(irq
);
625 entry
.vector
= vector
;
627 if (IO_APIC_irq_trigger(irq
))
628 irq_desc
[irq
].handler
= &ioapic_level_irq_type
;
630 irq_desc
[irq
].handler
= &ioapic_edge_irq_type
;
632 set_intr_gate(vector
, interrupt
[irq
]);
634 if (!apic
&& (irq
< 16))
635 disable_8259A_irq(irq
);
637 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
638 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
643 printk(" not connected.\n");
647 * Set up the 8259A-master output pin as broadcast to all
650 void __init
setup_ExtINT_IRQ0_pin(unsigned int pin
, int vector
)
652 struct IO_APIC_route_entry entry
;
654 memset(&entry
,0,sizeof(entry
));
656 disable_8259A_irq(0);
659 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
662 * We use logical delivery to get the timer IRQ
665 entry
.dest_mode
= 1; /* logical delivery */
666 entry
.mask
= 0; /* unmask IRQ now */
667 entry
.dest
.logical
.logical_dest
= TARGET_CPUS
;
668 entry
.delivery_mode
= dest_LowestPrio
;
671 entry
.vector
= vector
;
674 * The timer IRQ doesnt have to know that behind the
675 * scene we have a 8259A-master in AEOI mode ...
677 irq_desc
[0].handler
= &ioapic_edge_irq_type
;
680 * Add it to the IO-APIC irq-routing table:
682 io_apic_write(0, 0x11+2*pin
, *(((int *)&entry
)+1));
683 io_apic_write(0, 0x10+2*pin
, *(((int *)&entry
)+0));
688 void __init
UNEXPECTED_IO_APIC(void)
690 printk(KERN_WARNING
" WARNING: unexpected IO-APIC, please mail\n");
691 printk(KERN_WARNING
" to linux-smp@vger.rutgers.edu\n");
694 void __init
print_IO_APIC(void)
697 struct IO_APIC_reg_00 reg_00
;
698 struct IO_APIC_reg_01 reg_01
;
699 struct IO_APIC_reg_02 reg_02
;
701 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
702 for (i
= 0; i
< nr_ioapics
; i
++)
703 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
704 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
707 * We are a bit conservative about what we expect. We have to
708 * know about every hardware change ASAP.
710 printk(KERN_INFO
"testing the IO APIC.......................\n");
712 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
714 *(int *)®_00
= io_apic_read(apic
, 0);
715 *(int *)®_01
= io_apic_read(apic
, 1);
716 if (reg_01
.version
>= 0x10)
717 *(int *)®_02
= io_apic_read(apic
, 2);
720 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
721 printk(KERN_DEBUG
".... register #00: %08X\n", *(int *)®_00
);
722 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.ID
);
723 if (reg_00
.__reserved_1
|| reg_00
.__reserved_2
)
724 UNEXPECTED_IO_APIC();
726 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
727 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.entries
);
728 if ( (reg_01
.entries
!= 0x0f) && /* older (Neptune) boards */
729 (reg_01
.entries
!= 0x17) && /* typical ISA+PCI boards */
730 (reg_01
.entries
!= 0x1b) && /* Compaq Proliant boards */
731 (reg_01
.entries
!= 0x1f) && /* dual Xeon boards */
732 (reg_01
.entries
!= 0x22) && /* bigger Xeon boards */
733 (reg_01
.entries
!= 0x2E) &&
734 (reg_01
.entries
!= 0x3F)
736 UNEXPECTED_IO_APIC();
738 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.version
);
739 if ( (reg_01
.version
!= 0x01) && /* 82489DX IO-APICs */
740 (reg_01
.version
!= 0x10) && /* oldest IO-APICs */
741 (reg_01
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
742 (reg_01
.version
!= 0x13) /* Xeon IO-APICs */
744 UNEXPECTED_IO_APIC();
745 if (reg_01
.__reserved_1
|| reg_01
.__reserved_2
)
746 UNEXPECTED_IO_APIC();
748 if (reg_01
.version
>= 0x10) {
749 printk(KERN_DEBUG
".... register #02: %08X\n", *(int *)®_02
);
750 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.arbitration
);
751 if (reg_02
.__reserved_1
|| reg_02
.__reserved_2
)
752 UNEXPECTED_IO_APIC();
755 printk(KERN_DEBUG
".... IRQ redirection table:\n");
757 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
758 " Stat Dest Deli Vect: \n");
760 for (i
= 0; i
<= reg_01
.entries
; i
++) {
761 struct IO_APIC_route_entry entry
;
763 *(((int *)&entry
)+0) = io_apic_read(apic
, 0x10+i
*2);
764 *(((int *)&entry
)+1) = io_apic_read(apic
, 0x11+i
*2);
766 printk(KERN_DEBUG
" %02x %03X %02X ",
768 entry
.dest
.logical
.logical_dest
,
769 entry
.dest
.physical
.physical_dest
772 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
777 entry
.delivery_status
,
784 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
785 for (i
= 0; i
< NR_IRQS
; i
++) {
786 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
789 printk(KERN_DEBUG
"IRQ%d ", i
);
791 printk("-> %d", entry
->pin
);
794 entry
= irq_2_pin
+ entry
->next
;
799 printk(KERN_INFO
".................................... done.\n");
804 static void print_APIC_bitfield (int base
)
809 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
810 for (i
= 0; i
< 8; i
++) {
811 v
= apic_read(base
+ i
*0x10);
812 for (j
= 0; j
< 32; j
++) {
822 void /*__init*/ print_local_APIC(void * dummy
)
824 unsigned int v
, ver
, maxlvt
;
826 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
827 smp_processor_id(), hard_smp_processor_id());
828 v
= apic_read(APIC_ID
);
829 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
830 v
= apic_read(APIC_LVR
);
831 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
832 ver
= GET_APIC_VERSION(v
);
833 maxlvt
= get_maxlvt();
835 v
= apic_read(APIC_TASKPRI
);
836 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
838 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
839 v
= apic_read(APIC_ARBPRI
);
840 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
841 v
& APIC_ARBPRI_MASK
);
842 v
= apic_read(APIC_PROCPRI
);
843 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
846 v
= apic_read(APIC_EOI
);
847 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
848 v
= apic_read(APIC_LDR
);
849 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
850 v
= apic_read(APIC_DFR
);
851 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
852 v
= apic_read(APIC_SPIV
);
853 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
855 printk(KERN_DEBUG
"... APIC ISR field:\n");
856 print_APIC_bitfield(APIC_ISR
);
857 printk(KERN_DEBUG
"... APIC TMR field:\n");
858 print_APIC_bitfield(APIC_TMR
);
859 printk(KERN_DEBUG
"... APIC IRR field:\n");
860 print_APIC_bitfield(APIC_IRR
);
862 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
863 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
864 apic_write(APIC_ESR
, 0);
865 v
= apic_read(APIC_ESR
);
866 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
869 v
= apic_read(APIC_ICR
);
870 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
871 v
= apic_read(APIC_ICR2
);
872 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
874 v
= apic_read(APIC_LVTT
);
875 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
877 if (maxlvt
> 3) { /* PC is LVT#4. */
878 v
= apic_read(APIC_LVTPC
);
879 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
881 v
= apic_read(APIC_LVT0
);
882 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
883 v
= apic_read(APIC_LVT1
);
884 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
886 if (maxlvt
> 2) { /* ERR is LVT#3. */
887 v
= apic_read(APIC_LVTERR
);
888 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
891 v
= apic_read(APIC_TMICT
);
892 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
893 v
= apic_read(APIC_TMCCT
);
894 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
895 v
= apic_read(APIC_TDCR
);
896 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
900 void print_all_local_APICs (void)
902 smp_call_function(print_local_APIC
, NULL
, 1, 1);
903 print_local_APIC(NULL
);
906 void /*__init*/ print_PIC(void)
908 extern spinlock_t i8259A_lock
;
909 unsigned int v
, flags
;
911 printk(KERN_DEBUG
"\nprinting PIC contents\n");
913 spin_lock_irqsave(&i8259A_lock
, flags
);
915 v
= inb(0xa1) << 8 | inb(0x21);
916 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
918 v
= inb(0xa0) << 8 | inb(0x20);
919 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
923 v
= inb(0xa0) << 8 | inb(0x20);
927 spin_unlock_irqrestore(&i8259A_lock
, flags
);
929 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
931 v
= inb(0x4d1) << 8 | inb(0x4d0);
932 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
935 static void __init
enable_IO_APIC(void)
937 struct IO_APIC_reg_01 reg_01
;
940 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
941 irq_2_pin
[i
].pin
= -1;
942 irq_2_pin
[i
].next
= 0;
945 for (i
= 0; i
< MAX_PIRQS
; i
++)
946 pirq_entries
[i
] = -1;
949 * The number of IO-APIC IRQ registers (== #pins):
951 for (i
= 0; i
< nr_ioapics
; i
++) {
952 *(int *)®_01
= io_apic_read(i
, 1);
953 nr_ioapic_registers
[i
] = reg_01
.entries
+1;
957 * Do not trust the IO-APIC being empty at bootup
963 * Not an __init, needed by the reboot code
965 void disable_IO_APIC(void)
968 * Clear the IO-APIC before rebooting:
972 disconnect_bsp_APIC();
976 * function to set the IO-APIC physical IDs based on the
977 * values stored in the MPC table.
979 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
982 static void __init
setup_ioapic_ids_from_mpc (void)
984 struct IO_APIC_reg_00 reg_00
;
988 * Set the IOAPIC ID to the value stored in the MPC table.
990 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
992 /* Read the register 0 value */
993 *(int *)®_00
= io_apic_read(apic
, 0);
995 if (mp_ioapics
[apic
].mpc_apicid
>= 0xf) {
996 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
997 apic
, mp_ioapics
[apic
].mpc_apicid
);
998 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1000 mp_ioapics
[apic
].mpc_apicid
= reg_00
.ID
;
1004 * Read the right value from the MPC table and
1005 * write it into the ID register.
1007 printk(KERN_INFO
"...changing IO-APIC physical APIC ID to %d ...",
1008 mp_ioapics
[apic
].mpc_apicid
);
1011 * Sanity check, is the ID really free? Every APIC in the
1012 * system must have a unique ID or we get lots of nice
1013 * 'stuck on smp_invalidate_needed IPI wait' messages.
1015 if (phys_cpu_present_map
& (1<<mp_ioapics
[apic
].mpc_apicid
))
1016 panic("APIC ID %d already used",
1017 mp_ioapics
[apic
].mpc_apicid
);
1019 reg_00
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1020 io_apic_write(apic
, 0, *(int *)®_00
);
1025 *(int *)®_00
= io_apic_read(apic
, 0);
1026 if (reg_00
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1027 panic("could not set ID!\n");
1034 * There is a nasty bug in some older SMP boards, their mptable lies
1035 * about the timer IRQ. We do the following to work around the situation:
1037 * - timer IRQ defaults to IO-APIC IRQ
1038 * - if this function detects that timer IRQs are defunct, then we fall
1039 * back to ISA timer IRQs
1041 static int __init
timer_irq_works(void)
1043 unsigned int t1
= jiffies
;
1046 /* Let ten ticks pass... */
1047 mdelay((10 * 1000) / HZ
);
1050 * Expect a few ticks at least, to be sure some possible
1051 * glue logic does not lock up after one or two first
1052 * ticks in a non-ExtINT mode. Also the local APIC
1053 * might have cached one ExtINT interrupt. Finally, at
1054 * least one tick may be lost due to delays.
1056 if (jiffies
- t1
> 4)
1062 static int __init
nmi_irq_works(void)
1064 irq_cpustat_t tmp
[NR_CPUS
];
1067 memcpy(tmp
, irq_stat
, sizeof(tmp
));
1071 for (j
= 0; j
< smp_num_cpus
; j
++) {
1072 cpu
= cpu_logical_map(j
);
1073 if (nmi_counter(cpu
) - tmp
[cpu
].__nmi_counter
<= 3) {
1074 printk(KERN_WARNING
"CPU#%d NMI appears to be stuck.\n", cpu
);
1082 * In the SMP+IOAPIC case it might happen that there are an unspecified
1083 * number of pending IRQ events unhandled. These cases are very rare,
1084 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1085 * better to do it this way as thus we do not have to be aware of
1086 * 'pending' interrupts in the IRQ path, except at this point.
1089 * Edge triggered needs to resend any interrupt
1090 * that was delayed but this is now handled in the device
1093 #define enable_edge_ioapic_irq unmask_IO_APIC_irq
1095 static void disable_edge_ioapic_irq (unsigned int irq
) { /* nothing */ }
1098 * Starting up a edge-triggered IO-APIC interrupt is
1099 * nasty - we need to make sure that we get the edge.
1100 * If it is already asserted for some reason, we need
1101 * return 1 to indicate that is was pending.
1103 * This is not complete - we should be able to fake
1104 * an edge even if it isn't on the 8259A...
1107 static unsigned int startup_edge_ioapic_irq(unsigned int irq
)
1109 int was_pending
= 0;
1110 unsigned long flags
;
1112 spin_lock_irqsave(&ioapic_lock
, flags
);
1114 disable_8259A_irq(irq
);
1115 if (i8259A_irq_pending(irq
))
1118 __unmask_IO_APIC_irq(irq
);
1119 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1124 #define shutdown_edge_ioapic_irq disable_edge_ioapic_irq
1127 * Once we have recorded IRQ_PENDING already, we can mask the
1128 * interrupt for real. This prevents IRQ storms from unhandled
1131 static void ack_edge_ioapic_irq(unsigned int irq
)
1133 if ((irq_desc
[irq
].status
& (IRQ_PENDING
| IRQ_DISABLED
))
1134 == (IRQ_PENDING
| IRQ_DISABLED
))
1135 mask_IO_APIC_irq(irq
);
1139 static void end_edge_ioapic_irq (unsigned int i
) { /* nothing */ }
1143 * Level triggered interrupts can just be masked,
1144 * and shutting down and starting up the interrupt
1145 * is the same as enabling and disabling them -- except
1146 * with a startup need to return a "was pending" value.
1148 * Level triggered interrupts are special because we
1149 * do not touch any IO-APIC register while handling
1150 * them. We ack the APIC in the end-IRQ handler, not
1151 * in the start-IRQ-handler. Protection against reentrance
1152 * from the same interrupt is still provided, both by the
1153 * generic IRQ layer and by the fact that an unacked local
1154 * APIC does not accept IRQs.
1156 static unsigned int startup_level_ioapic_irq (unsigned int irq
)
1158 unmask_IO_APIC_irq(irq
);
1160 return 0; /* don't check for pending */
1163 #define shutdown_level_ioapic_irq mask_IO_APIC_irq
1164 #define enable_level_ioapic_irq unmask_IO_APIC_irq
1165 #define disable_level_ioapic_irq mask_IO_APIC_irq
1167 static void end_level_ioapic_irq (unsigned int i
)
1172 static void mask_and_ack_level_ioapic_irq (unsigned int i
) { /* nothing */ }
1174 static void set_ioapic_affinity (unsigned int irq
, unsigned long mask
)
1176 unsigned long flags
;
1178 * Only the first 8 bits are valid.
1182 spin_lock_irqsave(&ioapic_lock
, flags
);
1183 __DO_ACTION(1, = mask
, )
1184 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1188 * Level and edge triggered IO-APIC interrupts need different handling,
1189 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1190 * handled with the level-triggered descriptor, but that one has slightly
1191 * more overhead. Level-triggered interrupts cannot be handled with the
1192 * edge-triggered handler, without risking IRQ storms and other ugly
1196 static struct hw_interrupt_type ioapic_edge_irq_type
= {
1198 startup_edge_ioapic_irq
,
1199 shutdown_edge_ioapic_irq
,
1200 enable_edge_ioapic_irq
,
1201 disable_edge_ioapic_irq
,
1202 ack_edge_ioapic_irq
,
1203 end_edge_ioapic_irq
,
1204 set_ioapic_affinity
,
1207 static struct hw_interrupt_type ioapic_level_irq_type
= {
1209 startup_level_ioapic_irq
,
1210 shutdown_level_ioapic_irq
,
1211 enable_level_ioapic_irq
,
1212 disable_level_ioapic_irq
,
1213 mask_and_ack_level_ioapic_irq
,
1214 end_level_ioapic_irq
,
1215 set_ioapic_affinity
,
1218 static inline void init_IO_APIC_traps(void)
1223 * NOTE! The local APIC isn't very good at handling
1224 * multiple interrupts at the same interrupt level.
1225 * As the interrupt level is determined by taking the
1226 * vector number and shifting that right by 4, we
1227 * want to spread these out a bit so that they don't
1228 * all fall in the same interrupt level.
1230 * Also, we've got to be careful not to trash gate
1231 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1233 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1234 if (IO_APIC_IRQ(irq
) && !IO_APIC_VECTOR(irq
)) {
1236 * Hmm.. We don't have an entry for this,
1237 * so default to an old-fashioned 8259
1238 * interrupt if we can..
1241 make_8259A_irq(irq
);
1243 /* Strange. Oh, well.. */
1244 irq_desc
[irq
].handler
= &no_irq_type
;
1249 static void enable_lapic_irq (unsigned int irq
)
1253 v
= apic_read(APIC_LVT0
);
1254 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
1257 static void disable_lapic_irq (unsigned int irq
)
1261 v
= apic_read(APIC_LVT0
);
1262 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1265 static void ack_lapic_irq (unsigned int irq
)
1270 static void end_lapic_irq (unsigned int i
) { /* nothing */ }
1272 static struct hw_interrupt_type lapic_irq_type
= {
1274 NULL
, /* startup_irq() not used for IRQ0 */
1275 NULL
, /* shutdown_irq() not used for IRQ0 */
1282 static void enable_NMI_through_LVT0 (void * dummy
)
1284 unsigned int v
, ver
;
1286 ver
= apic_read(APIC_LVR
);
1287 ver
= GET_APIC_VERSION(ver
);
1288 v
= APIC_DM_NMI
; /* unmask and set to NMI */
1289 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
1290 v
|= APIC_LVT_LEVEL_TRIGGER
;
1291 apic_write_around(APIC_LVT0
, v
);
1294 static void setup_nmi (void)
1297 * Dirty trick to enable the NMI watchdog ...
1298 * We put the 8259A master into AEOI mode and
1299 * unmask on all local APICs LVT0 as NMI.
1301 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1302 * is from Maciej W. Rozycki - so we do not have to EOI from
1303 * the NMI handler or the timer interrupt.
1305 printk(KERN_INFO
"activating NMI Watchdog ...");
1307 smp_call_function(enable_NMI_through_LVT0
, NULL
, 1, 1);
1308 enable_NMI_through_LVT0(NULL
);
1314 * This looks a bit hackish but it's about the only one way of sending
1315 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1316 * not support the ExtINT mode, unfortunately. We need to send these
1317 * cycles as some i82489DX-based boards have glue logic that keeps the
1318 * 8259A interrupt line asserted until INTA. --macro
1320 static inline void unlock_ExtINT_logic(void)
1323 struct IO_APIC_route_entry entry0
, entry1
;
1324 unsigned char save_control
, save_freq_select
;
1326 pin
= find_isa_irq_pin(8, mp_INT
);
1330 *(((int *)&entry0
) + 1) = io_apic_read(0, 0x11 + 2 * pin
);
1331 *(((int *)&entry0
) + 0) = io_apic_read(0, 0x10 + 2 * pin
);
1332 clear_IO_APIC_pin(0, pin
);
1334 memset(&entry1
, 0, sizeof(entry1
));
1336 entry1
.dest_mode
= 0; /* physical delivery */
1337 entry1
.mask
= 0; /* unmask IRQ now */
1338 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
1339 entry1
.delivery_mode
= dest_ExtINT
;
1340 entry1
.polarity
= entry0
.polarity
;
1344 io_apic_write(0, 0x11 + 2 * pin
, *(((int *)&entry1
) + 1));
1345 io_apic_write(0, 0x10 + 2 * pin
, *(((int *)&entry1
) + 0));
1347 save_control
= CMOS_READ(RTC_CONTROL
);
1348 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
1349 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
1351 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
1356 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
1360 CMOS_WRITE(save_control
, RTC_CONTROL
);
1361 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
1362 clear_IO_APIC_pin(0, pin
);
1364 io_apic_write(0, 0x11 + 2 * pin
, *(((int *)&entry0
) + 1));
1365 io_apic_write(0, 0x10 + 2 * pin
, *(((int *)&entry0
) + 0));
1369 * This code may look a bit paranoid, but it's supposed to cooperate with
1370 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1371 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1372 * fanatically on his truly buggy board.
1374 static inline void check_timer(void)
1376 extern int timer_ack
;
1381 * get/set the timer IRQ vector:
1383 disable_8259A_irq(0);
1384 vector
= assign_irq_vector(0);
1385 set_intr_gate(vector
, interrupt
[0]);
1388 * Subtle, code in do_timer_interrupt() expects an AEOI
1389 * mode for the 8259A whenever interrupts are routed
1390 * through I/O APICs. Also IRQ0 has to be enabled in
1391 * the 8259A which implies the virtual wire has to be
1392 * disabled in the local APIC.
1394 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1397 enable_8259A_irq(0);
1399 pin1
= find_isa_irq_pin(0, mp_INT
);
1400 pin2
= find_isa_irq_pin(0, mp_ExtINT
);
1402 printk(KERN_INFO
"..TIMER: vector=%d pin1=%d pin2=%d\n", vector
, pin1
, pin2
);
1406 * Ok, does IRQ0 through the IOAPIC work?
1408 unmask_IO_APIC_irq(0);
1409 if (timer_irq_works()) {
1411 disable_8259A_irq(0);
1413 enable_8259A_irq(0);
1418 clear_IO_APIC_pin(0, pin1
);
1419 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1422 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
1424 printk("\n..... (found pin %d) ...", pin2
);
1426 * legacy devices should be connected to IO APIC #0
1428 setup_ExtINT_IRQ0_pin(pin2
, vector
);
1429 if (timer_irq_works()) {
1438 * Cleanup, just in case ...
1440 clear_IO_APIC_pin(0, pin2
);
1442 printk(" failed.\n");
1445 printk(KERN_WARNING
"timer doesnt work through the IO-APIC - disabling NMI Watchdog!\n");
1449 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
1451 disable_8259A_irq(0);
1452 irq_desc
[0].handler
= &lapic_irq_type
;
1453 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
1454 enable_8259A_irq(0);
1456 if (timer_irq_works()) {
1457 printk(" works.\n");
1460 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
1461 printk(" failed.\n");
1463 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
1467 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
1469 unlock_ExtINT_logic();
1471 if (timer_irq_works()) {
1472 printk(" works.\n");
1475 printk(" failed :(.\n");
1476 panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
1481 * IRQ's that are handled by the old PIC in all cases:
1482 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1483 * Linux doesn't really care, as it's not actually used
1484 * for any interrupt handling anyway.
1485 * - IRQ13 is the FPU error IRQ, and may be connected
1486 * directly from the FPU to the old PIC. Linux doesn't
1487 * really care, because Linux doesn't want to use IRQ13
1488 * anyway (exception 16 is the proper FPU error signal)
1490 * Additionally, something is definitely wrong with irq9
1493 #define PIC_IRQS ((1<<2)|(1<<13))
1495 void __init
setup_IO_APIC(void)
1499 io_apic_irqs
= ~PIC_IRQS
;
1500 printk("ENABLING IO-APIC IRQs\n");
1503 * Set up the IO-APIC IRQ routing table by parsing the MP-BIOS
1506 setup_ioapic_ids_from_mpc();
1508 setup_IO_APIC_irqs();
1509 init_IO_APIC_traps();
1516 * This initializes the IO-APIC and APIC hardware if this is
1519 void IO_APIC_init_uniprocessor (void)
1521 if (!smp_found_config
)
1526 setup_APIC_clocks();