1 /* sis900.h Definitions for SiS ethernet controllers including 7014/7016 and 900
2 * Copyright 1999 Silicon Integrated System Corporation
4 * SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support,
5 * preliminary Rev. 1.0 Jan. 14, 1998
6 * SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support,
7 * preliminary Rev. 1.0 Nov. 10, 1998
8 * SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
9 * preliminary Rev. 1.0 Jan. 18, 1998
10 * http://www.sis.com.tw/support/databook.htm
14 * SiS 7016 and SiS 900 ethernet controller registers
17 /* The I/O extent, SiS 900 needs 256 bytes of io address */
18 #define SIS900_TOTAL_SIZE 0x100
20 /* Symbolic offsets to registers. */
21 enum sis900_registers
{
22 cr
=0x0, //Command Register
23 cfg
=0x4, //Configuration Register
24 mear
=0x8, //EEPROM Access Register
25 ptscr
=0xc, //PCI Test Control Register
26 isr
=0x10, //Interrupt Status Register
27 imr
=0x14, //Interrupt Mask Register
28 ier
=0x18, //Interrupt Enable Register
29 epar
=0x18, //Enhanced PHY Access Register
30 txdp
=0x20, //Transmit Descriptor Pointer Register
31 txcfg
=0x24, //Transmit Configuration Register
32 rxdp
=0x30, //Receive Descriptor Pointer Register
33 rxcfg
=0x34, //Receive Configuration Register
34 flctrl
=0x38, //Flow Control Register
35 rxlen
=0x3c, //Receive Packet Length Register
36 rfcr
=0x48, //Receive Filter Control Register
37 rfdr
=0x4C, //Receive Filter Data Register
38 pmctrl
=0xB0, //Power Management Control Register
39 pmer
=0xB4 //Power Management Wake-up Event Register
42 /* Symbolic names for bits in various registers */
43 enum sis900_command_register_bits
{
45 RESET
= 0x00000100, SWI
= 0x00000080, RxRESET
= 0x00000020,
46 TxRESET
= 0x00000010, RxDIS
= 0x00000008, RxENA
= 0x00000004,
47 TxDIS
= 0x00000002, TxENA
= 0x00000001
50 enum sis900_configuration_register_bits
{
51 DESCRFMT
= 0x00000100 /* 7016 specific */, REQALG
= 0x00000080,
52 SB
= 0x00000040, POW
= 0x00000020, EXD
= 0x00000010,
53 PESEL
= 0x00000008, LPM
= 0x00000004, BEM
= 0x00000001
56 enum sis900_eeprom_access_reigster_bits
{
57 MDC
= 0x00000040, MDDIR
= 0x00000020, MDIO
= 0x00000010, /* 7016 specific */
58 EECS
= 0x00000008, EECLK
= 0x00000004, EEDO
= 0x00000002,
62 enum sis900_interrupt_register_bits
{
63 WKEVT
= 0x10000000, TxPAUSEEND
= 0x08000000, TxPAUSE
= 0x04000000,
64 TxRCMP
= 0x02000000, RxRCMP
= 0x01000000, DPERR
= 0x00800000,
65 SSERR
= 0x00400000, RMABT
= 0x00200000, RTABT
= 0x00100000,
66 RxSOVR
= 0x00010000, HIBERR
= 0x00008000, SWINT
= 0x00001000,
67 MIBINT
= 0x00000800, TxURN
= 0x00000400, TxIDLE
= 0x00000200,
68 TxERR
= 0x00000100, TxDESC
= 0x00000080, TxOK
= 0x00000040,
69 RxORN
= 0x00000020, RxIDLE
= 0x00000010, RxEARLY
= 0x00000008,
70 RxERR
= 0x00000004, RxDESC
= 0x00000002, RxOK
= 0x00000001
73 enum sis900_interrupt_enable_reigster_bits
{
77 /* maximum dma burst fro transmission and receive*/
78 #define MAX_DMA_RANGE 7 /* actually 0 means MAXIMUM !! */
79 #define TxMXDMA_shift 20
80 #define RxMXDMA_shift 20
81 #define TX_DMA_BURST 0
82 #define RX_DMA_BURST 0
84 /* transmit FIFO threshholds */
85 #define TX_FILL_THRESH 16 /* 1/4 FIFO size */
86 #define TxFILLT_shift 8
87 #define TxDRNT_shift 0
88 #define TxDRNT_100 48 /* 3/4 FIFO size */
89 #define TxDRNT_10 16 /* 1/2 FIFO size */
91 enum sis900_transmit_config_register_bits
{
92 TxCSI
= 0x80000000, TxHBI
= 0x40000000, TxMLB
= 0x20000000,
93 TxATP
= 0x10000000, TxIFG
= 0x0C000000, TxFILLT
= 0x00003F00,
97 /* recevie FIFO thresholds */
98 #define RxDRNT_shift 1
99 #define RxDRNT_100 16 /* 1/2 FIFO size */
100 #define RxDRNT_10 24 /* 3/4 FIFO size */
102 enum sis900_reveive_config_register_bits
{
103 RxAEP
= 0x80000000, RxARP
= 0x40000000, RxATX
= 0x10000000,
104 RxAJAB
= 0x08000000, RxDRNT
= 0x0000007F
107 #define RFAA_shift 28
108 #define RFADDR_shift 16
110 enum sis900_receive_filter_control_register_bits
{
111 RFEN
= 0x80000000, RFAAB
= 0x40000000, RFAAM
= 0x20000000,
112 RFAAP
= 0x10000000, RFPromiscuous
= (RFAAB
|RFAAM
|RFAAP
)
115 enum sis900_reveive_filter_data_mask
{
119 /* EEPROM Addresses */
120 enum sis900_eeprom_address
{
121 EEPROMSignature
= 0x00, EEPROMVendorID
= 0x02, EEPROMDeviceID
= 0x03,
122 EEPROMMACAddr
= 0x08, EEPROMChecksum
= 0x0b
125 /* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */
126 enum sis900_eeprom_command
{
127 EEread
= 0x0180, EEwrite
= 0x0140, EEerase
= 0x01C0,
128 EEwriteEnable
= 0x0130, EEwriteDisable
= 0x0100,
129 EEeraseAll
= 0x0120, EEwriteAll
= 0x0110,
130 EEaddrMask
= 0x013F, EEcmdShift
= 16
133 /* Manamgement Data I/O (mdio) frame */
134 #define MIIread 0x6000
135 #define MIIwrite 0x5002
136 #define MIIpmdShift 7
137 #define MIIregShift 2
139 #define MIIcmdShift 16
141 /* Buffer Descriptor Status*/
142 enum sis900_buffer_status
{
143 OWN
= 0x80000000, MORE
= 0x40000000, INTR
= 0x20000000,
144 SUPCRC
= 0x10000000, INCCRC
= 0x10000000,
145 OK
= 0x08000000, DSIZE
= 0x00000FFF
147 /* Status for TX Buffers */
148 enum sis900_tx_buffer_status
{
149 ABORT
= 0x04000000, UNDERRUN
= 0x02000000, NOCARRIER
= 0x01000000,
150 DEFERD
= 0x00800000, EXCDEFER
= 0x00400000, OWCOLL
= 0x00200000,
151 EXCCOLL
= 0x00100000, COLCNT
= 0x000F0000
154 enum sis900_rx_bufer_status
{
155 OVERRUN
= 0x02000000, DEST
= 0x00800000, BCAST
= 0x01800000,
156 MCAST
= 0x01000000, UNIMATCH
= 0x00800000, TOOLONG
= 0x00400000,
157 RUNT
= 0x00200000, RXISERR
= 0x00100000, CRCERR
= 0x00080000,
158 FAERR
= 0x00040000, LOOPBK
= 0x00020000, RXCOL
= 0x00010000
161 /* MII register offsets */
163 MII_CONTROL
= 0x0000, MII_STATUS
= 0x0001, MII_PHY_ID0
= 0x0002,
164 MII_PHY_ID1
= 0x0003, MII_ANADV
= 0x0004, MII_ANLPAR
= 0x0005,
168 /* mii registers specific to SiS 900 */
169 enum sis_mii_registers
{
170 MII_CONFIG1
= 0x0010, MII_CONFIG2
= 0x0011, MII_STSOUT
= 0x0012,
171 MII_MASK
= 0x0013, MII_RESV
= 0x0014
174 /* mii registers specific to ICS 1893 */
175 enum ics_mii_registers
{
176 MII_EXTCTRL
= 0x0010, MII_QPDSTS
= 0x0011, MII_10BTOP
= 0x0012,
177 MII_EXTCTRL2
= 0x0013
180 /* mii registers specific to AMD 79C901 */
181 enum amd_mii_registers
{
182 MII_STATUS_SUMMARY
= 0x0018
185 /* MII Control register bit definitions. */
186 enum mii_control_register_bits
{
187 MII_CNTL_FDX
= 0x0100, MII_CNTL_RST_AUTO
= 0x0200,
188 MII_CNTL_ISOLATE
= 0x0400, MII_CNTL_PWRDWN
= 0x0800,
189 MII_CNTL_AUTO
= 0x1000, MII_CNTL_SPEED
= 0x2000,
190 MII_CNTL_LPBK
= 0x4000, MII_CNTL_RESET
= 0x8000
193 /* MII Status register bit */
194 enum mii_status_register_bits
{
195 MII_STAT_EXT
= 0x0001, MII_STAT_JAB
= 0x0002,
196 MII_STAT_LINK
= 0x0004, MII_STAT_CAN_AUTO
= 0x0008,
197 MII_STAT_FAULT
= 0x0010, MII_STAT_AUTO_DONE
= 0x0020,
198 MII_STAT_CAN_T
= 0x0800, MII_STAT_CAN_T_FDX
= 0x1000,
199 MII_STAT_CAN_TX
= 0x2000, MII_STAT_CAN_TX_FDX
= 0x4000,
200 MII_STAT_CAN_T4
= 0x8000
203 #define MII_ID1_OUI_LO 0xFC00 /* low bits of OUI mask */
204 #define MII_ID1_MODEL 0x03F0 /* model number */
205 #define MII_ID1_REV 0x000F /* model number */
207 /* MII NWAY Register Bits ...
208 valid for the ANAR (Auto-Negotiation Advertisement) and
209 ANLPAR (Auto-Negotiation Link Partner) registers */
210 enum mii_nway_register_bits
{
211 MII_NWAY_NODE_SEL
= 0x001f, MII_NWAY_CSMA_CD
= 0x0001,
212 MII_NWAY_T
= 0x0020, MII_NWAY_T_FDX
= 0x0040,
213 MII_NWAY_TX
= 0x0080, MII_NWAY_TX_FDX
= 0x0100,
214 MII_NWAY_T4
= 0x0200, MII_NWAY_PAUSE
= 0x0400,
215 MII_NWAY_RF
= 0x2000, MII_NWAY_ACK
= 0x4000,
219 enum mii_stsout_register_bits
{
220 MII_STSOUT_LINK_FAIL
= 0x4000,
221 MII_STSOUT_SPD
= 0x0080, MII_STSOUT_DPLX
= 0x0040
224 enum mii_stsics_register_bits
{
225 MII_STSICS_SPD
= 0x8000, MII_STSICS_DPLX
= 0x4000,
226 MII_STSICS_LINKSTS
= 0x0001
229 enum mii_stssum_register_bits
{
230 MII_STSSUM_LINK
= 0x0008, MII_STSSUM_DPLX
= 0x0004,
231 MII_STSSUM_AUTO
= 0x0002, MII_STSSUM_SPD
= 0x0001
234 enum sis630_revision_id
{
235 SIS630E_REV
= 0x81, SIS630EA1_REV
= 0x83,
239 #define FDX_CAPABLE_DUPLEX_UNKNOWN 0
240 #define FDX_CAPABLE_HALF_SELECTED 1
241 #define FDX_CAPABLE_FULL_SELECTED 2
243 #define HW_SPEED_UNCONFIG 0
244 #define HW_SPEED_HOME 1
245 #define HW_SPEED_10_MBPS 10
246 #define HW_SPEED_100_MBPS 100
247 #define HW_SPEED_DEFAULT (HW_SPEED_100_MBPS)
250 #define MAC_HEADER_SIZE 14
252 #define TX_BUF_SIZE 1536
253 #define RX_BUF_SIZE 1536
255 #define NUM_TX_DESC 16 /* Number of Tx descriptor registers. */
256 #define NUM_RX_DESC 16 /* Number of Rx descriptor registers. */
258 /* PCI stuff, should be move to pic.h */
259 #define PCI_DEVICE_ID_SI_900 0x900
260 #define PCI_DEVICE_ID_SI_7016 0x7016
262 /* ioctl for accessing MII transceiver */
263 #define SIOCGMIIPHY (SIOCDEVPRIVATE) /* Get the PHY in use. */
264 #define SIOCGMIIREG (SIOCDEVPRIVATE+1) /* Read a PHY register. */
265 #define SIOCSMIIREG (SIOCDEVPRIVATE+2) /* Write a PHY register */