drivers/pci/pci.c

   1 /*
   2  *      $Id: pci.c,v 1.88 1998/08/15 10:37:12 mj Exp $
   3  *
   4  *      PCI Bus Services, see include/linux/pci.h for further explanation.
   5  *
   6  *      Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
   7  *      David Mosberger-Tang
   8  *
   9  *      Copyright 1997 -- 1998 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
  10  */
  11
  12 #include <linux/config.h>
  13 #include <linux/types.h>
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/string.h>
  17 #include <linux/init.h>
  18 #include <linux/malloc.h>
  19
  20 #include <asm/page.h>
  21
  22 #undef DEBUG
  23
  24 #ifdef DEBUG
  25 #define DBG(x...) printk(x)
  26 #else
  27 #define DBG(x...)
  28 #endif
  29
  30 struct pci_bus pci_root;
  31 struct pci_dev *pci_devices = NULL;
  32 static struct pci_dev **pci_last_dev_p = &pci_devices;
  33 static int pci_reverse __initdata = 0;
  34
  35 struct pci_dev *
  36 pci_find_slot(unsigned int bus, unsigned int devfn)
  37 {
  38         struct pci_dev *dev;
  39
  40         for(dev=pci_devices; dev; dev=dev->next)
  41                 if (dev->bus->number == bus && dev->devfn == devfn)
  42                         break;
  43         return dev;
  44 }
  45
  46
  47 struct pci_dev *
  48 pci_find_device(unsigned int vendor, unsigned int device, struct pci_dev *from)
  49 {
  50         if (!from)
  51                 from = pci_devices;
  52         else
  53                 from = from->next;
  54         while (from && (from->vendor != vendor || from->device != device))
  55                 from = from->next;
  56         return from;
  57 }
  58
  59
  60 struct pci_dev *
  61 pci_find_class(unsigned int class, struct pci_dev *from)
  62 {
  63         if (!from)
  64                 from = pci_devices;
  65         else
  66                 from = from->next;
  67         while (from && from->class != class)
  68                 from = from->next;
  69         return from;
  70 }
  71
  72
  73 int
  74 pci_read_config_byte(struct pci_dev *dev, u8 where, u8 *val)
  75 {
  76         return pcibios_read_config_byte(dev->bus->number, dev->devfn, where, val);
  77 }
  78
  79 int
  80 pci_read_config_word(struct pci_dev *dev, u8 where, u16 *val)
  81 {
  82         return pcibios_read_config_word(dev->bus->number, dev->devfn, where, val);
  83 }
  84
  85 int
  86 pci_read_config_dword(struct pci_dev *dev, u8 where, u32 *val)
  87 {
  88         return pcibios_read_config_dword(dev->bus->number, dev->devfn, where, val);
  89 }
  90
  91 int
  92 pci_write_config_byte(struct pci_dev *dev, u8 where, u8 val)
  93 {
  94         return pcibios_write_config_byte(dev->bus->number, dev->devfn, where, val);
  95 }
  96
  97 int
  98 pci_write_config_word(struct pci_dev *dev, u8 where, u16 val)
  99 {
 100         return pcibios_write_config_word(dev->bus->number, dev->devfn, where, val);
 101 }
 102
 103 int
 104 pci_write_config_dword(struct pci_dev *dev, u8 where, u32 val)
 105 {
 106         return pcibios_write_config_dword(dev->bus->number, dev->devfn, where, val);
 107 }
 108
 109
 110 void
 111 pci_set_master(struct pci_dev *dev)
 112 {
 113         u16 cmd;
 114         u8 lat;
 115
 116         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 117         if (! (cmd & PCI_COMMAND_MASTER)) {
 118                 printk("PCI: Enabling bus mastering for device %02x:%02x\n",
 119                         dev->bus->number, dev->devfn);
 120                 cmd |= PCI_COMMAND_MASTER;
 121                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 122         }
 123         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 124         if (lat < 16) {
 125                 printk("PCI: Increasing latency timer of device %02x:%02x to 64\n",
 126                         dev->bus->number, dev->devfn);
 127                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 128         }
 129 }
 130
 131 __initfunc(void pci_read_bases(struct pci_dev *dev, unsigned int howmany))
 132 {
 133         unsigned int reg;
 134         u32 l;
 135
 136         for(reg=0; reg<howmany; reg++) {
 137                 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (reg << 2), &l);
 138                 if (l == 0xffffffff)
 139                         continue;
 140                 dev->base_address[reg] = l;
 141                 if ((l & PCI_MEMORY_RANGE_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64) {
 142                         reg++;
 143                         pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (reg << 2), &l);
 144                         if (l) {
 145 #if BITS_PER_LONG == 64
 146                                 dev->base_address[reg-1] |= ((unsigned long) l) << 32;
 147 #else
 148                                 printk("PCI: Unable to handle 64-bit address for device %02x:%02x\n",
 149                                         dev->bus->number, dev->devfn);
 150                                 dev->base_address[reg-1] = 0;
 151 #endif
 152                         }
 153                 }
 154         }
 155 }
 156
 157
 158 __initfunc(unsigned int pci_scan_bus(struct pci_bus *bus))
 159 {
 160         unsigned int devfn, l, max, class;
 161         unsigned char cmd, irq, tmp, hdr_type, is_multi = 0;
 162         struct pci_dev *dev, **bus_last;
 163         struct pci_bus *child;
 164
 165         DBG("pci_scan_bus for bus %d\n", bus->number);
 166         bus_last = &bus->devices;
 167         max = bus->secondary;
 168         for (devfn = 0; devfn < 0xff; ++devfn) {
 169                 if (PCI_FUNC(devfn) && !is_multi) {
 170                         /* not a multi-function device */
 171                         continue;
 172                 }
 173                 if (pcibios_read_config_byte(bus->number, devfn, PCI_HEADER_TYPE, &hdr_type))
 174                         continue;
 175                 if (!PCI_FUNC(devfn))
 176                         is_multi = hdr_type & 0x80;
 177
 178                 if (pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID, &l) ||
 179                     /* some broken boards return 0 if a slot is empty: */
 180                     l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff || l == 0xffff0000) {
 181                         is_multi = 0;
 182                         continue;
 183                 }
 184
 185                 dev = kmalloc(sizeof(*dev), GFP_ATOMIC);
 186                 memset(dev, 0, sizeof(*dev));
 187                 dev->bus = bus;
 188                 dev->devfn  = devfn;
 189                 dev->vendor = l & 0xffff;
 190                 dev->device = (l >> 16) & 0xffff;
 191
 192                 /* non-destructively determine if device can be a master: */
 193                 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND, &cmd);
 194                 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
 195                 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND, &tmp);
 196                 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
 197                 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND, cmd);
 198
 199                 pcibios_read_config_dword(bus->number, devfn, PCI_CLASS_REVISION, &class);
 200                 class >>= 8;                                /* upper 3 bytes */
 201                 dev->class = class;
 202                 class >>= 8;
 203                 dev->hdr_type = hdr_type;
 204
 205                 switch (hdr_type & 0x7f) {                  /* header type */
 206                 case PCI_HEADER_TYPE_NORMAL:                /* standard header */
 207                         if (class == PCI_CLASS_BRIDGE_PCI)
 208                                 goto bad;
 209                         /*
 210                          * If the card generates interrupts, read IRQ number
 211                          * (some architectures change it during pcibios_fixup())
 212                          */
 213                         pcibios_read_config_byte(bus->number, dev->devfn, PCI_INTERRUPT_PIN, &irq);
 214                         if (irq)
 215                                 pcibios_read_config_byte(bus->number, dev->devfn, PCI_INTERRUPT_LINE, &irq);
 216                         dev->irq = irq;
 217                         /*
 218                          * read base address registers, again pcibios_fixup() can
 219                          * tweak these
 220                          */
 221                         pci_read_bases(dev, 6);
 222                         pcibios_read_config_dword(bus->number, devfn, PCI_ROM_ADDRESS, &l);
 223                         dev->rom_address = (l == 0xffffffff) ? 0 : l;
 224                         break;
 225                 case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
 226                         if (class != PCI_CLASS_BRIDGE_PCI)
 227                                 goto bad;
 228                         pci_read_bases(dev, 2);
 229                         pcibios_read_config_dword(bus->number, devfn, PCI_ROM_ADDRESS1, &l);
 230                         dev->rom_address = (l == 0xffffffff) ? 0 : l;
 231                         break;
 232                 case PCI_HEADER_TYPE_CARDBUS:               /* CardBus bridge header */
 233                         if (class != PCI_CLASS_BRIDGE_CARDBUS)
 234                                 goto bad;
 235                         pci_read_bases(dev, 1);
 236                         break;
 237                 default:                                    /* unknown header */
 238                 bad:
 239                         printk(KERN_ERR "PCI: %02x:%02x [%04x/%04x/%06x] has unknown header type %02x, ignoring.\n",
 240                                bus->number, dev->devfn, dev->vendor, dev->device, class, hdr_type);
 241                         continue;
 242                 }
 243
 244                 DBG("PCI: %02x:%02x [%04x/%04x]\n", bus->number, dev->devfn, dev->vendor, dev->device);
 245
 246                 /*
 247                  * Put it into the global PCI device chain. It's used to
 248                  * find devices once everything is set up.
 249                  */
 250                 if (!pci_reverse) {
 251                         *pci_last_dev_p = dev;
 252                         pci_last_dev_p = &dev->next;
 253                 } else {
 254                         dev->next = pci_devices;
 255                         pci_devices = dev;
 256                 }
 257
 258                 /*
 259                  * Now insert it into the list of devices held
 260                  * by the parent bus.
 261                  */
 262                 *bus_last = dev;
 263                 bus_last = &dev->sibling;
 264
 265 #if 0
 266                 /*
 267                  * Setting of latency timer in case it was less than 32 was
 268                  * a great idea, but it confused several broken devices. Grrr.
 269                  */
 270                 pcibios_read_config_byte(bus->number, dev->devfn, PCI_LATENCY_TIMER, &tmp);
 271                 if (tmp < 32)
 272                         pcibios_write_config_byte(bus->number, dev->devfn, PCI_LATENCY_TIMER, 32);
 273 #endif
 274         }
 275
 276         /*
 277          * After performing arch-dependent fixup of the bus, look behind
 278          * all PCI-to-PCI bridges on this bus.
 279          */
 280         pcibios_fixup_bus(bus);
 281         for(dev=bus->devices; dev; dev=dev->sibling)
 282                 /*
 283                  * If it's a bridge, scan the bus behind it.
 284                  */
 285                 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 286                         unsigned int buses;
 287                         unsigned int devfn = dev->devfn;
 288                         unsigned short cr;
 289
 290                         /*
 291                          * Insert it into the tree of buses.
 292                          */
 293                         child = kmalloc(sizeof(*child), GFP_ATOMIC);
 294                         memset(child, 0, sizeof(*child));
 295                         child->next = bus->children;
 296                         bus->children = child;
 297                         child->self = dev;
 298                         child->parent = bus;
 299
 300                         /*
 301                          * Set up the primary, secondary and subordinate
 302                          * bus numbers.
 303                          */
 304                         child->number = child->secondary = ++max;
 305                         child->primary = bus->secondary;
 306                         child->subordinate = 0xff;
 307                         /*
 308                          * Clear all status bits and turn off memory,
 309                          * I/O and master enables.
 310                          */
 311                         pcibios_read_config_word(bus->number, devfn, PCI_COMMAND, &cr);
 312                         pcibios_write_config_word(bus->number, devfn, PCI_COMMAND, 0x0000);
 313                         pcibios_write_config_word(bus->number, devfn, PCI_STATUS, 0xffff);
 314                         /*
 315                          * Read the existing primary/secondary/subordinate bus
 316                          * number configuration to determine if the PCI bridge
 317                          * has already been configured by the system.  If so,
 318                          * do not modify the configuration, merely note it.
 319                          */
 320                         pcibios_read_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, &buses);
 321                         if ((buses & 0xFFFFFF) != 0)
 322                           {
 323                             unsigned int cmax;
 324
 325                             child->primary = buses & 0xFF;
 326                             child->secondary = (buses >> 8) & 0xFF;
 327                             child->subordinate = (buses >> 16) & 0xFF;
 328                             child->number = child->secondary;
 329                             cmax = pci_scan_bus(child);
 330                             if (cmax > max) max = cmax;
 331                           }
 332                         else
 333                           {
 334                             /*
 335                              * Configure the bus numbers for this bridge:
 336                              */
 337                             buses &= 0xff000000;
 338                             buses |=
 339                               (((unsigned int)(child->primary)     <<  0) |
 340                                ((unsigned int)(child->secondary)   <<  8) |
 341                                ((unsigned int)(child->subordinate) << 16));
 342                             pcibios_write_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, buses);
 343                             /*
 344                              * Now we can scan all subordinate buses:
 345                              */
 346                             max = pci_scan_bus(child);
 347                             /*
 348                              * Set the subordinate bus number to its real
 349                              * value:
 350                              */
 351                             child->subordinate = max;
 352                             buses = (buses & 0xff00ffff)
 353                               | ((unsigned int)(child->subordinate) << 16);
 354                             pcibios_write_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, buses);
 355                           }
 356                         pcibios_write_config_word(bus->number, devfn, PCI_COMMAND, cr);
 357                 }
 358
 359         /*
 360          * We've scanned the bus and so we know all about what's on
 361          * the other side of any bridges that may be on this bus plus
 362          * any devices.
 363          *
 364          * Return how far we've got finding sub-buses.
 365          */
 366         DBG("PCI: pci_scan_bus returning with max=%02x\n", max);
 367         return max;
 368 }
 369
 370
 371 __initfunc(void pci_init(void))
 372 {
 373         pcibios_init();
 374
 375         if (!pci_present()) {
 376                 printk("PCI: No PCI bus detected\n");
 377                 return;
 378         }
 379
 380         printk("PCI: Probing PCI hardware\n");
 381
 382         memset(&pci_root, 0, sizeof(pci_root));
 383         pci_root.subordinate = pci_scan_bus(&pci_root);
 384
 385         /* give BIOS a chance to apply platform specific fixes: */
 386         pcibios_fixup();
 387
 388 #ifdef CONFIG_PCI_QUIRKS
 389         pci_quirks_init();
 390 #endif
 391
 392 #ifdef CONFIG_PROC_FS
 393         pci_proc_init();
 394 #endif
 395 }
 396
 397
 398 __initfunc(void pci_setup (char *str, int *ints))
 399 {
 400         while (str) {
 401                 char *k = strchr(str, ',');
 402                 if (k)
 403                         *k++ = 0;
 404                 if (*str && (str = pcibios_setup(str)) && *str) {
 405                         if (!strcmp(str, "reverse"))
 406                                 pci_reverse = 1;
 407                         else printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
 408                 }
 409                 str = k;
 410         }
 411 }