1 /* $Id: pci_psycho.c,v 1.17 2000/09/21 06:25:14 anton Exp $
2 * pci_psycho.c: PSYCHO/U2P specific PCI controller support.
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/init.h>
13 #include <linux/malloc.h>
16 #include <asm/iommu.h>
18 #include <asm/starfire.h>
22 /* All PSYCHO registers are 64-bits. The following accessor
23 * routines are how they are accessed. The REG parameter
24 * is a physical address.
26 #define psycho_read(__reg) \
28 __asm__ __volatile__("ldxa [%1] %2, %0" \
30 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
34 #define psycho_write(__reg, __val) \
35 __asm__ __volatile__("stxa %0, [%1] %2" \
37 : "r" (__val), "r" (__reg), \
38 "i" (ASI_PHYS_BYPASS_EC_E))
40 /* Misc. PSYCHO PCI controller register offsets and definitions. */
41 #define PSYCHO_CONTROL 0x0010UL
42 #define PSYCHO_CONTROL_IMPL 0xf000000000000000 /* Implementation of this PSYCHO*/
43 #define PSYCHO_CONTROL_VER 0x0f00000000000000 /* Version of this PSYCHO */
44 #define PSYCHO_CONTROL_MID 0x00f8000000000000 /* UPA Module ID of PSYCHO */
45 #define PSYCHO_CONTROL_IGN 0x0007c00000000000 /* Interrupt Group Number */
46 #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0 /* Reserved */
47 #define PSYCHO_CONTROL_APCKEN 0x0000000000000008 /* Address Parity Check Enable */
48 #define PSYCHO_CONTROL_APERR 0x0000000000000004 /* Incoming System Addr Parerr */
49 #define PSYCHO_CONTROL_IAP 0x0000000000000002 /* Invert UPA Parity */
50 #define PSYCHO_CONTROL_MODE 0x0000000000000001 /* PSYCHO clock mode */
51 #define PSYCHO_PCIA_CTRL 0x2000UL
52 #define PSYCHO_PCIB_CTRL 0x4000UL
53 #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000 /* Reserved */
54 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000 /* Streaming byte hole error */
55 #define PSYCHO_PCICTRL_SERR 0x0000000400000000 /* SERR signal asserted */
56 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000 /* PCI speed (1 is U2P clock) */
57 #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000 /* Reserved */
58 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000 /* PCI arbitration parking */
59 #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800 /* Reserved */
60 #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400 /* Streaming byte hole int enab */
61 #define PSYCHO_PCICTRL_WEN 0x0000000000000200 /* Power Mgmt Wake Enable */
62 #define PSYCHO_PCICTRL_EEN 0x0000000000000100 /* PCI Error Interrupt Enable */
63 #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0 /* Reserved */
64 #define PSYCHO_PCICTRL_AEN 0x000000000000003f /* PCI DVMA Arbitration Enable */
66 /* U2P Programmer's Manual, page 13-55, configuration space
69 * 32 24 23 16 15 11 10 8 7 2 1 0
70 * ---------------------------------------------------------
71 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
72 * ---------------------------------------------------------
74 #define PSYCHO_CONFIG_BASE(PBM) \
75 ((PBM)->parent->config_space | (1UL << 24))
76 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
77 (((unsigned long)(BUS) << 16) | \
78 ((unsigned long)(DEVFN) << 8) | \
79 ((unsigned long)(REG)))
81 static void *psycho_pci_config_mkaddr(struct pci_pbm_info
*pbm
,
89 (PSYCHO_CONFIG_BASE(pbm
) |
90 PSYCHO_CONFIG_ENCODE(bus
, devfn
, where
));
93 static int psycho_out_of_range(struct pci_pbm_info
*pbm
,
97 return ((pbm
->parent
== 0) ||
98 ((pbm
== &pbm
->parent
->pbm_B
) &&
99 (bus
== pbm
->pci_first_busno
) &&
100 PCI_SLOT(devfn
) > 8) ||
101 ((pbm
== &pbm
->parent
->pbm_A
) &&
102 (bus
== pbm
->pci_first_busno
) &&
103 PCI_SLOT(devfn
) > 8));
106 /* PSYCHO PCI configuration space accessors. */
108 static int psycho_read_byte(struct pci_dev
*dev
, int where
, u8
*value
)
110 struct pci_pbm_info
*pbm
= pci_bus2pbm
[dev
->bus
->number
];
111 unsigned char bus
= dev
->bus
->number
;
112 unsigned int devfn
= dev
->devfn
;
116 addr
= psycho_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
118 return PCIBIOS_SUCCESSFUL
;
120 if (psycho_out_of_range(pbm
, bus
, devfn
))
121 return PCIBIOS_SUCCESSFUL
;
122 pci_config_read8(addr
, value
);
123 return PCIBIOS_SUCCESSFUL
;
126 static int psycho_read_word(struct pci_dev
*dev
, int where
, u16
*value
)
128 struct pci_pbm_info
*pbm
= pci_bus2pbm
[dev
->bus
->number
];
129 unsigned char bus
= dev
->bus
->number
;
130 unsigned int devfn
= dev
->devfn
;
134 addr
= psycho_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
136 return PCIBIOS_SUCCESSFUL
;
138 if (psycho_out_of_range(pbm
, bus
, devfn
))
139 return PCIBIOS_SUCCESSFUL
;
142 printk("pcibios_read_config_word: misaligned reg [%x]\n",
144 return PCIBIOS_SUCCESSFUL
;
146 pci_config_read16(addr
, value
);
147 return PCIBIOS_SUCCESSFUL
;
150 static int psycho_read_dword(struct pci_dev
*dev
, int where
, u32
*value
)
152 struct pci_pbm_info
*pbm
= pci_bus2pbm
[dev
->bus
->number
];
153 unsigned char bus
= dev
->bus
->number
;
154 unsigned int devfn
= dev
->devfn
;
158 addr
= psycho_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
160 return PCIBIOS_SUCCESSFUL
;
162 if (psycho_out_of_range(pbm
, bus
, devfn
))
163 return PCIBIOS_SUCCESSFUL
;
166 printk("pcibios_read_config_dword: misaligned reg [%x]\n",
168 return PCIBIOS_SUCCESSFUL
;
171 pci_config_read32(addr
, value
);
172 return PCIBIOS_SUCCESSFUL
;
175 static int psycho_write_byte(struct pci_dev
*dev
, int where
, u8 value
)
177 struct pci_pbm_info
*pbm
= pci_bus2pbm
[dev
->bus
->number
];
178 unsigned char bus
= dev
->bus
->number
;
179 unsigned int devfn
= dev
->devfn
;
182 addr
= psycho_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
184 return PCIBIOS_SUCCESSFUL
;
186 if (psycho_out_of_range(pbm
, bus
, devfn
))
187 return PCIBIOS_SUCCESSFUL
;
189 pci_config_write8(addr
, value
);
190 return PCIBIOS_SUCCESSFUL
;
193 static int psycho_write_word(struct pci_dev
*dev
, int where
, u16 value
)
195 struct pci_pbm_info
*pbm
= pci_bus2pbm
[dev
->bus
->number
];
196 unsigned char bus
= dev
->bus
->number
;
197 unsigned int devfn
= dev
->devfn
;
200 addr
= psycho_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
202 return PCIBIOS_SUCCESSFUL
;
204 if (psycho_out_of_range(pbm
, bus
, devfn
))
205 return PCIBIOS_SUCCESSFUL
;
208 printk("pcibios_write_config_word: misaligned reg [%x]\n",
210 return PCIBIOS_SUCCESSFUL
;
212 pci_config_write16(addr
, value
);
213 return PCIBIOS_SUCCESSFUL
;
216 static int psycho_write_dword(struct pci_dev
*dev
, int where
, u32 value
)
218 struct pci_pbm_info
*pbm
= pci_bus2pbm
[dev
->bus
->number
];
219 unsigned char bus
= dev
->bus
->number
;
220 unsigned int devfn
= dev
->devfn
;
223 addr
= psycho_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
225 return PCIBIOS_SUCCESSFUL
;
227 if (psycho_out_of_range(pbm
, bus
, devfn
))
228 return PCIBIOS_SUCCESSFUL
;
231 printk("pcibios_write_config_dword: misaligned reg [%x]\n",
233 return PCIBIOS_SUCCESSFUL
;
235 pci_config_write32(addr
, value
);
236 return PCIBIOS_SUCCESSFUL
;
239 static struct pci_ops psycho_ops
= {
248 /* PSYCHO interrupt mapping support. */
249 #define PSYCHO_IMAP_A_SLOT0 0x0c00UL
250 #define PSYCHO_IMAP_B_SLOT0 0x0c20UL
251 static unsigned long psycho_pcislot_imap_offset(unsigned long ino
)
253 unsigned int bus
= (ino
& 0x10) >> 4;
254 unsigned int slot
= (ino
& 0x0c) >> 2;
257 return PSYCHO_IMAP_A_SLOT0
+ (slot
* 8);
259 return PSYCHO_IMAP_B_SLOT0
+ (slot
* 8);
262 #define PSYCHO_IMAP_SCSI 0x1000UL
263 #define PSYCHO_IMAP_ETH 0x1008UL
264 #define PSYCHO_IMAP_BPP 0x1010UL
265 #define PSYCHO_IMAP_AU_REC 0x1018UL
266 #define PSYCHO_IMAP_AU_PLAY 0x1020UL
267 #define PSYCHO_IMAP_PFAIL 0x1028UL
268 #define PSYCHO_IMAP_KMS 0x1030UL
269 #define PSYCHO_IMAP_FLPY 0x1038UL
270 #define PSYCHO_IMAP_SHW 0x1040UL
271 #define PSYCHO_IMAP_KBD 0x1048UL
272 #define PSYCHO_IMAP_MS 0x1050UL
273 #define PSYCHO_IMAP_SER 0x1058UL
274 #define PSYCHO_IMAP_TIM0 0x1060UL
275 #define PSYCHO_IMAP_TIM1 0x1068UL
276 #define PSYCHO_IMAP_UE 0x1070UL
277 #define PSYCHO_IMAP_CE 0x1078UL
278 #define PSYCHO_IMAP_A_ERR 0x1080UL
279 #define PSYCHO_IMAP_B_ERR 0x1088UL
280 #define PSYCHO_IMAP_PMGMT 0x1090UL
281 #define PSYCHO_IMAP_GFX 0x1098UL
282 #define PSYCHO_IMAP_EUPA 0x10a0UL
284 static unsigned long __onboard_imap_off
[] = {
285 /*0x20*/ PSYCHO_IMAP_SCSI
,
286 /*0x21*/ PSYCHO_IMAP_ETH
,
287 /*0x22*/ PSYCHO_IMAP_BPP
,
288 /*0x23*/ PSYCHO_IMAP_AU_REC
,
289 /*0x24*/ PSYCHO_IMAP_AU_PLAY
,
290 /*0x25*/ PSYCHO_IMAP_PFAIL
,
291 /*0x26*/ PSYCHO_IMAP_KMS
,
292 /*0x27*/ PSYCHO_IMAP_FLPY
,
293 /*0x28*/ PSYCHO_IMAP_SHW
,
294 /*0x29*/ PSYCHO_IMAP_KBD
,
295 /*0x2a*/ PSYCHO_IMAP_MS
,
296 /*0x2b*/ PSYCHO_IMAP_SER
,
297 /*0x2c*/ PSYCHO_IMAP_TIM0
,
298 /*0x2d*/ PSYCHO_IMAP_TIM1
,
299 /*0x2e*/ PSYCHO_IMAP_UE
,
300 /*0x2f*/ PSYCHO_IMAP_CE
,
301 /*0x30*/ PSYCHO_IMAP_A_ERR
,
302 /*0x31*/ PSYCHO_IMAP_B_ERR
,
303 /*0x32*/ PSYCHO_IMAP_PMGMT
305 #define PSYCHO_ONBOARD_IRQ_BASE 0x20
306 #define PSYCHO_ONBOARD_IRQ_LAST 0x32
307 #define psycho_onboard_imap_offset(__ino) \
308 __onboard_imap_off[(__ino) - PSYCHO_ONBOARD_IRQ_BASE]
310 #define PSYCHO_ICLR_A_SLOT0 0x1400UL
311 #define PSYCHO_ICLR_SCSI 0x1800UL
313 #define psycho_iclr_offset(ino) \
314 ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
315 (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
317 /* PCI PSYCHO INO number to Sparc PIL level. */
318 static unsigned char psycho_pil_table
[] = {
319 /*0x00*/0, 0, 0, 0, /* PCI A slot 0 Int A, B, C, D */
320 /*0x04*/0, 0, 0, 0, /* PCI A slot 1 Int A, B, C, D */
321 /*0x08*/0, 0, 0, 0, /* PCI A slot 2 Int A, B, C, D */
322 /*0x0c*/0, 0, 0, 0, /* PCI A slot 3 Int A, B, C, D */
323 /*0x10*/0, 0, 0, 0, /* PCI B slot 0 Int A, B, C, D */
324 /*0x14*/0, 0, 0, 0, /* PCI B slot 1 Int A, B, C, D */
325 /*0x18*/0, 0, 0, 0, /* PCI B slot 2 Int A, B, C, D */
326 /*0x1c*/0, 0, 0, 0, /* PCI B slot 3 Int A, B, C, D */
327 /*0x20*/3, /* SCSI */
328 /*0x21*/5, /* Ethernet */
329 /*0x22*/8, /* Parallel Port */
330 /*0x23*/13, /* Audio Record */
331 /*0x24*/14, /* Audio Playback */
332 /*0x25*/15, /* PowerFail */
333 /*0x26*/3, /* second SCSI */
334 /*0x27*/11, /* Floppy */
335 /*0x28*/2, /* Spare Hardware */
336 /*0x29*/9, /* Keyboard */
337 /*0x2a*/4, /* Mouse */
338 /*0x2b*/12, /* Serial */
339 /*0x2c*/10, /* Timer 0 */
340 /*0x2d*/11, /* Timer 1 */
341 /*0x2e*/15, /* Uncorrectable ECC */
342 /*0x2f*/15, /* Correctable ECC */
343 /*0x30*/15, /* PCI Bus A Error */
344 /*0x31*/15, /* PCI Bus B Error */
345 /*0x32*/1, /* Power Management */
348 static int __init
psycho_ino_to_pil(struct pci_dev
*pdev
, unsigned int ino
)
352 ret
= psycho_pil_table
[ino
];
353 if (ret
== 0 && pdev
== NULL
) {
355 } else if (ret
== 0) {
356 switch ((pdev
->class >> 16) & 0x0f) {
357 case PCI_BASE_CLASS_STORAGE
:
360 case PCI_BASE_CLASS_NETWORK
:
363 case PCI_BASE_CLASS_DISPLAY
:
366 case PCI_BASE_CLASS_MULTIMEDIA
:
367 case PCI_BASE_CLASS_MEMORY
:
368 case PCI_BASE_CLASS_BRIDGE
:
379 static unsigned int __init
psycho_irq_build(struct pci_controller_info
*p
,
380 struct pci_dev
*pdev
,
383 struct ino_bucket
*bucket
;
384 unsigned long imap
, iclr
;
385 unsigned long imap_off
, iclr_off
;
386 int pil
, inofixup
= 0;
389 if (ino
< PSYCHO_ONBOARD_IRQ_BASE
) {
391 imap_off
= psycho_pcislot_imap_offset(ino
);
394 if (ino
> PSYCHO_ONBOARD_IRQ_LAST
) {
395 prom_printf("psycho_irq_build: Wacky INO [%x]\n", ino
);
398 imap_off
= psycho_onboard_imap_offset(ino
);
401 /* Now build the IRQ bucket. */
402 pil
= psycho_ino_to_pil(pdev
, ino
);
403 imap
= p
->controller_regs
+ imap_off
;
406 iclr_off
= psycho_iclr_offset(ino
);
407 iclr
= p
->controller_regs
+ iclr_off
;
410 if ((ino
& 0x20) == 0)
411 inofixup
= ino
& 0x03;
413 bucket
= __bucket(build_irq(pil
, inofixup
, iclr
, imap
));
414 bucket
->flags
|= IBF_PCI
;
416 return __irq(bucket
);
419 /* PSYCHO error handling support. */
420 enum psycho_error_type
{
421 UE_ERR
, CE_ERR
, PCI_ERR
424 /* Helper function of IOMMU error checking, which checks out
425 * the state of the streaming buffers. The IOMMU lock is
426 * held when this is called.
428 * For the PCI error case we know which PBM (and thus which
429 * streaming buffer) caused the error, but for the uncorrectable
430 * error case we do not. So we always check both streaming caches.
432 #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
433 #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
434 #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0 /* LRU Lock Pointer */
435 #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008 /* LRU Lock Enable */
436 #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004 /* Rerun Disable */
437 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002 /* Diagnostic Mode Enable */
438 #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001 /* Streaming Buffer Enable */
439 #define PSYCHO_STRBUF_FLUSH_A 0x2808UL
440 #define PSYCHO_STRBUF_FLUSH_B 0x4808UL
441 #define PSYCHO_STRBUF_FSYNC_A 0x2810UL
442 #define PSYCHO_STRBUF_FSYNC_B 0x4810UL
443 #define PSYCHO_STC_DATA_A 0xb000UL
444 #define PSYCHO_STC_DATA_B 0xc000UL
445 #define PSYCHO_STC_ERR_A 0xb400UL
446 #define PSYCHO_STC_ERR_B 0xc400UL
447 #define PSYCHO_STCERR_WRITE 0x0000000000000002 /* Write Error */
448 #define PSYCHO_STCERR_READ 0x0000000000000001 /* Read Error */
449 #define PSYCHO_STC_TAG_A 0xb800UL
450 #define PSYCHO_STC_TAG_B 0xc800UL
451 #define PSYCHO_STCTAG_PPN 0x0fffffff00000000 /* Physical Page Number */
452 #define PSYCHO_STCTAG_VPN 0x00000000ffffe000 /* Virtual Page Number */
453 #define PSYCHO_STCTAG_VALID 0x0000000000000002 /* Valid */
454 #define PSYCHO_STCTAG_WRITE 0x0000000000000001 /* Writable */
455 #define PSYCHO_STC_LINE_A 0xb900UL
456 #define PSYCHO_STC_LINE_B 0xc900UL
457 #define PSYCHO_STCLINE_LINDX 0x0000000001e00000 /* LRU Index */
458 #define PSYCHO_STCLINE_SPTR 0x00000000001f8000 /* Dirty Data Start Pointer */
459 #define PSYCHO_STCLINE_LADDR 0x0000000000007f00 /* Line Address */
460 #define PSYCHO_STCLINE_EPTR 0x00000000000000fc /* Dirty Data End Pointer */
461 #define PSYCHO_STCLINE_VALID 0x0000000000000002 /* Valid */
462 #define PSYCHO_STCLINE_FOFN 0x0000000000000001 /* Fetch Outstanding / Flush Necessary */
464 static spinlock_t stc_buf_lock
= SPIN_LOCK_UNLOCKED
;
465 static unsigned long stc_error_buf
[128];
466 static unsigned long stc_tag_buf
[16];
467 static unsigned long stc_line_buf
[16];
469 static void __psycho_check_one_stc(struct pci_controller_info
*p
,
470 struct pci_pbm_info
*pbm
,
473 struct pci_strbuf
*strbuf
= &pbm
->stc
;
474 unsigned long regbase
= p
->controller_regs
;
475 unsigned long err_base
, tag_base
, line_base
;
480 err_base
= regbase
+ PSYCHO_STC_ERR_A
;
481 tag_base
= regbase
+ PSYCHO_STC_TAG_A
;
482 line_base
= regbase
+ PSYCHO_STC_LINE_A
;
484 err_base
= regbase
+ PSYCHO_STC_ERR_A
;
485 tag_base
= regbase
+ PSYCHO_STC_TAG_A
;
486 line_base
= regbase
+ PSYCHO_STC_LINE_A
;
489 spin_lock(&stc_buf_lock
);
491 /* This is __REALLY__ dangerous. When we put the
492 * streaming buffer into diagnostic mode to probe
493 * it's tags and error status, we _must_ clear all
494 * of the line tag valid bits before re-enabling
495 * the streaming buffer. If any dirty data lives
496 * in the STC when we do this, we will end up
497 * invalidating it before it has a chance to reach
500 control
= psycho_read(strbuf
->strbuf_control
);
501 psycho_write(strbuf
->strbuf_control
,
502 (control
| PSYCHO_STRBUF_CTRL_DENAB
));
503 for (i
= 0; i
< 128; i
++) {
506 val
= psycho_read(err_base
+ (i
* 8UL));
507 psycho_write(err_base
+ (i
* 8UL), 0UL);
508 stc_error_buf
[i
] = val
;
510 for (i
= 0; i
< 16; i
++) {
511 stc_tag_buf
[i
] = psycho_read(tag_base
+ (i
* 8UL));
512 stc_line_buf
[i
] = psycho_read(line_base
+ (i
* 8UL));
513 psycho_write(tag_base
+ (i
* 8UL), 0UL);
514 psycho_write(line_base
+ (i
* 8UL), 0UL);
517 /* OK, state is logged, exit diagnostic mode. */
518 psycho_write(strbuf
->strbuf_control
, control
);
520 for (i
= 0; i
< 16; i
++) {
521 int j
, saw_error
, first
, last
;
526 for (j
= first
; j
< last
; j
++) {
527 unsigned long errval
= stc_error_buf
[j
];
530 printk("PSYCHO%d(PBM%c): STC_ERR(%d)[wr(%d)rd(%d)]\n",
532 (is_pbm_a
? 'A' : 'B'),
534 (errval
& PSYCHO_STCERR_WRITE
) ? 1 : 0,
535 (errval
& PSYCHO_STCERR_READ
) ? 1 : 0);
538 if (saw_error
!= 0) {
539 unsigned long tagval
= stc_tag_buf
[i
];
540 unsigned long lineval
= stc_line_buf
[i
];
541 printk("PSYCHO%d(PBM%c): STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
543 (is_pbm_a
? 'A' : 'B'),
545 ((tagval
& PSYCHO_STCTAG_PPN
) >> 19UL),
546 (tagval
& PSYCHO_STCTAG_VPN
),
547 ((tagval
& PSYCHO_STCTAG_VALID
) ? 1 : 0),
548 ((tagval
& PSYCHO_STCTAG_WRITE
) ? 1 : 0));
549 printk("PSYCHO%d(PBM%c): STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
552 (is_pbm_a
? 'A' : 'B'),
554 ((lineval
& PSYCHO_STCLINE_LINDX
) >> 21UL),
555 ((lineval
& PSYCHO_STCLINE_SPTR
) >> 15UL),
556 ((lineval
& PSYCHO_STCLINE_LADDR
) >> 8UL),
557 ((lineval
& PSYCHO_STCLINE_EPTR
) >> 2UL),
558 ((lineval
& PSYCHO_STCLINE_VALID
) ? 1 : 0),
559 ((lineval
& PSYCHO_STCLINE_FOFN
) ? 1 : 0));
563 spin_unlock(&stc_buf_lock
);
566 static void __psycho_check_stc_error(struct pci_controller_info
*p
,
569 enum psycho_error_type type
)
571 struct pci_pbm_info
*pbm
;
574 if (pbm
->stc
.strbuf_enabled
)
575 __psycho_check_one_stc(p
, pbm
, 1);
578 if (pbm
->stc
.strbuf_enabled
)
579 __psycho_check_one_stc(p
, pbm
, 0);
582 /* When an Uncorrectable Error or a PCI Error happens, we
583 * interrogate the IOMMU state to see if it is the cause.
585 #define PSYCHO_IOMMU_CONTROL 0x0200UL
586 #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000 /* Reserved */
587 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000 /* Translation Error Status */
588 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000 /* Translation Error encountered */
589 #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000 /* Enable translation locking */
590 #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000 /* Translation lock pointer */
591 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000 /* TSB Size */
592 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000 /* TSB Table 1024 8-byte entries */
593 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000 /* TSB Table 2048 8-byte entries */
594 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000 /* TSB Table 4096 8-byte entries */
595 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000 /* TSB Table 8192 8-byte entries */
596 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000 /* TSB Table 16k 8-byte entries */
597 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000 /* TSB Table 32k 8-byte entries */
598 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000 /* TSB Table 64k 8-byte entries */
599 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000 /* TSB Table 128k 8-byte entries */
600 #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8 /* Reserved */
601 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004 /* Assumed page size, 0=8k 1=64k */
602 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002 /* Diagnostic mode enable */
603 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001 /* IOMMU Enable */
604 #define PSYCHO_IOMMU_TSBBASE 0x0208UL
605 #define PSYCHO_IOMMU_FLUSH 0x0210UL
606 #define PSYCHO_IOMMU_TAG 0xa580UL
607 #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
608 #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
609 #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
610 #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
611 #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
612 #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
613 #define PSYCHO_IOMMU_DATA 0xa600UL
614 #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
615 #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
616 #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
617 static void psycho_check_iommu_error(struct pci_controller_info
*p
,
620 enum psycho_error_type type
)
622 unsigned long iommu_tag
[16];
623 unsigned long iommu_data
[16];
628 spin_lock_irqsave(&p
->iommu
.lock
, flags
);
629 control
= psycho_read(p
->iommu
.iommu_control
);
630 if (control
& PSYCHO_IOMMU_CTRL_XLTEERR
) {
633 /* Clear the error encountered bit. */
634 control
&= ~PSYCHO_IOMMU_CTRL_XLTEERR
;
635 psycho_write(p
->iommu
.iommu_control
, control
);
637 switch((control
& PSYCHO_IOMMU_CTRL_XLTESTAT
) >> 25UL) {
639 type_string
= "Protection Error";
642 type_string
= "Invalid Error";
645 type_string
= "TimeOut Error";
649 type_string
= "ECC Error";
652 printk("PSYCHO%d: IOMMU Error, type[%s]\n",
653 p
->index
, type_string
);
655 /* Put the IOMMU into diagnostic mode and probe
656 * it's TLB for entries with error status.
658 * It is very possible for another DVMA to occur
659 * while we do this probe, and corrupt the system
660 * further. But we are so screwed at this point
661 * that we are likely to crash hard anyways, so
662 * get as much diagnostic information to the
665 psycho_write(p
->iommu
.iommu_control
,
666 control
| PSYCHO_IOMMU_CTRL_DENAB
);
667 for (i
= 0; i
< 16; i
++) {
668 unsigned long base
= p
->controller_regs
;
671 psycho_read(base
+ PSYCHO_IOMMU_TAG
+ (i
* 8UL));
673 psycho_read(base
+ PSYCHO_IOMMU_DATA
+ (i
* 8UL));
675 /* Now clear out the entry. */
676 psycho_write(base
+ PSYCHO_IOMMU_TAG
+ (i
* 8UL), 0);
677 psycho_write(base
+ PSYCHO_IOMMU_DATA
+ (i
* 8UL), 0);
680 /* Leave diagnostic mode. */
681 psycho_write(p
->iommu
.iommu_control
, control
);
683 for (i
= 0; i
< 16; i
++) {
684 unsigned long tag
, data
;
687 if (!(tag
& PSYCHO_IOMMU_TAG_ERR
))
690 data
= iommu_data
[i
];
691 switch((tag
& PSYCHO_IOMMU_TAG_ERRSTS
) >> 23UL) {
693 type_string
= "Protection Error";
696 type_string
= "Invalid Error";
699 type_string
= "TimeOut Error";
703 type_string
= "ECC Error";
706 printk("PSYCHO%d: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
707 p
->index
, i
, type_string
,
708 ((tag
& PSYCHO_IOMMU_TAG_WRITE
) ? 1 : 0),
709 ((tag
& PSYCHO_IOMMU_TAG_STREAM
) ? 1 : 0),
710 ((tag
& PSYCHO_IOMMU_TAG_SIZE
) ? 64 : 8),
711 (tag
& PSYCHO_IOMMU_TAG_VPAGE
) << PAGE_SHIFT
);
712 printk("PSYCHO%d: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
714 ((data
& PSYCHO_IOMMU_DATA_VALID
) ? 1 : 0),
715 ((data
& PSYCHO_IOMMU_DATA_CACHE
) ? 1 : 0),
716 (data
& PSYCHO_IOMMU_DATA_PPAGE
) << PAGE_SHIFT
);
719 __psycho_check_stc_error(p
, afsr
, afar
, type
);
720 spin_unlock_irqrestore(&p
->iommu
.lock
, flags
);
723 /* Uncorrectable Errors. Cause of the error and the address are
724 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
725 * relating to UPA interface transactions.
727 #define PSYCHO_UE_AFSR 0x0030UL
728 #define PSYCHO_UEAFSR_PPIO 0x8000000000000000 /* Primary PIO is cause */
729 #define PSYCHO_UEAFSR_PDRD 0x4000000000000000 /* Primary DVMA read is cause */
730 #define PSYCHO_UEAFSR_PDWR 0x2000000000000000 /* Primary DVMA write is cause */
731 #define PSYCHO_UEAFSR_SPIO 0x1000000000000000 /* Secondary PIO is cause */
732 #define PSYCHO_UEAFSR_SDRD 0x0800000000000000 /* Secondary DVMA read is cause */
733 #define PSYCHO_UEAFSR_SDWR 0x0400000000000000 /* Secondary DVMA write is cause*/
734 #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000 /* Reserved */
735 #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000 /* Bytemask of failed transfer */
736 #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000 /* Doubleword Offset */
737 #define PSYCHO_UEAFSR_MID 0x000000001f000000 /* UPA MID causing the fault */
738 #define PSYCHO_UEAFSR_BLK 0x0000000000800000 /* Trans was block operation */
739 #define PSYCHO_UEAFSR_RESV2 0x00000000007fffff /* Reserved */
740 #define PSYCHO_UE_AFAR 0x0038UL
742 static void psycho_ue_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
744 struct pci_controller_info
*p
= dev_id
;
745 unsigned long afsr_reg
= p
->controller_regs
+ PSYCHO_UE_AFSR
;
746 unsigned long afar_reg
= p
->controller_regs
+ PSYCHO_UE_AFAR
;
747 unsigned long afsr
, afar
, error_bits
;
750 /* Latch uncorrectable error status. */
751 afar
= psycho_read(afar_reg
);
752 afsr
= psycho_read(afsr_reg
);
754 /* Clear the primary/secondary error status bits. */
756 (PSYCHO_UEAFSR_PPIO
| PSYCHO_UEAFSR_PDRD
| PSYCHO_UEAFSR_PDWR
|
757 PSYCHO_UEAFSR_SPIO
| PSYCHO_UEAFSR_SDRD
| PSYCHO_UEAFSR_SDWR
);
758 psycho_write(afsr_reg
, error_bits
);
761 printk("PSYCHO%d: Uncorrectable Error, primary error type[%s]\n",
763 (((error_bits
& PSYCHO_UEAFSR_PPIO
) ?
765 ((error_bits
& PSYCHO_UEAFSR_PDRD
) ?
767 ((error_bits
& PSYCHO_UEAFSR_PDWR
) ?
768 "DMA Write" : "???")))));
769 printk("PSYCHO%d: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
771 (afsr
& PSYCHO_UEAFSR_BMSK
) >> 32UL,
772 (afsr
& PSYCHO_UEAFSR_DOFF
) >> 29UL,
773 (afsr
& PSYCHO_UEAFSR_MID
) >> 24UL,
774 ((afsr
& PSYCHO_UEAFSR_BLK
) ? 1 : 0));
775 printk("PSYCHO%d: UE AFAR [%016lx]\n", p
->index
, afar
);
776 printk("PSYCHO%d: UE Secondary errors [", p
->index
);
778 if (afsr
& PSYCHO_UEAFSR_SPIO
) {
782 if (afsr
& PSYCHO_UEAFSR_SDRD
) {
784 printk("(DMA Read)");
786 if (afsr
& PSYCHO_UEAFSR_SDWR
) {
788 printk("(DMA Write)");
794 /* Interrogate IOMMU for error status. */
795 psycho_check_iommu_error(p
, afsr
, afar
, UE_ERR
);
798 /* Correctable Errors. */
799 #define PSYCHO_CE_AFSR 0x0040UL
800 #define PSYCHO_CEAFSR_PPIO 0x8000000000000000 /* Primary PIO is cause */
801 #define PSYCHO_CEAFSR_PDRD 0x4000000000000000 /* Primary DVMA read is cause */
802 #define PSYCHO_CEAFSR_PDWR 0x2000000000000000 /* Primary DVMA write is cause */
803 #define PSYCHO_CEAFSR_SPIO 0x1000000000000000 /* Secondary PIO is cause */
804 #define PSYCHO_CEAFSR_SDRD 0x0800000000000000 /* Secondary DVMA read is cause */
805 #define PSYCHO_CEAFSR_SDWR 0x0400000000000000 /* Secondary DVMA write is cause*/
806 #define PSYCHO_CEAFSR_RESV1 0x0300000000000000 /* Reserved */
807 #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000 /* Syndrome Bits */
808 #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000 /* Bytemask of failed transfer */
809 #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000 /* Double Offset */
810 #define PSYCHO_CEAFSR_MID 0x000000001f000000 /* UPA MID causing the fault */
811 #define PSYCHO_CEAFSR_BLK 0x0000000000800000 /* Trans was block operation */
812 #define PSYCHO_CEAFSR_RESV2 0x00000000007fffff /* Reserved */
813 #define PSYCHO_CE_AFAR 0x0040UL
815 static void psycho_ce_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
817 struct pci_controller_info
*p
= dev_id
;
818 unsigned long afsr_reg
= p
->controller_regs
+ PSYCHO_CE_AFSR
;
819 unsigned long afar_reg
= p
->controller_regs
+ PSYCHO_CE_AFAR
;
820 unsigned long afsr
, afar
, error_bits
;
823 /* Latch error status. */
824 afar
= psycho_read(afar_reg
);
825 afsr
= psycho_read(afsr_reg
);
827 /* Clear primary/secondary error status bits. */
829 (PSYCHO_CEAFSR_PPIO
| PSYCHO_CEAFSR_PDRD
| PSYCHO_CEAFSR_PDWR
|
830 PSYCHO_CEAFSR_SPIO
| PSYCHO_CEAFSR_SDRD
| PSYCHO_CEAFSR_SDWR
);
831 psycho_write(afsr_reg
, error_bits
);
834 printk("PSYCHO%d: Correctable Error, primary error type[%s]\n",
836 (((error_bits
& PSYCHO_CEAFSR_PPIO
) ?
838 ((error_bits
& PSYCHO_CEAFSR_PDRD
) ?
840 ((error_bits
& PSYCHO_CEAFSR_PDWR
) ?
841 "DMA Write" : "???")))));
843 /* XXX Use syndrome and afar to print out module string just like
844 * XXX UDB CE trap handler does... -DaveM
846 printk("PSYCHO%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
847 "UPA_MID[%02lx] was_block(%d)\n",
849 (afsr
& PSYCHO_CEAFSR_ESYND
) >> 48UL,
850 (afsr
& PSYCHO_CEAFSR_BMSK
) >> 32UL,
851 (afsr
& PSYCHO_CEAFSR_DOFF
) >> 29UL,
852 (afsr
& PSYCHO_CEAFSR_MID
) >> 24UL,
853 ((afsr
& PSYCHO_CEAFSR_BLK
) ? 1 : 0));
854 printk("PSYCHO%d: CE AFAR [%016lx]\n", p
->index
, afar
);
855 printk("PSYCHO%d: CE Secondary errors [", p
->index
);
857 if (afsr
& PSYCHO_CEAFSR_SPIO
) {
861 if (afsr
& PSYCHO_CEAFSR_SDRD
) {
863 printk("(DMA Read)");
865 if (afsr
& PSYCHO_CEAFSR_SDWR
) {
867 printk("(DMA Write)");
874 /* PCI Errors. They are signalled by the PCI bus module since they
875 * are assosciated with a specific bus segment.
877 #define PSYCHO_PCI_AFSR_A 0x2010UL
878 #define PSYCHO_PCI_AFSR_B 0x4010UL
879 #define PSYCHO_PCIAFSR_PMA 0x8000000000000000 /* Primary Master Abort Error */
880 #define PSYCHO_PCIAFSR_PTA 0x4000000000000000 /* Primary Target Abort Error */
881 #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000 /* Primary Excessive Retries */
882 #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000 /* Primary Parity Error */
883 #define PSYCHO_PCIAFSR_SMA 0x0800000000000000 /* Secondary Master Abort Error */
884 #define PSYCHO_PCIAFSR_STA 0x0400000000000000 /* Secondary Target Abort Error */
885 #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000 /* Secondary Excessive Retries */
886 #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000 /* Secondary Parity Error */
887 #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000 /* Reserved */
888 #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000 /* Bytemask of failed transfer */
889 #define PSYCHO_PCIAFSR_BLK 0x0000000080000000 /* Trans was block operation */
890 #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000 /* Reserved */
891 #define PSYCHO_PCIAFSR_MID 0x000000003e000000 /* MID causing the error */
892 #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffff /* Reserved */
893 #define PSYCHO_PCI_AFAR_A 0x2018UL
894 #define PSYCHO_PCI_AFAR_B 0x4018UL
896 static void psycho_pcierr_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
898 struct pci_pbm_info
*pbm
= dev_id
;
899 struct pci_controller_info
*p
= pbm
->parent
;
900 unsigned long afsr_reg
, afar_reg
;
901 unsigned long afsr
, afar
, error_bits
;
902 int is_pbm_a
, reported
;
904 is_pbm_a
= (pbm
== &pbm
->parent
->pbm_A
);
906 afsr_reg
= p
->controller_regs
+ PSYCHO_PCI_AFSR_A
;
907 afar_reg
= p
->controller_regs
+ PSYCHO_PCI_AFAR_A
;
909 afsr_reg
= p
->controller_regs
+ PSYCHO_PCI_AFSR_B
;
910 afar_reg
= p
->controller_regs
+ PSYCHO_PCI_AFAR_B
;
913 /* Latch error status. */
914 afar
= psycho_read(afar_reg
);
915 afsr
= psycho_read(afsr_reg
);
917 /* Clear primary/secondary error status bits. */
919 (PSYCHO_PCIAFSR_PMA
| PSYCHO_PCIAFSR_PTA
|
920 PSYCHO_PCIAFSR_PRTRY
| PSYCHO_PCIAFSR_PPERR
|
921 PSYCHO_PCIAFSR_SMA
| PSYCHO_PCIAFSR_STA
|
922 PSYCHO_PCIAFSR_SRTRY
| PSYCHO_PCIAFSR_SPERR
);
923 psycho_write(afsr_reg
, error_bits
);
926 printk("PSYCHO%d(PBM%c): PCI Error, primary error type[%s]\n",
927 p
->index
, (is_pbm_a
? 'A' : 'B'),
928 (((error_bits
& PSYCHO_PCIAFSR_PMA
) ?
930 ((error_bits
& PSYCHO_PCIAFSR_PTA
) ?
932 ((error_bits
& PSYCHO_PCIAFSR_PRTRY
) ?
933 "Excessive Retries" :
934 ((error_bits
& PSYCHO_PCIAFSR_PPERR
) ?
935 "Parity Error" : "???"))))));
936 printk("PSYCHO%d(PBM%c): bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
937 p
->index
, (is_pbm_a
? 'A' : 'B'),
938 (afsr
& PSYCHO_PCIAFSR_BMSK
) >> 32UL,
939 (afsr
& PSYCHO_PCIAFSR_MID
) >> 25UL,
940 (afsr
& PSYCHO_PCIAFSR_BLK
) ? 1 : 0);
941 printk("PSYCHO%d(PBM%c): PCI AFAR [%016lx]\n",
942 p
->index
, (is_pbm_a
? 'A' : 'B'), afar
);
943 printk("PSYCHO%d(PBM%c): PCI Secondary errors [",
944 p
->index
, (is_pbm_a
? 'A' : 'B'));
946 if (afsr
& PSYCHO_PCIAFSR_SMA
) {
948 printk("(Master Abort)");
950 if (afsr
& PSYCHO_PCIAFSR_STA
) {
952 printk("(Target Abort)");
954 if (afsr
& PSYCHO_PCIAFSR_SRTRY
) {
956 printk("(Excessive Retries)");
958 if (afsr
& PSYCHO_PCIAFSR_SPERR
) {
960 printk("(Parity Error)");
966 /* For the error types shown, scan PBM's PCI bus for devices
967 * which have logged that error type.
970 /* If we see a Target Abort, this could be the result of an
971 * IOMMU translation error of some sort. It is extremely
972 * useful to log this information as usually it indicates
973 * a bug in the IOMMU support code or a PCI device driver.
975 if (error_bits
& (PSYCHO_PCIAFSR_PTA
| PSYCHO_PCIAFSR_STA
)) {
976 psycho_check_iommu_error(p
, afsr
, afar
, PCI_ERR
);
977 pci_scan_for_target_abort(p
, pbm
, pbm
->pci_bus
);
979 if (error_bits
& (PSYCHO_PCIAFSR_PMA
| PSYCHO_PCIAFSR_SMA
))
980 pci_scan_for_master_abort(p
, pbm
, pbm
->pci_bus
);
982 /* For excessive retries, PSYCHO/PBM will abort the device
983 * and there is no way to specifically check for excessive
984 * retries in the config space status registers. So what
985 * we hope is that we'll catch it via the master/target
989 if (error_bits
& (PSYCHO_PCIAFSR_PPERR
| PSYCHO_PCIAFSR_SPERR
))
990 pci_scan_for_parity_error(p
, pbm
, pbm
->pci_bus
);
993 /* XXX What about PowerFail/PowerManagement??? -DaveM */
994 #define PSYCHO_ECC_CTRL 0x0020
995 #define PSYCHO_ECCCTRL_EE 0x8000000000000000 /* Enable ECC Checking */
996 #define PSYCHO_ECCCTRL_UE 0x4000000000000000 /* Enable UE Interrupts */
997 #define PSYCHO_ECCCTRL_CE 0x2000000000000000 /* Enable CE INterrupts */
998 #define PSYCHO_UE_INO 0x2e
999 #define PSYCHO_CE_INO 0x2f
1000 #define PSYCHO_PCIERR_A_INO 0x30
1001 #define PSYCHO_PCIERR_B_INO 0x31
1002 static void __init
psycho_register_error_handlers(struct pci_controller_info
*p
)
1004 unsigned long base
= p
->controller_regs
;
1005 unsigned int irq
, portid
= p
->portid
;
1008 /* Build IRQs and register handlers. */
1009 irq
= psycho_irq_build(p
, NULL
, (portid
<< 6) | PSYCHO_UE_INO
);
1010 if (request_irq(irq
, psycho_ue_intr
,
1011 SA_SHIRQ
, "PSYCHO UE", p
) < 0) {
1012 prom_printf("PSYCHO%d: Cannot register UE interrupt.\n",
1017 irq
= psycho_irq_build(p
, NULL
, (portid
<< 6) | PSYCHO_CE_INO
);
1018 if (request_irq(irq
, psycho_ce_intr
,
1019 SA_SHIRQ
, "PSYCHO CE", p
) < 0) {
1020 prom_printf("PSYCHO%d: Cannot register CE interrupt.\n",
1025 irq
= psycho_irq_build(p
, NULL
, (portid
<< 6) | PSYCHO_PCIERR_A_INO
);
1026 if (request_irq(irq
, psycho_pcierr_intr
,
1027 SA_SHIRQ
, "PSYCHO PCIERR", &p
->pbm_A
) < 0) {
1028 prom_printf("PSYCHO%d(PBMA): Cannot register PciERR interrupt.\n",
1033 irq
= psycho_irq_build(p
, NULL
, (portid
<< 6) | PSYCHO_PCIERR_B_INO
);
1034 if (request_irq(irq
, psycho_pcierr_intr
,
1035 SA_SHIRQ
, "PSYCHO PCIERR", &p
->pbm_B
) < 0) {
1036 prom_printf("PSYCHO%d(PBMB): Cannot register PciERR interrupt.\n",
1041 /* Enable UE and CE interrupts for controller. */
1042 psycho_write(base
+ PSYCHO_ECC_CTRL
,
1043 (PSYCHO_ECCCTRL_EE
|
1045 PSYCHO_ECCCTRL_CE
));
1047 /* Enable PCI Error interrupts and clear error
1048 * bits for each PBM.
1050 tmp
= psycho_read(base
+ PSYCHO_PCIA_CTRL
);
1051 tmp
|= (PSYCHO_PCICTRL_SBH_ERR
|
1052 PSYCHO_PCICTRL_SERR
|
1053 PSYCHO_PCICTRL_SBH_INT
|
1054 PSYCHO_PCICTRL_EEN
);
1055 psycho_write(base
+ PSYCHO_PCIA_CTRL
, tmp
);
1057 tmp
= psycho_read(base
+ PSYCHO_PCIB_CTRL
);
1058 tmp
|= (PSYCHO_PCICTRL_SBH_ERR
|
1059 PSYCHO_PCICTRL_SERR
|
1060 PSYCHO_PCICTRL_SBH_INT
|
1061 PSYCHO_PCICTRL_EEN
);
1062 psycho_write(base
+ PSYCHO_PCIB_CTRL
, tmp
);
1065 /* PSYCHO boot time probing and initialization. */
1066 static void __init
psycho_resource_adjust(struct pci_dev
*pdev
,
1067 struct resource
*res
,
1068 struct resource
*root
)
1070 res
->start
+= root
->start
;
1071 res
->end
+= root
->start
;
1074 static void __init
psycho_base_address_update(struct pci_dev
*pdev
, int resource
)
1076 struct pcidev_cookie
*pcp
= pdev
->sysdata
;
1077 struct pci_pbm_info
*pbm
= pcp
->pbm
;
1078 struct resource
*res
, *root
;
1080 int where
, size
, is_64bit
;
1082 res
= &pdev
->resource
[resource
];
1083 where
= PCI_BASE_ADDRESS_0
+ (resource
* 4);
1086 if (res
->flags
& IORESOURCE_IO
)
1087 root
= &pbm
->io_space
;
1089 root
= &pbm
->mem_space
;
1090 if ((res
->flags
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
)
1091 == PCI_BASE_ADDRESS_MEM_TYPE_64
)
1095 size
= res
->end
- res
->start
;
1096 pci_read_config_dword(pdev
, where
, ®
);
1097 reg
= ((reg
& size
) |
1098 (((u32
)(res
->start
- root
->start
)) & ~size
));
1099 pci_write_config_dword(pdev
, where
, reg
);
1101 /* This knows that the upper 32-bits of the address
1102 * must be zero. Our PCI common layer enforces this.
1105 pci_write_config_dword(pdev
, where
+ 4, 0);
1108 /* We have to do the config space accesses by hand, thus... */
1109 #define PBM_BRIDGE_BUS 0x40
1110 #define PBM_BRIDGE_SUBORDINATE 0x41
1111 static void __init
pbm_renumber(struct pci_pbm_info
*pbm
, u8 orig_busno
)
1116 busno
= pci_highest_busnum
;
1117 nbus
= pbm
->pci_last_busno
- pbm
->pci_first_busno
;
1119 addr
= psycho_pci_config_mkaddr(pbm
, orig_busno
,
1121 pci_config_write8(addr
, busno
);
1122 addr
= psycho_pci_config_mkaddr(pbm
, busno
,
1123 0, PBM_BRIDGE_SUBORDINATE
);
1124 pci_config_write8(addr
, busno
+ nbus
);
1126 pbm
->pci_first_busno
= busno
;
1127 pbm
->pci_last_busno
= busno
+ nbus
;
1128 pci_highest_busnum
= busno
+ nbus
+ 1;
1131 pci_bus2pbm
[busno
++] = pbm
;
1135 /* We have to do the config space accesses by hand here since
1136 * the pci_bus2pbm array is not ready yet.
1138 static void __init
pbm_pci_bridge_renumber(struct pci_pbm_info
*pbm
,
1141 u32 devfn
, l
, class;
1145 for(devfn
= 0; devfn
< 0xff; ++devfn
) {
1149 if (PCI_FUNC(devfn
) != 0 && is_multi
== 0)
1152 /* Anything there? */
1153 dwaddr
= psycho_pci_config_mkaddr(pbm
, busno
, devfn
, PCI_VENDOR_ID
);
1155 pci_config_read32(dwaddr
, &l
);
1156 if (l
== 0xffffffff || l
== 0x00000000 ||
1157 l
== 0x0000ffff || l
== 0xffff0000) {
1162 baddr
= psycho_pci_config_mkaddr(pbm
, busno
, devfn
, PCI_HEADER_TYPE
);
1163 pci_config_read8(baddr
, &hdr_type
);
1164 if (PCI_FUNC(devfn
) == 0)
1165 is_multi
= hdr_type
& 0x80;
1167 dwaddr
= psycho_pci_config_mkaddr(pbm
, busno
, devfn
, PCI_CLASS_REVISION
);
1169 pci_config_read32(dwaddr
, &class);
1170 if ((class >> 16) == PCI_CLASS_BRIDGE_PCI
) {
1171 u32 buses
= 0xffffffff;
1173 dwaddr
= psycho_pci_config_mkaddr(pbm
, busno
, devfn
,
1175 pci_config_read32(dwaddr
, &buses
);
1176 pbm_pci_bridge_renumber(pbm
, (buses
>> 8) & 0xff);
1177 buses
&= 0xff000000;
1178 pci_config_write32(dwaddr
, buses
);
1183 static void __init
pbm_bridge_reconfigure(struct pci_controller_info
*p
)
1185 struct pci_pbm_info
*pbm
;
1188 /* Clear out primary/secondary/subordinate bus numbers on
1189 * all PCI-to-PCI bridges under each PBM. The generic bus
1190 * probing will fix them up.
1192 pbm_pci_bridge_renumber(&p
->pbm_B
, p
->pbm_B
.pci_first_busno
);
1193 pbm_pci_bridge_renumber(&p
->pbm_A
, p
->pbm_A
.pci_first_busno
);
1195 /* Move PBM A out of the way. */
1197 addr
= psycho_pci_config_mkaddr(pbm
, pbm
->pci_first_busno
,
1199 pci_config_write8(addr
, 0xff);
1200 addr
= psycho_pci_config_mkaddr(pbm
, 0xff,
1201 0, PBM_BRIDGE_SUBORDINATE
);
1202 pci_config_write8(addr
, 0xff);
1204 /* Now we can safely renumber both PBMs. */
1205 pbm_renumber(&p
->pbm_B
, p
->pbm_B
.pci_first_busno
);
1206 pbm_renumber(&p
->pbm_A
, 0xff);
1209 static void __init
pbm_config_busmastering(struct pci_pbm_info
*pbm
)
1213 /* Set cache-line size to 64 bytes, this is actually
1214 * a nop but I do it for completeness.
1216 addr
= psycho_pci_config_mkaddr(pbm
, pbm
->pci_first_busno
,
1217 0, PCI_CACHE_LINE_SIZE
);
1218 pci_config_write8(addr
, 64 / sizeof(u32
));
1220 /* Set PBM latency timer to 64 PCI clocks. */
1221 addr
= psycho_pci_config_mkaddr(pbm
, pbm
->pci_first_busno
,
1222 0, PCI_LATENCY_TIMER
);
1223 pci_config_write8(addr
, 64);
1226 static void __init
pbm_scan_bus(struct pci_controller_info
*p
,
1227 struct pci_pbm_info
*pbm
)
1229 pbm
->pci_bus
= pci_scan_bus(pbm
->pci_first_busno
,
1232 pci_fill_in_pbm_cookies(pbm
->pci_bus
, pbm
, pbm
->prom_node
);
1233 pci_record_assignments(pbm
, pbm
->pci_bus
);
1234 pci_assign_unassigned(pbm
, pbm
->pci_bus
);
1235 pci_fixup_irq(pbm
, pbm
->pci_bus
);
1236 pci_determine_66mhz_disposition(pbm
, pbm
->pci_bus
);
1237 pci_setup_busmastering(pbm
, pbm
->pci_bus
);
1240 static void __init
psycho_scan_bus(struct pci_controller_info
*p
)
1242 pbm_bridge_reconfigure(p
);
1243 pbm_config_busmastering(&p
->pbm_B
);
1244 p
->pbm_B
.is_66mhz_capable
= 0;
1245 pbm_config_busmastering(&p
->pbm_A
);
1246 p
->pbm_A
.is_66mhz_capable
= 1;
1247 pbm_scan_bus(p
, &p
->pbm_B
);
1248 pbm_scan_bus(p
, &p
->pbm_A
);
1250 /* After the PCI bus scan is complete, we can register
1251 * the error interrupt handlers.
1253 psycho_register_error_handlers(p
);
1256 static void __init
psycho_iommu_init(struct pci_controller_info
*p
)
1258 unsigned long tsbbase
, i
;
1261 /* Setup initial software IOMMU state. */
1262 spin_lock_init(&p
->iommu
.lock
);
1263 p
->iommu
.iommu_cur_ctx
= 0;
1265 /* Register addresses. */
1266 p
->iommu
.iommu_control
= p
->controller_regs
+ PSYCHO_IOMMU_CONTROL
;
1267 p
->iommu
.iommu_tsbbase
= p
->controller_regs
+ PSYCHO_IOMMU_TSBBASE
;
1268 p
->iommu
.iommu_flush
= p
->controller_regs
+ PSYCHO_IOMMU_FLUSH
;
1269 /* PSYCHO's IOMMU lacks ctx flushing. */
1270 p
->iommu
.iommu_ctxflush
= 0;
1272 /* We use the main control register of PSYCHO as the write
1273 * completion register.
1275 p
->iommu
.write_complete_reg
= p
->controller_regs
+ PSYCHO_CONTROL
;
1278 * Invalidate TLB Entries.
1280 control
= psycho_read(p
->controller_regs
+ PSYCHO_IOMMU_CONTROL
);
1281 control
|= PSYCHO_IOMMU_CTRL_DENAB
;
1282 psycho_write(p
->controller_regs
+ PSYCHO_IOMMU_CONTROL
, control
);
1283 for(i
= 0; i
< 16; i
++) {
1284 psycho_write(p
->controller_regs
+ PSYCHO_IOMMU_TAG
+ (i
* 8UL), 0);
1285 psycho_write(p
->controller_regs
+ PSYCHO_IOMMU_DATA
+ (i
* 8UL), 0);
1288 /* Leave diag mode enabled for full-flushing done
1292 /* Using assumed page size 8K with 128K entries we need 1MB iommu page
1293 * table (128K ioptes * 8 bytes per iopte). This is
1294 * page order 7 on UltraSparc.
1296 tsbbase
= __get_free_pages(GFP_KERNEL
, 7);
1298 prom_printf("PSYCHO_IOMMU: Error, gfp(tsb) failed.\n");
1301 p
->iommu
.page_table
= (iopte_t
*)tsbbase
;
1302 p
->iommu
.page_table_sz_bits
= 17;
1303 p
->iommu
.page_table_map_base
= 0xc0000000;
1304 p
->iommu
.dma_addr_mask
= 0xffffffff;
1305 memset((char *)tsbbase
, 0, PAGE_SIZE
<< 7);
1307 /* We start with no consistent mappings. */
1308 p
->iommu
.lowest_consistent_map
=
1309 1 << (p
->iommu
.page_table_sz_bits
- PBM_LOGCLUSTERS
);
1311 for (i
= 0; i
< PBM_NCLUSTERS
; i
++) {
1312 p
->iommu
.alloc_info
[i
].flush
= 0;
1313 p
->iommu
.alloc_info
[i
].next
= 0;
1316 psycho_write(p
->controller_regs
+ PSYCHO_IOMMU_TSBBASE
, __pa(tsbbase
));
1318 control
= psycho_read(p
->controller_regs
+ PSYCHO_IOMMU_CONTROL
);
1319 control
&= ~(PSYCHO_IOMMU_CTRL_TSBSZ
| PSYCHO_IOMMU_CTRL_TBWSZ
);
1320 control
|= (PSYCHO_IOMMU_TSBSZ_128K
| PSYCHO_IOMMU_CTRL_ENAB
);
1321 psycho_write(p
->controller_regs
+ PSYCHO_IOMMU_CONTROL
, control
);
1323 /* If necessary, hook us up for starfire IRQ translations. */
1324 if(this_is_starfire
)
1325 p
->starfire_cookie
= starfire_hookup(p
->portid
);
1327 p
->starfire_cookie
= NULL
;
1330 #define PSYCHO_IRQ_RETRY 0x1a00UL
1331 #define PSYCHO_PCIA_DIAG 0x2020UL
1332 #define PSYCHO_PCIB_DIAG 0x4020UL
1333 #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80 /* Reserved */
1334 #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040 /* Disable retry limit */
1335 #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020 /* Disable DMA wr / irq sync */
1336 #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010 /* Disable DMA wr / PIO rd sync */
1337 #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008 /* Invert DMA data parity */
1338 #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004 /* Invert PIO data parity */
1339 #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002 /* Invert PIO address parity */
1340 #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001 /* Enable loopback mode */
1342 static void psycho_controller_hwinit(struct pci_controller_info
*p
)
1346 /* PROM sets the IRQ retry value too low, increase it. */
1347 psycho_write(p
->controller_regs
+ PSYCHO_IRQ_RETRY
, 0xff);
1349 /* Enable arbiter for all PCI slots. */
1350 tmp
= psycho_read(p
->controller_regs
+ PSYCHO_PCIA_CTRL
);
1351 tmp
|= PSYCHO_PCICTRL_AEN
;
1352 psycho_write(p
->controller_regs
+ PSYCHO_PCIA_CTRL
, tmp
);
1354 tmp
= psycho_read(p
->controller_regs
+ PSYCHO_PCIB_CTRL
);
1355 tmp
|= PSYCHO_PCICTRL_AEN
;
1356 psycho_write(p
->controller_regs
+ PSYCHO_PCIB_CTRL
, tmp
);
1358 /* Disable DMA write / PIO read synchronization on
1359 * both PCI bus segments.
1360 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
1362 tmp
= psycho_read(p
->controller_regs
+ PSYCHO_PCIA_DIAG
);
1363 tmp
|= PSYCHO_PCIDIAG_DDWSYNC
;
1364 psycho_write(p
->controller_regs
+ PSYCHO_PCIA_DIAG
, tmp
);
1366 tmp
= psycho_read(p
->controller_regs
+ PSYCHO_PCIB_DIAG
);
1367 tmp
|= PSYCHO_PCIDIAG_DDWSYNC
;
1368 psycho_write(p
->controller_regs
+ PSYCHO_PCIB_DIAG
, tmp
);
1371 static void __init
pbm_register_toplevel_resources(struct pci_controller_info
*p
,
1372 struct pci_pbm_info
*pbm
)
1374 char *name
= pbm
->name
;
1376 sprintf(name
, "PSYCHO%d PBM%c",
1378 (pbm
== &p
->pbm_A
? 'A' : 'B'));
1379 pbm
->io_space
.name
= pbm
->mem_space
.name
= name
;
1381 request_resource(&ioport_resource
, &pbm
->io_space
);
1382 request_resource(&iomem_resource
, &pbm
->mem_space
);
1385 static void psycho_pbm_strbuf_init(struct pci_controller_info
*p
,
1386 struct pci_pbm_info
*pbm
,
1389 unsigned long base
= p
->controller_regs
;
1393 pbm
->stc
.strbuf_control
= base
+ PSYCHO_STRBUF_CONTROL_A
;
1394 pbm
->stc
.strbuf_pflush
= base
+ PSYCHO_STRBUF_FLUSH_A
;
1395 pbm
->stc
.strbuf_fsync
= base
+ PSYCHO_STRBUF_FSYNC_A
;
1397 pbm
->stc
.strbuf_control
= base
+ PSYCHO_STRBUF_CONTROL_B
;
1398 pbm
->stc
.strbuf_pflush
= base
+ PSYCHO_STRBUF_FLUSH_B
;
1399 pbm
->stc
.strbuf_fsync
= base
+ PSYCHO_STRBUF_FSYNC_B
;
1401 /* PSYCHO's streaming buffer lacks ctx flushing. */
1402 pbm
->stc
.strbuf_ctxflush
= 0;
1403 pbm
->stc
.strbuf_ctxmatch_base
= 0;
1405 pbm
->stc
.strbuf_flushflag
= (volatile unsigned long *)
1406 ((((unsigned long)&pbm
->stc
.__flushflag_buf
[0])
1409 pbm
->stc
.strbuf_flushflag_pa
= (unsigned long)
1410 __pa(pbm
->stc
.strbuf_flushflag
);
1412 /* Enable the streaming buffer. We have to be careful
1413 * just in case OBP left it with LRU locking enabled.
1415 * It is possible to control if PBM will be rerun on
1416 * line misses. Currently I just retain whatever setting
1417 * OBP left us with. All checks so far show it having
1420 #undef PSYCHO_STRBUF_RERUN_ENABLE
1421 #undef PSYCHO_STRBUF_RERUN_DISABLE
1422 control
= psycho_read(pbm
->stc
.strbuf_control
);
1423 control
|= PSYCHO_STRBUF_CTRL_ENAB
;
1424 control
&= ~(PSYCHO_STRBUF_CTRL_LENAB
| PSYCHO_STRBUF_CTRL_LPTR
);
1425 #ifdef PSYCHO_STRBUF_RERUN_ENABLE
1426 control
&= ~(PSYCHO_STRBUF_CTRL_RRDIS
);
1428 #ifdef PSYCHO_STRBUF_RERUN_DISABLE
1429 control
|= PSYCHO_STRBUF_CTRL_RRDIS
;
1432 psycho_write(pbm
->stc
.strbuf_control
, control
);
1434 pbm
->stc
.strbuf_enabled
= 1;
1437 #define PSYCHO_IOSPACE_A 0x002000000UL
1438 #define PSYCHO_IOSPACE_B 0x002010000UL
1439 #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
1440 #define PSYCHO_MEMSPACE_A 0x100000000UL
1441 #define PSYCHO_MEMSPACE_B 0x180000000UL
1442 #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
1444 static void psycho_pbm_init(struct pci_controller_info
*p
,
1445 int prom_node
, int is_pbm_a
)
1447 unsigned int busrange
[2];
1448 struct pci_pbm_info
*pbm
;
1453 pbm
->io_space
.start
= p
->controller_regs
+ PSYCHO_IOSPACE_A
;
1454 pbm
->mem_space
.start
= p
->controller_regs
+ PSYCHO_MEMSPACE_A
;
1457 pbm
->io_space
.start
= p
->controller_regs
+ PSYCHO_IOSPACE_B
;
1458 pbm
->mem_space
.start
= p
->controller_regs
+ PSYCHO_MEMSPACE_B
;
1460 pbm
->io_space
.end
= pbm
->io_space
.start
+ PSYCHO_IOSPACE_SIZE
;
1461 pbm
->io_space
.flags
= IORESOURCE_IO
;
1462 pbm
->mem_space
.end
= pbm
->mem_space
.start
+ PSYCHO_MEMSPACE_SIZE
;
1463 pbm
->mem_space
.flags
= IORESOURCE_MEM
;
1464 pbm_register_toplevel_resources(p
, pbm
);
1467 pbm
->prom_node
= prom_node
;
1468 prom_getstring(prom_node
, "name",
1470 sizeof(pbm
->prom_name
));
1472 err
= prom_getproperty(prom_node
, "ranges",
1473 (char *)pbm
->pbm_ranges
,
1474 sizeof(pbm
->pbm_ranges
));
1476 pbm
->num_pbm_ranges
=
1477 (err
/ sizeof(struct linux_prom_pci_ranges
));
1479 pbm
->num_pbm_ranges
= 0;
1481 err
= prom_getproperty(prom_node
, "interrupt-map",
1482 (char *)pbm
->pbm_intmap
,
1483 sizeof(pbm
->pbm_intmap
));
1485 pbm
->num_pbm_intmap
= (err
/ sizeof(struct linux_prom_pci_intmap
));
1486 err
= prom_getproperty(prom_node
, "interrupt-map-mask",
1487 (char *)&pbm
->pbm_intmask
,
1488 sizeof(pbm
->pbm_intmask
));
1490 prom_printf("PSYCHO-PBM: Fatal error, no "
1491 "interrupt-map-mask.\n");
1495 pbm
->num_pbm_intmap
= 0;
1496 memset(&pbm
->pbm_intmask
, 0, sizeof(pbm
->pbm_intmask
));
1499 err
= prom_getproperty(prom_node
, "bus-range",
1500 (char *)&busrange
[0],
1502 if (err
== 0 || err
== -1) {
1503 prom_printf("PSYCHO-PBM: Fatal error, no bus-range.\n");
1506 pbm
->pci_first_busno
= busrange
[0];
1507 pbm
->pci_last_busno
= busrange
[1];
1509 psycho_pbm_strbuf_init(p
, pbm
, is_pbm_a
);
1512 #define PSYCHO_CONFIGSPACE 0x001000000UL
1514 void __init
psycho_init(int node
)
1516 struct linux_prom64_registers pr_regs
[3];
1517 struct pci_controller_info
*p
;
1518 unsigned long flags
;
1522 upa_portid
= prom_getintdefault(node
, "upa-portid", 0xff);
1524 spin_lock_irqsave(&pci_controller_lock
, flags
);
1525 for(p
= pci_controller_root
; p
; p
= p
->next
) {
1526 if (p
->portid
== upa_portid
) {
1527 spin_unlock_irqrestore(&pci_controller_lock
, flags
);
1528 is_pbm_a
= (p
->pbm_A
.prom_node
== 0);
1529 psycho_pbm_init(p
, node
, is_pbm_a
);
1533 spin_unlock_irqrestore(&pci_controller_lock
, flags
);
1535 p
= kmalloc(sizeof(struct pci_controller_info
), GFP_ATOMIC
);
1537 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1540 memset(p
, 0, sizeof(*p
));
1542 spin_lock_irqsave(&pci_controller_lock
, flags
);
1543 p
->next
= pci_controller_root
;
1544 pci_controller_root
= p
;
1545 spin_unlock_irqrestore(&pci_controller_lock
, flags
);
1547 p
->portid
= upa_portid
;
1548 p
->index
= pci_num_controllers
++;
1549 p
->scan_bus
= psycho_scan_bus
;
1550 p
->irq_build
= psycho_irq_build
;
1551 p
->base_address_update
= psycho_base_address_update
;
1552 p
->resource_adjust
= psycho_resource_adjust
;
1553 p
->pci_ops
= &psycho_ops
;
1555 err
= prom_getproperty(node
, "reg",
1556 (char *)&pr_regs
[0],
1558 if (err
== 0 || err
== -1) {
1559 prom_printf("PSYCHO: Fatal error, no reg property.\n");
1563 p
->controller_regs
= pr_regs
[2].phys_addr
;
1564 printk("PCI: Found PSYCHO, control regs at %016lx\n",
1565 p
->controller_regs
);
1567 p
->config_space
= pr_regs
[2].phys_addr
+ PSYCHO_CONFIGSPACE
;
1568 printk("PSYCHO: PCI config space at %016lx\n", p
->config_space
);
1571 * Psycho's PCI MEM space is mapped to a 2GB aligned area, so
1572 * we need to adjust our MEM space mask.
1574 pci_memspace_mask
= 0x7fffffffUL
;
1576 psycho_controller_hwinit(p
);
1578 psycho_iommu_init(p
);
1580 is_pbm_a
= ((pr_regs
[0].phys_addr
& 0x6000) == 0x2000);
1581 psycho_pbm_init(p
, node
, is_pbm_a
);