arch/i386/kernel/visws_apic.c

   1 /*
   2  *      linux/arch/i386/kernel/visws_apic.c
   3  *
   4  *      Copyright (C) 1999 Bent Hagemark, Ingo Molnar
   5  *
   6  *  SGI Visual Workstation interrupt controller
   7  *
   8  *  The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
   9  *  which serves as the main interrupt controller in the system.  Non-legacy
  10  *  hardware in the system uses this controller directly.  Legacy devices
  11  *  are connected to the PIIX4 which in turn has its 8259(s) connected to
  12  *  a of the Cobalt APIC entry.
  13  */
  14
  15 #include <linux/ptrace.h>
  16 #include <linux/errno.h>
  17 #include <linux/kernel_stat.h>
  18 #include <linux/signal.h>
  19 #include <linux/sched.h>
  20 #include <linux/ioport.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/timex.h>
  23 #include <linux/malloc.h>
  24 #include <linux/random.h>
  25 #include <linux/smp.h>
  26 #include <linux/smp_lock.h>
  27 #include <linux/init.h>
  28
  29 #include <asm/system.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <asm/bitops.h>
  33 #include <asm/smp.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/delay.h>
  36 #include <asm/desc.h>
  37
  38 #include <asm/cobalt.h>
  39
  40 #include "irq.h"
  41
  42 /*
  43  * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
  44  * -- not the manner expected by the normal 8259 code in irq.c.
  45  *
  46  * there is a 'master' physical interrupt source that gets sent to
  47  * the CPU. But in the chipset there are various 'virtual' interrupts
  48  * waiting to be handled. We represent this to Linux through a 'master'
  49  * interrupt controller type, and through a special virtual interrupt-
  50  * controller. Device drivers only see the virtual interrupt sources.
  51  */
  52
  53 #define CO_IRQ_BASE     0x20    /* This is the 0x20 in init_IRQ()! */
  54
  55 static void startup_piix4_master_irq(unsigned int irq);
  56 static void shutdown_piix4_master_irq(unsigned int irq);
  57 static void do_piix4_master_IRQ(unsigned int irq, struct pt_regs * regs);
  58 #define enable_piix4_master_irq startup_piix4_master_irq
  59 #define disable_piix4_master_irq shutdown_piix4_master_irq
  60
  61 static struct hw_interrupt_type piix4_master_irq_type = {
  62         "PIIX4-master",
  63         startup_piix4_master_irq,
  64         shutdown_piix4_master_irq,
  65         do_piix4_master_IRQ,
  66         enable_piix4_master_irq,
  67         disable_piix4_master_irq
  68 };
  69
  70 static void enable_piix4_virtual_irq(unsigned int irq);
  71 static void disable_piix4_virtual_irq(unsigned int irq);
  72 #define startup_piix4_virtual_irq enable_piix4_virtual_irq
  73 #define shutdown_piix4_virtual_irq disable_piix4_virtual_irq
  74
  75 static struct hw_interrupt_type piix4_virtual_irq_type = {
  76         "PIIX4-virtual",
  77         startup_piix4_virtual_irq,
  78         shutdown_piix4_virtual_irq,
  79         0, /* no handler, it's never called physically */
  80         enable_piix4_virtual_irq,
  81         disable_piix4_virtual_irq
  82 };
  83
  84 /*
  85  * This is the SGI Cobalt (IO-)APIC:
  86  */
  87
  88 static void do_cobalt_IRQ(unsigned int irq, struct pt_regs * regs);
  89 static void enable_cobalt_irq(unsigned int irq);
  90 static void disable_cobalt_irq(unsigned int irq);
  91 static void startup_cobalt_irq(unsigned int irq);
  92 #define shutdown_cobalt_irq disable_cobalt_irq
  93
  94 static struct hw_interrupt_type cobalt_irq_type = {
  95         "Cobalt-APIC",
  96         startup_cobalt_irq,
  97         shutdown_cobalt_irq,
  98         do_cobalt_IRQ,
  99         enable_cobalt_irq,
 100         disable_cobalt_irq
 101 };
 102
 103
 104 /*
 105  * Not an initfunc, needed by the reboot code
 106  */
 107 void init_pic_mode(void)
 108 {
 109         /* Nop on Cobalt */
 110 }
 111
 112 /*
 113  * Cobalt (IO)-APIC functions to handle PCI devices.
 114  */
 115
 116 static void disable_cobalt_irq(unsigned int irq)
 117 {
 118         /* XXX undo the APIC entry here? */
 119
 120         /*
 121          * definitely, we do not want to have IRQ storms from
 122          * unused devices --mingo
 123          */
 124 }
 125
 126 static void enable_cobalt_irq(unsigned int irq)
 127 {
 128 }
 129
 130 /*
 131  * Set the given Cobalt APIC Redirection Table entry to point
 132  * to the given IDT vector/index.
 133  */
 134 static void co_apic_set(int entry, int idtvec)
 135 {
 136         co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (CO_IRQ_BASE+idtvec));
 137         co_apic_write(CO_APIC_HI(entry), 0);
 138
 139         printk("Cobalt APIC Entry %d IDT Vector %d\n", entry, idtvec);
 140 }
 141
 142 /*
 143  * "irq" really just serves to identify the device.  Here is where we
 144  * map this to the Cobalt APIC entry where it's physically wired.
 145  * This is called via request_irq -> setup_x86_irq -> irq_desc->startup()
 146  */
 147 static void startup_cobalt_irq(unsigned int irq)
 148 {
 149         /*
 150          * These "irq"'s are wired to the same Cobalt APIC entries
 151          * for all (known) motherboard types/revs
 152          */
 153         switch (irq) {
 154         case CO_IRQ_TIMER:      co_apic_set(CO_APIC_CPU, CO_IRQ_TIMER);
 155                                 return;
 156
 157         case CO_IRQ_ENET:       co_apic_set(CO_APIC_ENET, CO_IRQ_ENET);
 158                                 return;
 159
 160         case CO_IRQ_SERIAL:     return; /* XXX move to piix4-8259 "virtual" */
 161
 162         case CO_IRQ_8259:       co_apic_set(CO_APIC_8259, CO_IRQ_8259);
 163                                 return;
 164
 165         case CO_IRQ_IDE:
 166                 switch (visws_board_type) {
 167                 case VISWS_320:
 168                         switch (visws_board_rev) {
 169                         case 5:
 170                                 co_apic_set(CO_APIC_0_5_IDE0, CO_IRQ_IDE);
 171                                 co_apic_set(CO_APIC_0_5_IDE1, CO_IRQ_IDE);
 172                                         return;
 173                         case 6:
 174                                 co_apic_set(CO_APIC_0_6_IDE0, CO_IRQ_IDE);
 175                                 co_apic_set(CO_APIC_0_6_IDE1, CO_IRQ_IDE);
 176                                         return;
 177                         }
 178                 case VISWS_540:
 179                         switch (visws_board_rev) {
 180                         case 2:
 181                                 co_apic_set(CO_APIC_1_2_IDE0, CO_IRQ_IDE);
 182                                         return;
 183                         }
 184                 }
 185                 break;
 186         default:
 187                 panic("huh?");
 188         }
 189 }
 190
 191 /*
 192  * This is the handle() op in do_IRQ()
 193  */
 194 static void do_cobalt_IRQ(unsigned int irq, struct pt_regs * regs)
 195 {
 196         struct irqaction * action;
 197         irq_desc_t *desc = irq_desc + irq;
 198
 199         spin_lock(&irq_controller_lock);
 200         {
 201                 unsigned int status;
 202                 /* XXX APIC EOI? */
 203                 status = desc->status & ~(IRQ_REPLAY | IRQ_WAITING);
 204                 action = NULL;
 205                 if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 206                         action = desc->action;
 207                         status |= IRQ_INPROGRESS;
 208                 }
 209                 desc->status = status;
 210         }
 211         spin_unlock(&irq_controller_lock);
 212
 213         /* Exit early if we had no action or it was disabled */
 214         if (!action)
 215                 return;
 216
 217         handle_IRQ_event(irq, regs, action);
 218
 219         (void)co_cpu_read(CO_CPU_REV); /* Sync driver ack to its h/w */
 220         apic_write(APIC_EOI, APIC_EIO_ACK); /* Send EOI to Cobalt APIC */
 221
 222         spin_lock(&irq_controller_lock);
 223         {
 224                 unsigned int status = desc->status & ~IRQ_INPROGRESS;
 225                 desc->status = status;
 226                 if (!(status & IRQ_DISABLED))
 227                         enable_cobalt_irq(irq);
 228         }
 229         spin_unlock(&irq_controller_lock);
 230 }
 231
 232 /*
 233  * PIIX4-8259 master/virtual functions to handle:
 234  *
 235  *      floppy
 236  *      parallel
 237  *      serial
 238  *      audio (?)
 239  *
 240  * None of these get Cobalt APIC entries, neither do they have IDT
 241  * entries. These interrupts are purely virtual and distributed from
 242  * the 'master' interrupt source: CO_IRQ_8259.
 243  *
 244  * When the 8259 interrupts its handler figures out which of these
 245  * devices is interrupting and dispatches to it's handler.
 246  *
 247  * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
 248  * enable_irq gets the right irq. This 'master' irq is never directly
 249  * manipulated by any driver.
 250  */
 251
 252 static void startup_piix4_master_irq(unsigned int irq)
 253 {
 254         /* ICW1 */
 255         outb(0x11, 0x20);
 256         outb(0x11, 0xa0);
 257
 258         /* ICW2 */
 259         outb(0x08, 0x21);
 260         outb(0x70, 0xa1);
 261
 262         /* ICW3 */
 263         outb(0x04, 0x21);
 264         outb(0x02, 0xa1);
 265
 266         /* ICW4 */
 267         outb(0x01, 0x21);
 268         outb(0x01, 0xa1);
 269
 270         /* OCW1 - disable all interrupts in both 8259's */
 271         outb(0xff, 0x21);
 272         outb(0xff, 0xa1);
 273
 274         startup_cobalt_irq(irq);
 275 }
 276
 277 static void shutdown_piix4_master_irq(unsigned int irq)
 278 {
 279         /*
 280          * [we skip the 8259 magic here, not strictly necessary]
 281          */
 282
 283         shutdown_cobalt_irq(irq);
 284 }
 285
 286 static void do_piix4_master_IRQ(unsigned int irq, struct pt_regs * regs)
 287 {
 288         int realirq, mask;
 289
 290         /* Find out what's interrupting in the PIIX4 8259 */
 291
 292         spin_lock(&irq_controller_lock);
 293         outb(0x0c, 0x20);               /* OCW3 Poll command */
 294         realirq = inb(0x20);
 295
 296         if (!(realirq & 0x80)) {
 297                 /*
 298                  * Bit 7 == 0 means invalid/spurious
 299                  */
 300                 goto out_unlock;
 301         }
 302         realirq &= 0x7f;
 303
 304         /*
 305          * mask and ack the 8259
 306          */
 307         mask = inb(0x21);
 308         if ((mask >> realirq) & 0x01)
 309                 /*
 310                  * This IRQ is masked... ignore
 311                  */
 312                 goto out_unlock;
 313
 314         outb(mask | (1<<realirq), 0x21);
 315         /*
 316          * OCW2 - non-specific EOI
 317          */
 318         outb(0x20, 0x20);
 319
 320         spin_unlock(&irq_controller_lock);
 321
 322         /*
 323          * handle this 'virtual interrupt' as a Cobalt one now.
 324          */
 325         kstat.irqs[smp_processor_id()][irq]++;
 326         do_cobalt_IRQ(realirq, regs);
 327
 328         spin_lock(&irq_controller_lock);
 329         {
 330                 irq_desc_t *desc = irq_desc + realirq;
 331
 332                 if (!(desc->status & IRQ_DISABLED))
 333                         enable_piix4_virtual_irq(realirq);
 334         }
 335         spin_unlock(&irq_controller_lock);
 336         return;
 337
 338 out_unlock:
 339         spin_unlock(&irq_controller_lock);
 340         return;
 341 }
 342
 343 static void enable_piix4_virtual_irq(unsigned int irq)
 344 {
 345         /*
 346          * assumes this irq is one of the legacy devices
 347          */
 348
 349         unsigned int mask = inb(0x21);
 350         mask &= ~(1 << irq);
 351         outb(mask, 0x21);
 352         enable_cobalt_irq(irq);
 353 }
 354
 355 /*
 356  * assumes this irq is one of the legacy devices
 357  */
 358 static void disable_piix4_virtual_irq(unsigned int irq)
 359 {
 360         unsigned int mask;
 361
 362         disable_cobalt_irq(irq);
 363
 364         mask = inb(0x21);
 365         mask &= ~(1 << irq);
 366         outb(mask, 0x21);
 367 }
 368
 369 static struct irqaction master_action =
 370                 { no_action, 0, 0, "PIIX4-8259", NULL, NULL };
 371
 372 void init_VISWS_APIC_irqs(void)
 373 {
 374         int i;
 375
 376         for (i = 0; i < 16; i++) {
 377                 irq_desc[i].status = IRQ_DISABLED;
 378                 irq_desc[i].action = 0;
 379                 irq_desc[i].depth = 0;
 380
 381                 /*
 382                  * Cobalt IRQs are mapped to standard ISA
 383                  * interrupt vectors:
 384                  */
 385                 switch (i) {
 386                         /*
 387                          * Only CO_IRQ_8259 will be raised
 388                          * externally.
 389                          */
 390                 case CO_IRQ_8259:
 391                         irq_desc[i].handler = &piix4_master_irq_type;
 392                         break;
 393                 case CO_IRQ_FLOPPY:
 394                 case CO_IRQ_PARLL:
 395                         irq_desc[i].handler = &piix4_virtual_irq_type;
 396                         break;
 397                 default:
 398                         irq_desc[i].handler = &cobalt_irq_type;
 399                         break;
 400                 }
 401         }
 402
 403         /*
 404          * The master interrupt is always present:
 405          */
 406         setup_x86_irq(CO_IRQ_8259, &master_action);
 407 }
 408