2 * linux/arch/i386/kernel/time.c
4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
6 * This file contains the PC-specific time handling details:
7 * reading the RTC at bootup, etc..
8 * 1994-07-02 Alan Modra
9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
10 * 1995-03-26 Markus Kuhn
11 * fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
12 * precision CMOS clock update
13 * 1996-05-03 Ingo Molnar
14 * fixed time warps in do_[slow|fast]_gettimeoffset()
15 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
16 * "A Kernel Model for Precision Timekeeping" by Dave Mills
17 * 1998-09-05 (Various)
18 * More robust do_fast_gettimeoffset() algorithm implemented
19 * (works with APM, Cyrix 6x86MX and Centaur C6),
20 * monotonic gettimeofday() with fast_get_timeoffset(),
21 * drift-proof precision TSC calibration on boot
22 * (C. Scott Ananian <cananian@alumni.princeton.edu>, Andrew D.
23 * Balsa <andrebalsa@altern.org>, Philip Gladstone <philip@raptor.com>;
24 * ported from 2.0.35 Jumbo-9 by Michael Krause <m.krause@tu-harburg.de>).
25 * 1998-12-16 Andrea Arcangeli
26 * Fixed Jumbo-9 code in 2.1.131: do_gettimeofday was missing 1 jiffy
27 * because was not accounting lost_ticks.
28 * 1998-12-24 Copyright (C) 1998 Andrea Arcangeli
29 * Fixed a xtime SMP race (we need the xtime_lock rw spinlock to
30 * serialize accesses to xtime/lost_ticks).
33 #include <linux/errno.h>
34 #include <linux/sched.h>
35 #include <linux/kernel.h>
36 #include <linux/param.h>
37 #include <linux/string.h>
39 #include <linux/interrupt.h>
40 #include <linux/time.h>
41 #include <linux/delay.h>
42 #include <linux/init.h>
43 #include <linux/smp.h>
45 #include <asm/processor.h>
46 #include <asm/uaccess.h>
49 #include <asm/delay.h>
52 #include <linux/mc146818rtc.h>
53 #include <linux/timex.h>
54 #include <linux/config.h>
56 #include <asm/fixmap.h>
57 #include <asm/cobalt.h>
60 * for x86_do_profile()
65 unsigned long cpu_hz
; /* Detected as we calibrate the TSC */
67 /* Number of usecs that the last interrupt was delayed */
68 static int delay_at_last_interrupt
;
70 static unsigned long last_tsc_low
; /* lsb 32 bits of Time Stamp Counter */
72 /* Cached *multiplier* to convert TSC counts to microseconds.
73 * (see the equation below).
74 * Equal to 2^32 * (1 / (clocks per usec) ).
75 * Initialized in time_init.
77 static unsigned long fast_gettimeoffset_quotient
=0;
79 extern rwlock_t xtime_lock
;
81 static inline unsigned long do_fast_gettimeoffset(void)
83 register unsigned long eax
asm("ax");
84 register unsigned long edx
asm("dx");
86 /* Read the Time Stamp Counter */
90 /* .. relative to previous jiffy (32 bits is enough) */
91 eax
-= last_tsc_low
; /* tsc_low delta */
94 * Time offset = (tsc_low delta) * fast_gettimeoffset_quotient
95 * = (tsc_low delta) * (usecs_per_clock)
96 * = (tsc_low delta) * (usecs_per_jiffy / clocks_per_jiffy)
98 * Using a mull instead of a divl saves up to 31 clock cycles
99 * in the critical path.
103 :"=a" (eax
), "=d" (edx
)
104 :"g" (fast_gettimeoffset_quotient
),
107 /* our adjusted time offset in microseconds */
108 return delay_at_last_interrupt
+ edx
;
111 #define TICK_SIZE tick
113 #ifndef CONFIG_X86_TSC
115 /* This function must be called with interrupts disabled
116 * It was inspired by Steve McCanne's microtime-i386 for BSD. -- jrs
118 * However, the pc-audio speaker driver changes the divisor so that
119 * it gets interrupted rather more often - it loads 64 into the
120 * counter rather than 11932! This has an adverse impact on
121 * do_gettimeoffset() -- it stops working! What is also not
122 * good is that the interval that our timer function gets called
123 * is no longer 10.0002 ms, but 9.9767 ms. To get around this
124 * would require using a different timing source. Maybe someone
125 * could use the RTC - I know that this can interrupt at frequencies
126 * ranging from 8192Hz to 2Hz. If I had the energy, I'd somehow fix
127 * it so that at startup, the timer code in sched.c would select
128 * using either the RTC or the 8253 timer. The decision would be
129 * based on whether there was any other device around that needed
130 * to trample on the 8253. I'd set up the RTC to interrupt at 1024 Hz,
131 * and then do some jiggery to have a version of do_timer that
132 * advanced the clock by 1/1024 s. Every time that reached over 1/100
133 * of a second, then do all the old code. If the time was kept correct
134 * then do_gettimeoffset could just return 0 - there is no low order
135 * divider that can be accessed.
137 * Ideally, you would be able to use the RTC for the speaker driver,
138 * but it appears that the speaker driver really needs interrupt more
139 * often than every 120 us or so.
141 * Anyway, this needs more thought.... pjsg (1993-08-28)
143 * If you are really that interested, you should be reading
144 * comp.protocols.time.ntp!
147 static unsigned long do_slow_gettimeoffset(void)
151 static int count_p
= LATCH
; /* for the first call after boot */
152 static unsigned long jiffies_p
= 0;
155 * cache volatile jiffies temporarily; we have IRQs turned off.
157 unsigned long jiffies_t
;
159 /* timer count may underflow right here */
160 outb_p(0x00, 0x43); /* latch the count ASAP */
162 count
= inb_p(0x40); /* read the latched count */
165 * We do this guaranteed double memory access instead of a _p
166 * postfix in the previous port access. Wheee, hackady hack
170 count
|= inb_p(0x40) << 8;
173 * avoiding timer inconsistencies (they are rare, but they happen)...
174 * there are two kinds of problems that must be avoided here:
175 * 1. the timer counter underflows
176 * 2. hardware problem with the timer, not giving us continuous time,
177 * the counter does small "jumps" upwards on some Pentium systems,
178 * (see c't 95/10 page 335 for Neptun bug.)
181 /* you can safely undefine this if you don't have the Neptune chipset */
183 #define BUGGY_NEPTUN_TIMER
185 if( jiffies_t
== jiffies_p
) {
186 if( count
> count_p
) {
191 /* assumption about timer being IRQ1 */
192 if( inb(0x20) & 0x01 ) {
194 * We cannot detect lost timer interrupts ...
195 * well, that's why we call them lost, don't we? :)
196 * [hmm, on the Pentium and Alpha we can ... sort of]
200 #ifdef BUGGY_NEPTUN_TIMER
202 * for the Neptun bug we know that the 'latch'
203 * command doesnt latch the high and low value
204 * of the counter atomically. Thus we have to
205 * substract 256 from the counter
206 * ... funny, isnt it? :)
211 printk("do_slow_gettimeoffset(): hardware timer problem?\n");
216 jiffies_p
= jiffies_t
;
220 count
= ((LATCH
-1) - count
) * TICK_SIZE
;
221 count
= (count
+ LATCH
/2) / LATCH
;
226 static unsigned long (*do_gettimeoffset
)(void) = do_slow_gettimeoffset
;
230 #define do_gettimeoffset() do_fast_gettimeoffset()
235 * This version of gettimeofday has microsecond resolution
236 * and better than microsecond precision on fast x86 machines with TSC.
238 void do_gettimeofday(struct timeval
*tv
)
240 extern volatile unsigned long lost_ticks
;
242 unsigned long usec
, sec
;
244 read_lock_irqsave(&xtime_lock
, flags
);
245 usec
= do_gettimeoffset();
247 unsigned long lost
= lost_ticks
;
249 usec
+= lost
* (1000000 / HZ
);
252 usec
+= xtime
.tv_usec
;
253 read_unlock_irqrestore(&xtime_lock
, flags
);
255 while (usec
>= 1000000) {
264 void do_settimeofday(struct timeval
*tv
)
266 write_lock_irq(&xtime_lock
);
267 /* This is revolting. We need to set the xtime.tv_usec
268 * correctly. However, the value in this location is
269 * is value at the last tick.
270 * Discover what correction gettimeofday
271 * would have done, and then undo it!
273 tv
->tv_usec
-= do_gettimeoffset();
275 while (tv
->tv_usec
< 0) {
276 tv
->tv_usec
+= 1000000;
281 time_adjust
= 0; /* stop active adjtime() */
282 time_status
|= STA_UNSYNC
;
283 time_maxerror
= NTP_PHASE_LIMIT
;
284 time_esterror
= NTP_PHASE_LIMIT
;
285 write_unlock_irq(&xtime_lock
);
289 * In order to set the CMOS clock precisely, set_rtc_mmss has to be
290 * called 500 ms after the second nowtime has started, because when
291 * nowtime is written into the registers of the CMOS clock, it will
292 * jump to the next second precisely 500 ms later. Check the Motorola
293 * MC146818A or Dallas DS12887 data sheet for details.
295 * BUG: This routine does not handle hour overflow properly; it just
296 * sets the minutes. Usually you'll only notice that after reboot!
298 static int set_rtc_mmss(unsigned long nowtime
)
301 int real_seconds
, real_minutes
, cmos_minutes
;
302 unsigned char save_control
, save_freq_select
;
304 save_control
= CMOS_READ(RTC_CONTROL
); /* tell the clock it's being set */
305 CMOS_WRITE((save_control
|RTC_SET
), RTC_CONTROL
);
307 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
); /* stop and reset prescaler */
308 CMOS_WRITE((save_freq_select
|RTC_DIV_RESET2
), RTC_FREQ_SELECT
);
310 cmos_minutes
= CMOS_READ(RTC_MINUTES
);
311 if (!(save_control
& RTC_DM_BINARY
) || RTC_ALWAYS_BCD
)
312 BCD_TO_BIN(cmos_minutes
);
315 * since we're only adjusting minutes and seconds,
316 * don't interfere with hour overflow. This avoids
317 * messing with unknown time zones but requires your
318 * RTC not to be off by more than 15 minutes
320 real_seconds
= nowtime
% 60;
321 real_minutes
= nowtime
/ 60;
322 if (((abs(real_minutes
- cmos_minutes
) + 15)/30) & 1)
323 real_minutes
+= 30; /* correct for half hour time zone */
326 if (abs(real_minutes
- cmos_minutes
) < 30) {
327 if (!(save_control
& RTC_DM_BINARY
) || RTC_ALWAYS_BCD
) {
328 BIN_TO_BCD(real_seconds
);
329 BIN_TO_BCD(real_minutes
);
331 CMOS_WRITE(real_seconds
,RTC_SECONDS
);
332 CMOS_WRITE(real_minutes
,RTC_MINUTES
);
335 "set_rtc_mmss: can't update from %d to %d\n",
336 cmos_minutes
, real_minutes
);
340 /* The following flags have to be released exactly in this order,
341 * otherwise the DS12887 (popular MC146818A clone with integrated
342 * battery and quartz) will not reset the oscillator and will not
343 * update precisely 500 ms later. You won't find this mentioned in
344 * the Dallas Semiconductor data sheets, but who believes data
345 * sheets anyway ... -- Markus Kuhn
347 CMOS_WRITE(save_control
, RTC_CONTROL
);
348 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
353 /* last time the cmos clock got updated */
354 static long last_rtc_update
= 0;
357 * timer_interrupt() needs to keep up the real-time clock,
358 * as well as call the "do_timer()" routine every clocktick
360 static inline void do_timer_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
363 /* Clear the interrupt */
364 co_cpu_write(CO_CPU_STAT
,co_cpu_read(CO_CPU_STAT
) & ~CO_STAT_TIMEINTR
);
368 * In the SMP case we use the local APIC timer interrupt to do the
369 * profiling, except when we simulate SMP mode on a uniprocessor
370 * system, in that case we have to call the local interrupt handler.
373 if (!user_mode(regs
))
374 x86_do_profile(regs
->eip
);
376 if (!smp_found_config
)
377 smp_local_timer_interrupt(regs
);
381 * If we have an externally synchronized Linux clock, then update
382 * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
383 * called as close as possible to 500 ms before the new second starts.
385 if ((time_status
& STA_UNSYNC
) == 0 &&
386 xtime
.tv_sec
> last_rtc_update
+ 660 &&
387 xtime
.tv_usec
>= 500000 - ((unsigned) tick
) / 2 &&
388 xtime
.tv_usec
<= 500000 + ((unsigned) tick
) / 2) {
389 if (set_rtc_mmss(xtime
.tv_sec
) == 0)
390 last_rtc_update
= xtime
.tv_sec
;
392 last_rtc_update
= xtime
.tv_sec
- 600; /* do it again in 60 s */
397 /* The PS/2 uses level-triggered interrupts. You can't
398 turn them off, nor would you want to (any attempt to
399 enable edge-triggered interrupts usually gets intercepted by a
400 special hardware circuit). Hence we have to acknowledge
401 the timer interrupt. Through some incredibly stupid
402 design idea, the reset for IRQ 0 is done by setting the
403 high bit of the PPI port B (0x61). Note that some PS/2s,
404 notably the 55SX, work fine if this is removed. */
406 irq
= inb_p( 0x61 ); /* read the current state */
407 outb_p( irq
|0x80, 0x61 ); /* reset the IRQ */
412 static int use_tsc
= 0;
415 * This is the same as the above, except we _also_ save the current
416 * Time Stamp Counter value at the time of the timer interrupt, so that
417 * we later on can estimate the time of day more exactly.
419 static void timer_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
424 * Here we are in the timer irq handler. We just have irqs locally
425 * disabled but we don't know if the timer_bh is running on the other
426 * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
427 * the irq version of write_lock because as just said we have irq
428 * locally disabled. -arca
430 write_lock(&xtime_lock
);
435 * It is important that these two operations happen almost at
436 * the same time. We do the RDTSC stuff first, since it's
437 * faster. To avoid any inconsistencies, we need interrupts
442 * Interrupts are just disabled locally since the timer irq
443 * has the SA_INTERRUPT flag set. -arca
446 /* read Pentium cycle counter */
448 rdtscl(last_tsc_low
);
450 outb_p(0x00, 0x43); /* latch the count ASAP */
452 count
= inb_p(0x40); /* read the latched count */
453 count
|= inb(0x40) << 8;
455 count
= ((LATCH
-1) - count
) * TICK_SIZE
;
456 delay_at_last_interrupt
= (count
+ LATCH
/2) / LATCH
;
459 do_timer_interrupt(irq
, NULL
, regs
);
461 write_unlock(&xtime_lock
);
465 /* Converts Gregorian date to seconds since 1970-01-01 00:00:00.
466 * Assumes input in normal date format, i.e. 1980-12-31 23:59:59
467 * => year=1980, mon=12, day=31, hour=23, min=59, sec=59.
469 * [For the Julian calendar (which was used in Russia before 1917,
470 * Britain & colonies before 1752, anywhere else before 1582,
471 * and is still in use by some communities) leave out the
472 * -year/100+year/400 terms, and add 10.]
474 * This algorithm was first published by Gauss (I think).
476 * WARNING: this function will overflow on 2106-02-07 06:28:16 on
477 * machines were long is 32-bit! (However, as time_t is signed, we
478 * will already get problems at other places on 2038-01-19 03:14:08)
480 static inline unsigned long mktime(unsigned int year
, unsigned int mon
,
481 unsigned int day
, unsigned int hour
,
482 unsigned int min
, unsigned int sec
)
484 if (0 >= (int) (mon
-= 2)) { /* 1..12 -> 11,12,1..10 */
485 mon
+= 12; /* Puts Feb last since it has leap day */
489 (unsigned long)(year
/4 - year
/100 + year
/400 + 367*mon
/12 + day
) +
491 )*24 + hour
/* now have hours */
492 )*60 + min
/* now have minutes */
493 )*60 + sec
; /* finally seconds */
496 /* not static: needed by APM */
497 unsigned long get_cmos_time(void)
499 unsigned int year
, mon
, day
, hour
, min
, sec
;
502 /* The Linux interpretation of the CMOS clock register contents:
503 * When the Update-In-Progress (UIP) flag goes from 1 to 0, the
504 * RTC registers show the second which has precisely just started.
505 * Let's hope other operating systems interpret the RTC the same way.
507 /* read RTC exactly on falling edge of update flag */
508 for (i
= 0 ; i
< 1000000 ; i
++) /* may take up to 1 second... */
509 if (CMOS_READ(RTC_FREQ_SELECT
) & RTC_UIP
)
511 for (i
= 0 ; i
< 1000000 ; i
++) /* must try at least 2.228 ms */
512 if (!(CMOS_READ(RTC_FREQ_SELECT
) & RTC_UIP
))
514 do { /* Isn't this overkill ? UIP above should guarantee consistency */
515 sec
= CMOS_READ(RTC_SECONDS
);
516 min
= CMOS_READ(RTC_MINUTES
);
517 hour
= CMOS_READ(RTC_HOURS
);
518 day
= CMOS_READ(RTC_DAY_OF_MONTH
);
519 mon
= CMOS_READ(RTC_MONTH
);
520 year
= CMOS_READ(RTC_YEAR
);
521 } while (sec
!= CMOS_READ(RTC_SECONDS
));
522 if (!(CMOS_READ(RTC_CONTROL
) & RTC_DM_BINARY
) || RTC_ALWAYS_BCD
)
531 if ((year
+= 1900) < 1970)
533 return mktime(year
, mon
, day
, hour
, min
, sec
);
536 static struct irqaction irq0
= { timer_interrupt
, SA_INTERRUPT
, 0, "timer", NULL
, NULL
};
538 /* ------ Calibrate the TSC -------
539 * Return 2^32 * (1 / (TSC clocks per usec)) for do_fast_gettimeoffset().
540 * Too much 64-bit arithmetic here to do this cleanly in C, and for
541 * accuracy's sake we want to keep the overhead on the CTC speaker (channel 2)
542 * output busy loop as low as possible. We avoid reading the CTC registers
543 * directly because of the awkward 8-bit access mechanism of the 82C54
547 #define CALIBRATE_LATCH (5 * LATCH)
548 #define CALIBRATE_TIME (5 * 1000020/HZ)
550 __initfunc(static unsigned long calibrate_tsc(void))
552 /* Set the Gate high, disable speaker */
553 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
556 * Now let's take care of CTC channel 2
558 * Set the Gate high, program CTC channel 2 for mode 0,
559 * (interrupt on terminal count mode), binary count,
560 * load 5 * LATCH count, (LSB and MSB) to begin countdown.
562 outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
563 outb(CALIBRATE_LATCH
& 0xff, 0x42); /* LSB of count */
564 outb(CALIBRATE_LATCH
>> 8, 0x42); /* MSB of count */
567 unsigned long startlow
, starthigh
;
568 unsigned long endlow
, endhigh
;
571 rdtsc(startlow
,starthigh
);
575 } while ((inb(0x61) & 0x20) == 0);
576 rdtsc(endlow
,endhigh
);
578 last_tsc_low
= endlow
;
580 /* Error: ECTCNEVERSET */
584 /* 64-bit subtract - gcc just messes up with long longs */
585 __asm__("subl %2,%0\n\t"
587 :"=a" (endlow
), "=d" (endhigh
)
588 :"g" (startlow
), "g" (starthigh
),
589 "0" (endlow
), "1" (endhigh
));
591 /* Error: ECPUTOOFAST */
595 /* Error: ECPUTOOSLOW */
596 if (endlow
<= CALIBRATE_TIME
)
600 :"=a" (endlow
), "=d" (endhigh
)
601 :"r" (endlow
), "0" (0), "1" (CALIBRATE_TIME
));
607 * The CTC wasn't reliable: we got a hit on the very first read,
608 * or the CPU was so fast/slow that the quotient wouldn't fit in
615 __initfunc(void time_init(void))
617 xtime
.tv_sec
= get_cmos_time();
621 * If we have APM enabled or the CPU clock speed is variable
622 * (CPU stops clock on HLT or slows clock to save power)
623 * then the TSC timestamps may diverge by up to 1 jiffy from
624 * 'real time' but nothing will break.
625 * The most frequent case is that the CPU is "woken" from a halt
626 * state by the timer interrupt itself, so we get 0 error. In the
627 * rare cases where a driver would "wake" the CPU and request a
628 * timestamp, the maximum error is < 1 jiffy. But timestamps are
629 * still perfectly ordered.
630 * Note that the TSC counter will be reset if APM suspends
631 * to disk; this won't break the kernel, though, 'cuz we're
632 * smart. See arch/i386/kernel/apm.c.
635 * Firstly we have to do a CPU check for chips with
636 * a potentially buggy TSC. At this point we haven't run
637 * the ident/bugs checks so we must run this hook as it
638 * may turn off the TSC flag.
640 * NOTE: this doesnt yet handle SMP 486 machines where only
641 * some CPU's have a TSC. Thats never worked and nobody has
642 * moaned if you have the only one in the world - you fix it!
647 if (boot_cpu_data
.x86_capability
& X86_FEATURE_TSC
) {
648 unsigned long tsc_quotient
= calibrate_tsc();
650 fast_gettimeoffset_quotient
= tsc_quotient
;
652 #ifndef do_gettimeoffset
653 do_gettimeoffset
= do_fast_gettimeoffset
;
655 do_get_fast_time
= do_gettimeofday
;
657 /* report CPU clock rate in Hz.
658 * The formula is (10^6 * 2^32) / (2^32 * 1 / (clocks/us)) =
659 * clock/second. Our precision is about 100 ppm.
661 { unsigned long eax
=0, edx
=1000000;
663 :"=a" (cpu_hz
), "=d" (edx
)
665 "0" (eax
), "1" (edx
));
666 printk("Detected %ld Hz processor.\n", cpu_hz
);
672 printk("Starting Cobalt Timer system clock\n");
674 /* Set the countdown value */
675 co_cpu_write(CO_CPU_TIMEVAL
, CO_TIME_HZ
/HZ
);
677 /* Start the timer */
678 co_cpu_write(CO_CPU_CTRL
, co_cpu_read(CO_CPU_CTRL
) | CO_CTRL_TIMERUN
);
680 /* Enable (unmask) the timer interrupt */
681 co_cpu_write(CO_CPU_CTRL
, co_cpu_read(CO_CPU_CTRL
) & ~CO_CTRL_TIMEMASK
);
683 /* Wire cpu IDT entry to s/w handler (and Cobalt APIC to IDT) */
684 setup_x86_irq(CO_IRQ_TIMER
, &irq0
);
686 setup_x86_irq(0, &irq0
);