arch/alpha/kernel/sys_miata.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_miata.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996 Jay A Estabrook
   6  *      Copyright (C) 1998 Richard Henderson
   7  *
   8  * Code supporting the MIATA (EV56+PYXIS).
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/types.h>
  13 #include <linux/mm.h>
  14 #include <linux/sched.h>
  15 #include <linux/pci.h>
  16 #include <linux/init.h>
  17
  18 #include <asm/ptrace.h>
  19 #include <asm/system.h>
  20 #include <asm/dma.h>
  21 #include <asm/irq.h>
  22 #include <asm/mmu_context.h>
  23 #include <asm/io.h>
  24 #include <asm/pgtable.h>
  25 #include <asm/core_pyxis.h>
  26
  27 #include "proto.h"
  28 #include "irq.h"
  29 #include "bios32.h"
  30 #include "machvec.h"
  31
  32
  33 static void
  34 miata_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
  35 {
  36         if (irq >= 16) {
  37                 /* Make CERTAIN none of the bogus ints get enabled... */
  38                 *(vulp)PYXIS_INT_MASK =
  39                         ~((long)mask >> 16) & ~0x400000000000063bUL;
  40                 mb();
  41                 /* ... and read it back to make sure it got written.  */
  42                 *(vulp)PYXIS_INT_MASK;
  43         }
  44         else if (irq >= 8)
  45                 outb(mask >> 8, 0xA1);  /* ISA PIC2 */
  46         else
  47                 outb(mask, 0x21);       /* ISA PIC1 */
  48 }
  49
  50 static void
  51 miata_device_interrupt(unsigned long vector, struct pt_regs *regs)
  52 {
  53         unsigned long pld, tmp;
  54         unsigned int i;
  55
  56         /* Read the interrupt summary register of PYXIS */
  57         pld = *(vulp)PYXIS_INT_REQ;
  58
  59         /*
  60          * For now, AND off any bits we are not interested in:
  61          *   HALT (2), timer (6), ISA Bridge (7), 21142/3 (8)
  62          * then all the PCI slots/INTXs (12-31).
  63          */
  64         /* Maybe HALT should only be used for SRM console boots? */
  65         pld &= 0x00000000fffff9c4UL;
  66
  67         /*
  68          * Now for every possible bit set, work through them and call
  69          * the appropriate interrupt handler.
  70          */
  71         while (pld) {
  72                 i = ffz(~pld);
  73                 pld &= pld - 1; /* clear least bit set */
  74                 if (i == 7) {
  75                         isa_device_interrupt(vector, regs);
  76                 } else if (i == 6) {
  77                         continue;
  78                 } else {
  79                         /* if not timer int */
  80                         handle_irq(16 + i, 16 + i, regs);
  81                 }
  82                 *(vulp)PYXIS_INT_REQ = 1UL << i; mb();
  83                 tmp = *(vulp)PYXIS_INT_REQ;
  84         }
  85 }
  86
  87 static void
  88 miata_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
  89 {
  90         int irq, ack;
  91
  92         ack = irq = (vector - 0x800) >> 4;
  93
  94         /*
  95          * I really hate to do this, but the MIATA SRM console ignores the
  96          *  low 8 bits in the interrupt summary register, and reports the
  97          *  vector 0x80 *lower* than I expected from the bit numbering in
  98          *  the documentation.
  99          * This was done because the low 8 summary bits really aren't used
 100          *  for reporting any interrupts (the PCI-ISA bridge, bit 7, isn't
 101          *  used for this purpose, as PIC interrupts are delivered as the
 102          *  vectors 0x800-0x8f0).
 103          * But I really don't want to change the fixup code for allocation
 104          *  of IRQs, nor the alpha_irq_mask maintenance stuff, both of which
 105          *  look nice and clean now.
 106          * So, here's this grotty hack... :-(
 107          */
 108         if (irq >= 16)
 109                 ack = irq = irq + 8;
 110
 111         handle_irq(irq, ack, regs);
 112 }
 113
 114 static void __init
 115 miata_init_irq(void)
 116 {
 117         STANDARD_INIT_IRQ_PROLOG;
 118
 119         if (alpha_using_srm)
 120                 alpha_mv.device_interrupt = miata_srm_device_interrupt;
 121
 122         /* Note invert on MASK bits.  */
 123         *(vulp)PYXIS_INT_MASK =
 124           ~((long)alpha_irq_mask >> 16) & ~0x400000000000063bUL; mb();
 125 #if 0
 126         /* These break on MiataGL so we'll try not to do it at all.  */
 127         *(vulp)PYXIS_INT_HILO = 0x000000B2UL; mb();     /* ISA/NMI HI */
 128         *(vulp)PYXIS_RT_COUNT = 0UL; mb();              /* clear count */
 129 #endif
 130         /* Clear upper timer.  */
 131         *(vulp)PYXIS_INT_REQ  = 0x4000000000000180UL; mb();
 132
 133         enable_irq(16 + 2);     /* enable HALT switch - SRM only? */
 134         enable_irq(16 + 6);     /* enable timer */
 135         enable_irq(16 + 7);     /* enable ISA PIC cascade */
 136         enable_irq(2);          /* enable cascade */
 137 }
 138
 139
 140 /*
 141  * PCI Fixup configuration.
 142  *
 143  * Summary @ PYXIS_INT_REQ:
 144  * Bit      Meaning
 145  * 0        Fan Fault
 146  * 1        NMI
 147  * 2        Halt/Reset switch
 148  * 3        none
 149  * 4        CID0 (Riser ID)
 150  * 5        CID1 (Riser ID)
 151  * 6        Interval timer
 152  * 7        PCI-ISA Bridge
 153  * 8        Ethernet
 154  * 9        EIDE (deprecated, ISA 14/15 used)
 155  *10        none
 156  *11        USB
 157  *12        Interrupt Line A from slot 4
 158  *13        Interrupt Line B from slot 4
 159  *14        Interrupt Line C from slot 4
 160  *15        Interrupt Line D from slot 4
 161  *16        Interrupt Line A from slot 5
 162  *17        Interrupt line B from slot 5
 163  *18        Interrupt Line C from slot 5
 164  *19        Interrupt Line D from slot 5
 165  *20        Interrupt Line A from slot 1
 166  *21        Interrupt Line B from slot 1
 167  *22        Interrupt Line C from slot 1
 168  *23        Interrupt Line D from slot 1
 169  *24        Interrupt Line A from slot 2
 170  *25        Interrupt Line B from slot 2
 171  *26        Interrupt Line C from slot 2
 172  *27        Interrupt Line D from slot 2
 173  *27        Interrupt Line A from slot 3
 174  *29        Interrupt Line B from slot 3
 175  *30        Interrupt Line C from slot 3
 176  *31        Interrupt Line D from slot 3
 177  *
 178  * The device to slot mapping looks like:
 179  *
 180  * Slot     Device
 181  *  3       DC21142 Ethernet
 182  *  4       EIDE CMD646
 183  *  5       none
 184  *  6       USB
 185  *  7       PCI-ISA bridge
 186  *  8       PCI-PCI Bridge      (SBU Riser)
 187  *  9       none
 188  * 10       none
 189  * 11       PCI on board slot 4 (SBU Riser)
 190  * 12       PCI on board slot 5 (SBU Riser)
 191  *
 192  *  These are behind the bridge, so I'm not sure what to do...
 193  *
 194  * 13       PCI on board slot 1 (SBU Riser)
 195  * 14       PCI on board slot 2 (SBU Riser)
 196  * 15       PCI on board slot 3 (SBU Riser)
 197  *
 198  *
 199  * This two layered interrupt approach means that we allocate IRQ 16 and
 200  * above for PCI interrupts.  The IRQ relates to which bit the interrupt
 201  * comes in on.  This makes interrupt processing much easier.
 202  */
 203
 204 static int __init
 205 miata_map_irq(struct pci_dev *dev, int slot, int pin)
 206 {
 207         static char irq_tab[18][5] __initlocaldata = {
 208                 /*INT    INTA   INTB   INTC   INTD */
 209                 {16+ 8, 16+ 8, 16+ 8, 16+ 8, 16+ 8},  /* IdSel 14,  DC21142 */
 210                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 15,  EIDE    */
 211                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 16,  none    */
 212                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 17,  none    */
 213                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 18,  PCI-ISA */
 214                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 19,  PCI-PCI */
 215                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 20,  none    */
 216                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 21,  none    */
 217                 {16+12, 16+12, 16+13, 16+14, 16+15},  /* IdSel 22,  slot 4  */
 218                 {16+16, 16+16, 16+17, 16+18, 16+19},  /* IdSel 23,  slot 5  */
 219                 /* the next 7 are actually on PCI bus 1, across the bridge */
 220                 {16+11, 16+11, 16+11, 16+11, 16+11},  /* IdSel 24,  QLISP/GL*/
 221                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 25,  none    */
 222                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 26,  none    */
 223                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 27,  none    */
 224                 {16+20, 16+20, 16+21, 16+22, 16+23},  /* IdSel 28,  slot 1  */
 225                 {16+24, 16+24, 16+25, 16+26, 16+27},  /* IdSel 29,  slot 2  */
 226                 {16+28, 16+28, 16+29, 16+30, 16+31},  /* IdSel 30,  slot 3  */
 227                 /* this bridge is on the main bus of the later original MIATA */
 228                 {   -1,    -1,    -1,    -1,    -1},  /* IdSel 31,  PCI-PCI */
 229         };
 230         const long min_idsel = 3, max_idsel = 20, irqs_per_slot = 5;
 231         return COMMON_TABLE_LOOKUP;
 232 }
 233
 234 static int __init
 235 miata_swizzle(struct pci_dev *dev, int *pinp)
 236 {
 237         int slot, pin = *pinp;
 238
 239         /* Check first for the built-in bridge.  */
 240         if ((PCI_SLOT(dev->bus->self->devfn) == 8) ||
 241             (PCI_SLOT(dev->bus->self->devfn) == 20)) {
 242                 slot = PCI_SLOT(dev->devfn) + 9;
 243         }
 244         else
 245         {
 246                 /* Must be a card-based bridge.  */
 247                 do {
 248                         if ((PCI_SLOT(dev->bus->self->devfn) == 8) ||
 249                             (PCI_SLOT(dev->bus->self->devfn) == 20)) {
 250                                 slot = PCI_SLOT(dev->devfn) + 9;
 251                                 break;
 252                         }
 253                         pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
 254
 255                         /* Move up the chain of bridges.  */
 256                         dev = dev->bus->self;
 257                         /* Slot of the next bridge.  */
 258                         slot = PCI_SLOT(dev->devfn);
 259                 } while (dev->bus->self);
 260         }
 261         *pinp = pin;
 262         return slot;
 263 }
 264
 265 static void __init
 266 miata_pci_fixup(void)
 267 {
 268         layout_all_busses(DEFAULT_IO_BASE, DEFAULT_MEM_BASE);
 269         common_pci_fixup(miata_map_irq, miata_swizzle);
 270         SMC669_Init(0); /* it might be a GL (fails harmlessly if not) */
 271         es1888_init();
 272 }
 273
 274
 275 /*
 276  * The System Vector
 277  */
 278
 279 struct alpha_machine_vector miata_mv __initmv = {
 280         vector_name:            "Miata",
 281         DO_EV5_MMU,
 282         DO_DEFAULT_RTC,
 283         DO_PYXIS_IO,
 284         DO_PYXIS_BUS,
 285         machine_check:          pyxis_machine_check,
 286         max_dma_address:        ALPHA_MAX_DMA_ADDRESS,
 287
 288         nr_irqs:                48,
 289         irq_probe_mask:         _PROBE_MASK(48),
 290         update_irq_hw:          miata_update_irq_hw,
 291         ack_irq:                generic_ack_irq,
 292         device_interrupt:       miata_device_interrupt,
 293
 294         init_arch:              pyxis_init_arch,
 295         init_irq:               miata_init_irq,
 296         init_pit:               generic_init_pit,
 297         pci_fixup:              miata_pci_fixup,
 298         kill_arch:              generic_kill_arch,
 299 };
 300 ALIAS_MV(miata)