2 * $Id: quirks.c,v 1.5 1998/05/02 19:24:14 mj Exp $
4 * PCI Chipset-Specific Quirks
6 * Extracted from pci.c and rewritten by Martin Mares
8 * This is the right place for all special fixups for on-board
9 * devices not depending on system architecture -- for example
13 #include <linux/config.h>
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
22 #ifdef CONFIG_PCI_OPTIMIZE
25 * The PCI Bridge Optimization -- Some BIOS'es are too lazy
26 * and are unable to turn on several features which can burst
31 * An item of this structure has the following meaning:
32 * for each optimization, the register address, the mask
33 * and value to write to turn it on.
35 struct optimization_type
{
39 } bridge_optimization
[] __initdata
= {
40 {"Cache L2", "write through", "write back"},
41 {"CPU-PCI posted write", "off", "on"},
42 {"CPU-Memory posted write", "off", "on"},
43 {"PCI-Memory posted write", "off", "on"},
44 {"PCI burst", "off", "on"}
47 #define NUM_OPTIMIZATIONS \
48 (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
50 struct bridge_mapping_type
{
51 unsigned char addr
; /* config space address */
54 } bridge_mapping
[] = {
56 * Intel Neptune/Mercury/Saturn:
57 * If the internal cache is write back,
58 * the L2 cache must be write through!
59 * I've to check out how to control that
60 * for the moment, we won't touch the cache
69 * UMC 8891A Pentium chipset:
70 * Why did you think UMC was cheaper ??
79 __initfunc(static void quirk_bridge(struct pci_dev
*dev
, int pos
))
81 struct bridge_mapping_type
*bmap
;
85 pos
*= NUM_OPTIMIZATIONS
;
86 for (i
= 0; i
< NUM_OPTIMIZATIONS
; i
++) {
87 printk(" %s: ", bridge_optimization
[i
].type
);
88 bmap
= &bridge_mapping
[pos
+ i
];
90 printk("Not supported.\n");
92 pci_read_config_byte(dev
, bmap
->addr
, &val
);
93 if ((val
& bmap
->mask
) == bmap
->value
)
94 printk("%s.\n", bridge_optimization
[i
].on
);
96 printk("%s", bridge_optimization
[i
].off
);
97 pci_write_config_byte(dev
,
99 (val
& (0xff - bmap
->mask
)) + bmap
->value
);
100 printk(" -> %s.\n", bridge_optimization
[i
].on
);
109 /* Deal with broken BIOS'es that neglect to enable passive release,
110 which can cause problems in combination with the 82441FX/PPro MTRRs */
111 __initfunc(static void quirk_passive_release(struct pci_dev
*dev
, int arg
))
113 struct pci_dev
*d
= NULL
;
116 /* We have to make sure a particular bit is set in the PIIX3
117 ISA bridge, so we have to go out and find it. */
118 while ((d
= pci_find_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, d
))) {
119 pci_read_config_byte(d
, 0x82, &dlc
);
121 printk("PIIX3: Enabling Passive Release\n");
123 pci_write_config_byte(d
, 0x82, dlc
);
128 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
129 but VIA don't answer queries. If you happen to have good contacts at VIA
130 ask them for me please -- Alan
132 This appears to be BIOS not version dependent. So presumably there is a
136 int isa_dma_bridge_buggy
= 0; /* Exported */
138 __initfunc(static void quirk_isa_dma_hangs(struct pci_dev
*dev
, int arg
))
140 if(!isa_dma_bridge_buggy
)
142 isa_dma_bridge_buggy
=1;
143 printk(KERN_INFO
"Activating ISA DMA hang workarounds.\n");
148 typedef void (*quirk_handler
)(struct pci_dev
*, int);
151 * Mapping from quirk handler functions to names.
155 quirk_handler handler
;
159 static struct quirk_name quirk_names
[] __initdata
= {
160 #ifdef CONFIG_PCI_OPTIMIZE
161 { quirk_bridge
, "Bridge optimization" },
163 { quirk_passive_release
,"Passive release enable" },
164 { quirk_isa_dma_hangs
, "Work around ISA DMA hangs" },
168 static inline char *get_quirk_name(quirk_handler handler
)
172 for (i
= 0; i
< sizeof(quirk_names
)/sizeof(quirk_names
[0]); i
++)
173 if (handler
== quirk_names
[i
].handler
)
174 return quirk_names
[i
].name
;
181 * Mapping from PCI vendor/device ID pairs to quirk function types and arguments
185 unsigned short vendor
, device
;
186 quirk_handler handler
;
190 static struct quirk_info quirk_list
[] __initdata
= {
191 #ifdef CONFIG_PCI_OPTIMIZE
192 { PCI_VENDOR_ID_DEC
, PCI_DEVICE_ID_DEC_BRD
, quirk_bridge
, 0x00 },
193 { PCI_VENDOR_ID_UMC
, PCI_DEVICE_ID_UMC_UM8891A
, quirk_bridge
, 0x01 },
194 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82424
, quirk_bridge
, 0x00 },
195 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82434
, quirk_bridge
, 0x00 },
196 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82430
, quirk_bridge
, 0x00 },
198 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
, 0x00 },
200 * Its not totally clear which chipsets are the problematic ones
201 * This is the 82C586 variants. At the moment the 596 is an unknown
204 { PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_isa_dma_hangs
, 0x00 },
207 __initfunc(void pci_quirks_init(void))
213 printk("PCI: pci_quirks_init\n");
215 for(d
=pci_devices
; d
; d
=d
->next
) {
216 for(i
=0; i
<sizeof(quirk_list
)/sizeof(quirk_list
[0]); i
++) {
217 struct quirk_info
*q
= quirk_list
+ i
;
218 if (q
->vendor
== d
->vendor
&& q
->device
== d
->device
) {
219 printk("PCI: %02x:%02x [%04x/%04x]: %s (%02x)\n",
220 d
->bus
->number
, d
->devfn
, d
->vendor
, d
->device
,
221 get_quirk_name(q
->handler
), q
->arg
);
222 q
->handler(d
, q
->arg
);