include/asm-sparc64/io.h

   1 /* $Id: io.h,v 1.33 2000/02/25 05:47:38 davem Exp $ */
   2 #ifndef __SPARC64_IO_H
   3 #define __SPARC64_IO_H
   4
   5 #include <linux/kernel.h>
   6 #include <linux/types.h>
   7
   8 #include <asm/page.h>      /* IO address mapping routines need this */
   9 #include <asm/system.h>
  10 #include <asm/asi.h>
  11
  12 /* PC crapola... */
  13 #define __SLOW_DOWN_IO  do { } while (0)
  14 #define SLOW_DOWN_IO    do { } while (0)
  15
  16 extern unsigned long virt_to_bus_not_defined_use_pci_map(volatile void *addr);
  17 #define virt_to_bus virt_to_bus_not_defined_use_pci_map
  18 extern unsigned long bus_to_virt_not_defined_use_pci_map(volatile void *addr);
  19 #define bus_to_virt bus_to_virt_not_defined_use_pci_map
  20
  21 /* Different PCI controllers we support have their PCI MEM space
  22  * mapped to an either 2GB (Psycho) or 4GB (Sabre) aligned area,
  23  * so need to chop off the top 33 or 32 bits.
  24  */
  25 extern unsigned long pci_memspace_mask;
  26
  27 #define bus_dvma_to_mem(__vaddr) ((__vaddr) & pci_memspace_mask)
  28
  29 extern __inline__ unsigned int inb(unsigned long addr)
  30 {
  31         unsigned int ret;
  32
  33         __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_inb */"
  34                              : "=r" (ret)
  35                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
  36
  37         return ret;
  38 }
  39
  40 extern __inline__ unsigned int inw(unsigned long addr)
  41 {
  42         unsigned int ret;
  43
  44         __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_inw */"
  45                              : "=r" (ret)
  46                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
  47
  48         return ret;
  49 }
  50
  51 extern __inline__ unsigned int inl(unsigned long addr)
  52 {
  53         unsigned int ret;
  54
  55         __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_inl */"
  56                              : "=r" (ret)
  57                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
  58
  59         return ret;
  60 }
  61
  62 extern __inline__ void outb(unsigned char b, unsigned long addr)
  63 {
  64         __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_outb */"
  65                              : /* no outputs */
  66                              : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
  67 }
  68
  69 extern __inline__ void outw(unsigned short w, unsigned long addr)
  70 {
  71         __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_outw */"
  72                              : /* no outputs */
  73                              : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
  74 }
  75
  76 extern __inline__ void outl(unsigned int l, unsigned long addr)
  77 {
  78         __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_outl */"
  79                              : /* no outputs */
  80                              : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
  81 }
  82
  83 #define inb_p inb
  84 #define outb_p outb
  85 #define inw_p inw
  86 #define outw_p outw
  87 #define inl_p inl
  88 #define outl_p outl
  89
  90 extern void outsb(unsigned long addr, const void *src, unsigned long count);
  91 extern void outsw(unsigned long addr, const void *src, unsigned long count);
  92 extern void outsl(unsigned long addr, const void *src, unsigned long count);
  93 extern void insb(unsigned long addr, void *dst, unsigned long count);
  94 extern void insw(unsigned long addr, void *dst, unsigned long count);
  95 extern void insl(unsigned long addr, void *dst, unsigned long count);
  96
  97 /* Memory functions, same as I/O accesses on Ultra. */
  98 extern __inline__ unsigned int _readb(unsigned long addr)
  99 {
 100         unsigned int ret;
 101
 102         __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
 103                              : "=r" (ret)
 104                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
 105
 106         return ret;
 107 }
 108
 109 extern __inline__ unsigned int _readw(unsigned long addr)
 110 {
 111         unsigned int ret;
 112
 113         __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
 114                              : "=r" (ret)
 115                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
 116
 117         return ret;
 118 }
 119
 120 extern __inline__ unsigned int _readl(unsigned long addr)
 121 {
 122         unsigned int ret;
 123
 124         __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
 125                              : "=r" (ret)
 126                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
 127
 128         return ret;
 129 }
 130
 131 extern __inline__ void _writeb(unsigned char b, unsigned long addr)
 132 {
 133         __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
 134                              : /* no outputs */
 135                              : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
 136 }
 137
 138 extern __inline__ void _writew(unsigned short w, unsigned long addr)
 139 {
 140         __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
 141                              : /* no outputs */
 142                              : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
 143 }
 144
 145 extern __inline__ void _writel(unsigned int l, unsigned long addr)
 146 {
 147         __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
 148                              : /* no outputs */
 149                              : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
 150 }
 151
 152 #define readb(__addr)           (_readb((unsigned long)(__addr)))
 153 #define readw(__addr)           (_readw((unsigned long)(__addr)))
 154 #define readl(__addr)           (_readl((unsigned long)(__addr)))
 155 #define writeb(__b, __addr)     (_writeb((__b), (unsigned long)(__addr)))
 156 #define writew(__w, __addr)     (_writew((__w), (unsigned long)(__addr)))
 157 #define writel(__l, __addr)     (_writel((__l), (unsigned long)(__addr)))
 158
 159 /* Valid I/O Space regions are anywhere, because each PCI bus supported
 160  * can live in an arbitrary area of the physical address range.
 161  */
 162 #define IO_SPACE_LIMIT 0xffffffffffffffffUL
 163
 164 /* Now, SBUS variants, only difference from PCI is that we do
 165  * not use little-endian ASIs.
 166  */
 167 extern __inline__ unsigned int _sbus_readb(unsigned long addr)
 168 {
 169         unsigned int ret;
 170
 171         __asm__ __volatile__("lduba\t[%1] %2, %0\t/* sbus_readb */"
 172                              : "=r" (ret)
 173                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
 174
 175         return ret;
 176 }
 177
 178 extern __inline__ unsigned int _sbus_readw(unsigned long addr)
 179 {
 180         unsigned int ret;
 181
 182         __asm__ __volatile__("lduha\t[%1] %2, %0\t/* sbus_readw */"
 183                              : "=r" (ret)
 184                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
 185
 186         return ret;
 187 }
 188
 189 extern __inline__ unsigned int _sbus_readl(unsigned long addr)
 190 {
 191         unsigned int ret;
 192
 193         __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* sbus_readl */"
 194                              : "=r" (ret)
 195                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
 196
 197         return ret;
 198 }
 199
 200 extern __inline__ void _sbus_writeb(unsigned char b, unsigned long addr)
 201 {
 202         __asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
 203                              : /* no outputs */
 204                              : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
 205 }
 206
 207 extern __inline__ void _sbus_writew(unsigned short w, unsigned long addr)
 208 {
 209         __asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
 210                              : /* no outputs */
 211                              : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
 212 }
 213
 214 extern __inline__ void _sbus_writel(unsigned int l, unsigned long addr)
 215 {
 216         __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
 217                              : /* no outputs */
 218                              : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
 219 }
 220
 221 #define sbus_readb(__addr)              (_sbus_readb((unsigned long)(__addr)))
 222 #define sbus_readw(__addr)              (_sbus_readw((unsigned long)(__addr)))
 223 #define sbus_readl(__addr)              (_sbus_readl((unsigned long)(__addr)))
 224 #define sbus_writeb(__b, __addr)        (_sbus_writeb((__b), (unsigned long)(__addr)))
 225 #define sbus_writew(__w, __addr)        (_sbus_writew((__w), (unsigned long)(__addr)))
 226 #define sbus_writel(__l, __addr)        (_sbus_writel((__l), (unsigned long)(__addr)))
 227
 228 static inline void *_sbus_memset_io(unsigned long dst, int c, __kernel_size_t n)
 229 {
 230         while(n--) {
 231                 sbus_writeb(c, dst);
 232                 dst++;
 233         }
 234         return (void *) dst;
 235 }
 236
 237 #define sbus_memset_io(d,c,sz)  \
 238         _sbus_memset_io((unsigned long)d,(int)c,(__kernel_size_t)sz)
 239
 240 static inline void *
 241 _memset_io(void *dst, int c, __kernel_size_t n)
 242 {
 243         char *d = dst;
 244
 245         while (n--) {
 246                 writeb(c, d);
 247                 d++;
 248         }
 249
 250         return dst;
 251 }
 252
 253 #define memset_io(d,c,sz)       \
 254         _memset_io((void *)d,(int)c,(__kernel_size_t)sz)
 255
 256 static inline void *
 257 _memcpy_fromio(void *dst, unsigned long src, __kernel_size_t n)
 258 {
 259         char *d = dst;
 260
 261         while (n--) {
 262                 char tmp = readb(src);
 263                 *d++ = tmp;
 264                 src++;
 265         }
 266
 267         return dst;
 268 }
 269
 270 #define memcpy_fromio(d,s,sz)   \
 271         _memcpy_fromio((void *)d,(unsigned long)s,(__kernel_size_t)sz)
 272
 273 static inline void *
 274 _memcpy_toio(unsigned long dst, const void *src, __kernel_size_t n)
 275 {
 276         const char *s = src;
 277         unsigned long d = dst;
 278
 279         while (n--) {
 280                 char tmp = *s++;
 281                 writeb(tmp, d);
 282                 d++;
 283         }
 284         return (void *)dst;
 285 }
 286
 287 #define memcpy_toio(d,s,sz)     \
 288         _memcpy_toio((unsigned long)d,(const void *)s,(__kernel_size_t)sz)
 289
 290 static inline int check_signature(unsigned long io_addr,
 291                                   const unsigned char *signature,
 292                                   int length)
 293 {
 294         int retval = 0;
 295         do {
 296                 if (readb(io_addr++) != *signature++)
 297                         goto out;
 298         } while (--length);
 299         retval = 1;
 300 out:
 301         return retval;
 302 }
 303
 304 /* On sparc64 we have the whole physical IO address space accessible
 305  * using physically addressed loads and stores, so this does nothing.
 306  */
 307 #define ioremap(__offset, __size)       ((void *)(__offset))
 308 #define iounmap(__addr)                 do { } while(0)
 309
 310 /* Similarly for SBUS. */
 311 #define sbus_ioremap(__res, __offset, __size, __name) \
 312 ({      unsigned long __ret; \
 313         __ret  = (__res)->start + (((__res)->flags & 0x1ffUL) << 32UL); \
 314         __ret += (unsigned long) (__offset); \
 315         if (! request_region((__ret), (__size), (__name))) \
 316                 __ret = 0UL; \
 317         __ret; \
 318 })
 319
 320 #define sbus_iounmap(__addr, __size)    \
 321         release_region((__addr), (__size))
 322
 323 /* Nothing to do */
 324
 325 #define dma_cache_inv(_start,_size)             do { } while (0)
 326 #define dma_cache_wback(_start,_size)           do { } while (0)
 327 #define dma_cache_wback_inv(_start,_size)       do { } while (0)
 328
 329 #endif /* !(__SPARC64_IO_H) */