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Import 2.3.48
[davej-history.git] / drivers / isdn / hisax / hfc_pci.c
blobf2e7abf1027f88fe00a2ae53397767d9780fdd13
1 /* $Id: hfc_pci.c,v 1.27 2000/02/26 00:35:12 keil Exp $
2
3 * hfc_pci.c low level driver for CCD´s hfc-pci based cards
4 *
5 * Author Werner Cornelius (werner@isdn4linux.de)
6 * based on existing driver for CCD hfc ISA cards
7 *
8 * Copyright 1999 by Werner Cornelius (werner@isdn4linux.de)
9 * Copyright 1999 by Karsten Keil (keil@isdn4linux.de)
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * $Log: hfc_pci.c,v $
26 * Revision 1.27 2000/02/26 00:35:12 keil
27 * Fix skb freeing in interrupt context
28 *
29 * Revision 1.26 2000/02/09 20:22:55 werner
30 *
31 * Updated PCI-ID table
32 *
33 * Revision 1.25 1999/12/19 13:09:42 keil
34 * changed TASK_INTERRUPTIBLE into TASK_UNINTERRUPTIBLE for
35 * signal proof delays
36 *
37 * Revision 1.24 1999/11/17 23:59:55 werner
38 *
39 * removed unneeded data
40 *
41 * Revision 1.23 1999/11/07 17:01:55 keil
42 * fix for 2.3 pci structs
43 *
44 * Revision 1.22 1999/10/10 20:14:27 werner
45 *
46 * Correct B2-chan usage in conjuntion with echo mode. First implementation of NT-leased line mode.
47 *
48 * Revision 1.21 1999/10/02 17:47:49 werner
49 *
50 * Changed init order, added correction for page alignment with shared mem
51 *
52 * Revision 1.20 1999/09/07 06:18:55 werner
53 *
54 * Added io parameter for HFC-PCI based cards. Needed only with multiple cards
55 * when initialisation/selection order needs to be set.
56 *
57 * Revision 1.19 1999/09/04 06:20:06 keil
58 * Changes from kernel set_current_state()
59 *
60 * Revision 1.18 1999/08/29 17:05:44 werner
61 * corrected tx_lo line setup. Datasheet is not correct.
62 *
63 * Revision 1.17 1999/08/28 21:04:27 werner
64 * Implemented full audio support (transparent mode)
65 *
66 * Revision 1.16 1999/08/25 17:01:27 keil
67 * Use new LL->HL auxcmd call
68 *
69 * Revision 1.15 1999/08/22 20:27:05 calle
70 * backported changes from kernel 2.3.14:
71 * - several #include "config.h" gone, others come.
72 * - "struct device" changed to "struct net_device" in 2.3.14, added a
73 * define in isdn_compat.h for older kernel versions.
74 *
75 * Revision 1.14 1999/08/12 18:59:45 werner
76 * Added further manufacturer and device ids to PCI list
77 *
78 * Revision 1.13 1999/08/11 21:01:28 keil
79 * new PCI codefix
80 *
81 * Revision 1.12 1999/08/10 16:01:58 calle
82 * struct pci_dev changed in 2.3.13. Made the necessary changes.
83 *
84 * Revision 1.11 1999/08/09 19:13:32 werner
85 * moved constant pci ids to pci id table
86 *
87 * Revision 1.10 1999/08/08 10:17:34 werner
88 * added new PCI vendor and card ids for Manufacturer 0x1043
89 *
90 * Revision 1.9 1999/08/07 21:09:10 werner
91 * Fixed another memcpy problem in fifo handling.
92 * Thanks for debugging aid by Olaf Kordwittenborg.
93 *
94 * Revision 1.8 1999/07/23 14:25:15 werner
95 * Some smaller bug fixes and prepared support for GCI/IOM bus
96 *
97 * Revision 1.7 1999/07/14 21:24:20 werner
98 * fixed memcpy problem when using E-channel feature
99 *
100 * Revision 1.6 1999/07/13 21:08:08 werner
101 * added echo channel logging feature.
102 *
103 * Revision 1.5 1999/07/12 21:05:10 keil
104 * fix race in IRQ handling
105 * added watchdog for lost IRQs
106 *
107 * Revision 1.4 1999/07/04 21:51:39 werner
108 * Changes to solve problems with irq sharing and smp machines
109 * Thanks to Karsten Keil and Alex Holden for giving aid with
110 * testing and debugging
111 *
112 * Revision 1.3 1999/07/01 09:43:19 keil
113 * removed additional schedules in timeouts
114 *
115 * Revision 1.2 1999/07/01 08:07:51 keil
116 * Initial version
117 *
118 *
119 *
120 */
121
122 #include <linux/config.h>
123 #define __NO_VERSION__
124 #include "hisax.h"
125 #include "hfc_pci.h"
126 #include "isdnl1.h"
127 #include <linux/pci.h>
128 #include <linux/interrupt.h>
129
130 extern const char *CardType[];
131
132 static const char *hfcpci_revision = "$Revision: 1.27 $";
133
134 /* table entry in the PCI devices list */
135 typedef struct {
136 int vendor_id;
137 int device_id;
138 char *vendor_name;
139 char *card_name;
140 } PCI_ENTRY;
141
142 #define NT_T1_COUNT 20 /* number of 3.125ms interrupts for G2 timeout */
143
144 static const PCI_ENTRY id_list[] =
145 {
146 {0x1397, 0x2BD0, "CCD/Billion/Asuscom", "2BD0"},
147 {0x1397, 0xB000, "Billion", "B000"},
148 {0x1397, 0xB006, "Billion", "B006"},
149 {0x1397, 0xB007, "Billion", "B007"},
150 {0x1397, 0xB008, "Billion", "B008"},
151 {0x1397, 0xB009, "Billion", "B009"},
152 {0x1397, 0xB00A, "Billion", "B00A"},
153 {0x1397, 0xB00B, "Billion", "B00B"},
154 {0x1397, 0xB00C, "Billion", "B00C"},
155 {0x1043, 0x0675, "Asuscom/Askey", "675"},
156 {0x0871, 0xFFA2, "German telekom", "T-Concept"},
157 {0x0871, 0xFFA1, "German telekom", "A1T"},
158 {0x1051, 0x0100, "Motorola MC145575", "MC145575"},
159 {0x1397, 0xB100, "Seyeon", "B100"},
160 {0x15B0, 0x2BD0, "Zoltrix", "2BD0"},
161 {0x114f, 0x71, "Digi intl.","Digicom"},
162 {0, 0, NULL, NULL},
163 };
164
165
166 #if CONFIG_PCI
167
168 /******************************************/
169 /* free hardware resources used by driver */
170 /******************************************/
171 void
172 release_io_hfcpci(struct IsdnCardState *cs)
173 {
174 int flags;
175
176 save_flags(flags);
177 cli();
178 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */
179 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
180 restore_flags(flags);
181 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */
182 sti();
183 set_current_state(TASK_UNINTERRUPTIBLE);
184 schedule_timeout((30 * HZ) / 1000); /* Timeout 30ms */
185 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */
186 #if CONFIG_PCI
187 pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, 0); /* disable memory mapped ports + busmaster */
188 #endif /* CONFIG_PCI */
189 del_timer(&cs->hw.hfcpci.timer);
190 kfree(cs->hw.hfcpci.share_start);
191 cs->hw.hfcpci.share_start = NULL;
192 vfree(cs->hw.hfcpci.pci_io);
193 }
194
195 /********************************************************************************/
196 /* function called to reset the HFC PCI chip. A complete software reset of chip */
197 /* and fifos is done. */
198 /********************************************************************************/
199 static void
200 reset_hfcpci(struct IsdnCardState *cs)
201 {
202 long flags;
203
204 save_flags(flags);
205 cli();
206 pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */
207 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */
208 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
209
210 printk(KERN_INFO "HFC_PCI: resetting card\n");
211 pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, PCI_ENA_MEMIO + PCI_ENA_MASTER); /* enable memory ports + busmaster */
212 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */
213 sti();
214 set_current_state(TASK_UNINTERRUPTIBLE);
215 schedule_timeout((30 * HZ) / 1000); /* Timeout 30ms */
216 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */
217 set_current_state(TASK_UNINTERRUPTIBLE);
218 schedule_timeout((20 * HZ) / 1000); /* Timeout 20ms */
219 if (Read_hfc(cs, HFCPCI_STATUS) & 2)
220 printk(KERN_WARNING "HFC-PCI init bit busy\n");
221
222 cs->hw.hfcpci.fifo_en = 0x30; /* only D fifos enabled */
223 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
224
225 cs->hw.hfcpci.trm = 0 + HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
226 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
227
228 Write_hfc(cs, HFCPCI_CLKDEL, 0x0e); /* ST-Bit delay for TE-Mode */
229 cs->hw.hfcpci.sctrl_e = HFCPCI_AUTO_AWAKE;
230 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); /* S/T Auto awake */
231 cs->hw.hfcpci.bswapped = 0; /* no exchange */
232 cs->hw.hfcpci.nt_mode = 0; /* we are in TE mode */
233 cs->hw.hfcpci.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
234 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
235
236 cs->hw.hfcpci.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
237 HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
238 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
239
240 /* Clear already pending ints */
241 if (Read_hfc(cs, HFCPCI_INT_S1));
242
243 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 2); /* HFC ST 2 */
244 udelay(10);
245 Write_hfc(cs, HFCPCI_STATES, 2); /* HFC ST 2 */
246 cs->hw.hfcpci.mst_m = HFCPCI_MASTER; /* HFC Master Mode */
247
248 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
249 cs->hw.hfcpci.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
250 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
251 cs->hw.hfcpci.sctrl_r = 0;
252 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
253
254 /* Init GCI/IOM2 in master mode */
255 /* Slots 0 and 1 are set for B-chan 1 and 2 */
256 /* D- and monitor/CI channel are not enabled */
257 /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */
258 /* STIO2 is used as data input, B1+B2 from IOM->ST */
259 /* ST B-channel send disabled -> continous 1s */
260 /* The IOM slots are always enabled */
261 cs->hw.hfcpci.conn = 0x36; /* set data flow directions */
262 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
263 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */
264 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */
265 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */
266 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */
267
268 /* Finally enable IRQ output */
269 cs->hw.hfcpci.int_m2 = HFCPCI_IRQ_ENABLE;
270 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
271 if (Read_hfc(cs, HFCPCI_INT_S2));
272 restore_flags(flags);
273 }
274
275 /***************************************************/
276 /* Timer function called when kernel timer expires */
277 /***************************************************/
278 static void
279 hfcpci_Timer(struct IsdnCardState *cs)
280 {
281 cs->hw.hfcpci.timer.expires = jiffies + 75;
282 /* WD RESET */
283 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcpci.ctmt | 0x80);
284 add_timer(&cs->hw.hfcpci.timer);
285 */
286 }
287
288
289 /*********************************/
290 /* schedule a new D-channel task */
291 /*********************************/
292 static void
293 sched_event_D_pci(struct IsdnCardState *cs, int event)
294 {
295 test_and_set_bit(event, &cs->event);
296 queue_task(&cs->tqueue, &tq_immediate);
297 mark_bh(IMMEDIATE_BH);
298 }
299
300 /*********************************/
301 /* schedule a new b_channel task */
302 /*********************************/
303 static void
304 hfcpci_sched_event(struct BCState *bcs, int event)
305 {
306 bcs->event |= 1 << event;
307 queue_task(&bcs->tqueue, &tq_immediate);
308 mark_bh(IMMEDIATE_BH);
309 }
310
311 /************************************************/
312 /* select a b-channel entry matching and active */
313 /************************************************/
314 static
315 struct BCState *
316 Sel_BCS(struct IsdnCardState *cs, int channel)
317 {
318 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
319 return (&cs->bcs[0]);
320 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
321 return (&cs->bcs[1]);
322 else
323 return (NULL);
324 }
325
326 /*********************************************/
327 /* read a complete B-frame out of the buffer */
328 /*********************************************/
329 static struct sk_buff
330 *
331 hfcpci_empty_fifo(struct BCState *bcs, bzfifo_type * bz, u_char * bdata, int count)
332 {
333 u_char *ptr, *ptr1, new_f2;
334 struct sk_buff *skb;
335 struct IsdnCardState *cs = bcs->cs;
336 int flags, total, maxlen, new_z2;
337 z_type *zp;
338
339 save_flags(flags);
340 sti();
341 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
342 debugl1(cs, "hfcpci_empty_fifo");
343 zp = &bz->za[bz->f2]; /* point to Z-Regs */
344 new_z2 = zp->z2 + count; /* new position in fifo */
345 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
346 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
347 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
348 if ((count > HSCX_BUFMAX + 3) || (count < 4) ||
349 (*(bdata + (zp->z1 - B_SUB_VAL)))) {
350 if (cs->debug & L1_DEB_WARN)
351 debugl1(cs, "hfcpci_empty_fifo: incoming packet invalid length %d or crc", count);
352 bz->za[new_f2].z2 = new_z2;
353 bz->f2 = new_f2; /* next buffer */
354 skb = NULL;
355 } else if (!(skb = dev_alloc_skb(count - 3)))
356 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
357 else {
358 total = count;
359 count -= 3;
360 ptr = skb_put(skb, count);
361
362 if (zp->z2 + count <= B_FIFO_SIZE + B_SUB_VAL)
363 maxlen = count; /* complete transfer */
364 else
365 maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2; /* maximum */
366
367 ptr1 = bdata + (zp->z2 - B_SUB_VAL); /* start of data */
368 memcpy(ptr, ptr1, maxlen); /* copy data */
369 count -= maxlen;
370
371 if (count) { /* rest remaining */
372 ptr += maxlen;
373 ptr1 = bdata; /* start of buffer */
374 memcpy(ptr, ptr1, count); /* rest */
375 }
376 bz->za[new_f2].z2 = new_z2;
377 bz->f2 = new_f2; /* next buffer */
378
379 }
380 restore_flags(flags);
381 return (skb);
382 }
383
384 /*******************************/
385 /* D-channel receive procedure */
386 /*******************************/
387 static
388 int
389 receive_dmsg(struct IsdnCardState *cs)
390 {
391 struct sk_buff *skb;
392 int maxlen;
393 int rcnt, total;
394 int count = 5;
395 u_char *ptr, *ptr1;
396 dfifo_type *df;
397 z_type *zp;
398
399 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_rx;
400 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
401 debugl1(cs, "rec_dmsg blocked");
402 return (1);
403 }
404 while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
405 zp = &df->za[df->f2 & D_FREG_MASK];
406 rcnt = zp->z1 - zp->z2;
407 if (rcnt < 0)
408 rcnt += D_FIFO_SIZE;
409 rcnt++;
410 if (cs->debug & L1_DEB_ISAC)
411 debugl1(cs, "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)",
412 df->f1, df->f2, zp->z1, zp->z2, rcnt);
413
414 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
415 (df->data[zp->z1])) {
416 if (cs->debug & L1_DEB_WARN)
417 debugl1(cs, "empty_fifo hfcpci paket inv. len %d or crc %d", rcnt, df->data[zp->z1]);
418 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1); /* next buffer */
419 df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + rcnt) & (D_FIFO_SIZE - 1);
420 } else if ((skb = dev_alloc_skb(rcnt - 3))) {
421 total = rcnt;
422 rcnt -= 3;
423 ptr = skb_put(skb, rcnt);
424
425 if (zp->z2 + rcnt <= D_FIFO_SIZE)
426 maxlen = rcnt; /* complete transfer */
427 else
428 maxlen = D_FIFO_SIZE - zp->z2; /* maximum */
429
430 ptr1 = df->data + zp->z2; /* start of data */
431 memcpy(ptr, ptr1, maxlen); /* copy data */
432 rcnt -= maxlen;
433
434 if (rcnt) { /* rest remaining */
435 ptr += maxlen;
436 ptr1 = df->data; /* start of buffer */
437 memcpy(ptr, ptr1, rcnt); /* rest */
438 }
439 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1); /* next buffer */
440 df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + total) & (D_FIFO_SIZE - 1);
441
442 skb_queue_tail(&cs->rq, skb);
443 sched_event_D_pci(cs, D_RCVBUFREADY);
444 } else
445 printk(KERN_WARNING "HFC-PCI: D receive out of memory\n");
446 }
447 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
448 return (1);
449 }
450
451 /*******************************************************************************/
452 /* check for transparent receive data and read max one threshold size if avail */
453 /*******************************************************************************/
454 int
455 hfcpci_empty_fifo_trans(struct BCState *bcs, bzfifo_type * bz, u_char * bdata)
456 {
457 unsigned short *z1r, *z2r;
458 int new_z2, fcnt, maxlen;
459 struct sk_buff *skb;
460 u_char *ptr, *ptr1;
461
462 z1r = &bz->za[MAX_B_FRAMES].z1; /* pointer to z reg */
463 z2r = z1r + 1;
464
465 if (!(fcnt = *z1r - *z2r))
466 return (0); /* no data avail */
467
468 if (fcnt <= 0)
469 fcnt += B_FIFO_SIZE; /* bytes actually buffered */
470 if (fcnt > HFCPCI_BTRANS_THRESHOLD)
471 fcnt = HFCPCI_BTRANS_THRESHOLD; /* limit size */
472
473 new_z2 = *z2r + fcnt; /* new position in fifo */
474 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
475 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
476
477 if (!(skb = dev_alloc_skb(fcnt)))
478 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
479 else {
480 ptr = skb_put(skb, fcnt);
481 if (*z2r + fcnt <= B_FIFO_SIZE + B_SUB_VAL)
482 maxlen = fcnt; /* complete transfer */
483 else
484 maxlen = B_FIFO_SIZE + B_SUB_VAL - *z2r; /* maximum */
485
486 ptr1 = bdata + (*z2r - B_SUB_VAL); /* start of data */
487 memcpy(ptr, ptr1, maxlen); /* copy data */
488 fcnt -= maxlen;
489
490 if (fcnt) { /* rest remaining */
491 ptr += maxlen;
492 ptr1 = bdata; /* start of buffer */
493 memcpy(ptr, ptr1, fcnt); /* rest */
494 }
495 cli();
496 skb_queue_tail(&bcs->rqueue, skb);
497 sti();
498 hfcpci_sched_event(bcs, B_RCVBUFREADY);
499 }
500
501 *z2r = new_z2; /* new position */
502 return (1);
503 } /* hfcpci_empty_fifo_trans */
504
505 /**********************************/
506 /* B-channel main receive routine */
507 /**********************************/
508 void
509 main_rec_hfcpci(struct BCState *bcs)
510 {
511 long flags;
512 struct IsdnCardState *cs = bcs->cs;
513 int rcnt;
514 int receive, count = 5;
515 struct sk_buff *skb;
516 bzfifo_type *bz;
517 u_char *bdata;
518 z_type *zp;
519
520
521 save_flags(flags);
522 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
523 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
524 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
525 } else {
526 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
527 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b1;
528 }
529 Begin:
530 count--;
531 cli();
532 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
533 debugl1(cs, "rec_data %d blocked", bcs->channel);
534 restore_flags(flags);
535 return;
536 }
537 sti();
538 if (bz->f1 != bz->f2) {
539 if (cs->debug & L1_DEB_HSCX)
540 debugl1(cs, "hfcpci rec %d f1(%d) f2(%d)",
541 bcs->channel, bz->f1, bz->f2);
542 zp = &bz->za[bz->f2];
543
544 rcnt = zp->z1 - zp->z2;
545 if (rcnt < 0)
546 rcnt += B_FIFO_SIZE;
547 rcnt++;
548 if (cs->debug & L1_DEB_HSCX)
549 debugl1(cs, "hfcpci rec %d z1(%x) z2(%x) cnt(%d)",
550 bcs->channel, zp->z1, zp->z2, rcnt);
551 if ((skb = hfcpci_empty_fifo(bcs, bz, bdata, rcnt))) {
552 cli();
553 skb_queue_tail(&bcs->rqueue, skb);
554 sti();
555 hfcpci_sched_event(bcs, B_RCVBUFREADY);
556 }
557 rcnt = bz->f1 - bz->f2;
558 if (rcnt < 0)
559 rcnt += MAX_B_FRAMES + 1;
560 if (rcnt > 1)
561 receive = 1;
562 else
563 receive = 0;
564 } else if (bcs->mode == L1_MODE_TRANS)
565 receive = hfcpci_empty_fifo_trans(bcs, bz, bdata);
566 else
567 receive = 0;
568 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
569 if (count && receive)
570 goto Begin;
571 restore_flags(flags);
572 return;
573 }
574
575 /**************************/
576 /* D-channel send routine */
577 /**************************/
578 static void
579 hfcpci_fill_dfifo(struct IsdnCardState *cs)
580 {
581 long flags;
582 int fcnt;
583 int count, new_z1, maxlen;
584 dfifo_type *df;
585 u_char *src, *dst, new_f1;
586
587 if (!cs->tx_skb)
588 return;
589 if (cs->tx_skb->len <= 0)
590 return;
591
592 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_tx;
593
594 if (cs->debug & L1_DEB_ISAC)
595 debugl1(cs, "hfcpci_fill_Dfifo f1(%d) f2(%d) z1(f1)(%x)",
596 df->f1, df->f2,
597 df->za[df->f1 & D_FREG_MASK].z1);
598 fcnt = df->f1 - df->f2; /* frame count actually buffered */
599 if (fcnt < 0)
600 fcnt += (MAX_D_FRAMES + 1); /* if wrap around */
601 if (fcnt > (MAX_D_FRAMES - 1)) {
602 if (cs->debug & L1_DEB_ISAC)
603 debugl1(cs, "hfcpci_fill_Dfifo more as 14 frames");
604 return;
605 }
606 /* now determine free bytes in FIFO buffer */
607 count = df->za[df->f1 & D_FREG_MASK].z2 - df->za[df->f1 & D_FREG_MASK].z1;
608 if (count <= 0)
609 count += D_FIFO_SIZE; /* count now contains available bytes */
610
611 if (cs->debug & L1_DEB_ISAC)
612 debugl1(cs, "hfcpci_fill_Dfifo count(%ld/%d)",
613 cs->tx_skb->len, count);
614 if (count < cs->tx_skb->len) {
615 if (cs->debug & L1_DEB_ISAC)
616 debugl1(cs, "hfcpci_fill_Dfifo no fifo mem");
617 return;
618 }
619 count = cs->tx_skb->len; /* get frame len */
620 new_z1 = (df->za[df->f1 & D_FREG_MASK].z1 + count) & (D_FIFO_SIZE - 1);
621 new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
622 src = cs->tx_skb->data; /* source pointer */
623 dst = df->data + df->za[df->f1 & D_FREG_MASK].z1;
624 maxlen = D_FIFO_SIZE - df->za[df->f1 & D_FREG_MASK].z1; /* end fifo */
625 if (maxlen > count)
626 maxlen = count; /* limit size */
627 memcpy(dst, src, maxlen); /* first copy */
628
629 count -= maxlen; /* remaining bytes */
630 if (count) {
631 dst = df->data; /* start of buffer */
632 src += maxlen; /* new position */
633 memcpy(dst, src, count);
634 }
635 save_flags(flags);
636 cli();
637 df->za[new_f1 & D_FREG_MASK].z1 = new_z1; /* for next buffer */
638 df->za[df->f1 & D_FREG_MASK].z1 = new_z1; /* new pos actual buffer */
639 df->f1 = new_f1; /* next frame */
640 restore_flags(flags);
641
642 dev_kfree_skb_any(cs->tx_skb);
643 cs->tx_skb = NULL;
644 return;
645 }
646
647 /**************************/
648 /* B-channel send routine */
649 /**************************/
650 static void
651 hfcpci_fill_fifo(struct BCState *bcs)
652 {
653 struct IsdnCardState *cs = bcs->cs;
654 int flags, maxlen, fcnt;
655 int count, new_z1;
656 bzfifo_type *bz;
657 u_char *bdata;
658 u_char new_f1, *src, *dst;
659 unsigned short *z1t, *z2t;
660
661 if (!bcs->tx_skb)
662 return;
663 if (bcs->tx_skb->len <= 0)
664 return;
665
666 save_flags(flags);
667 sti();
668
669 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) {
670 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
671 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b2;
672 } else {
673 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
674 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b1;
675 }
676
677 if (bcs->mode == L1_MODE_TRANS) {
678 z1t = &bz->za[MAX_B_FRAMES].z1;
679 z2t = z1t + 1;
680 if (cs->debug & L1_DEB_HSCX)
681 debugl1(cs, "hfcpci_fill_fifo_trans %d z1(%x) z2(%x)",
682 bcs->channel, *z1t, *z2t);
683 fcnt = *z2t - *z1t;
684 if (fcnt <= 0)
685 fcnt += B_FIFO_SIZE; /* fcnt contains available bytes in fifo */
686 fcnt = B_FIFO_SIZE - fcnt; /* remaining bytes to send */
687
688 while ((fcnt < 2 * HFCPCI_BTRANS_THRESHOLD) && (bcs->tx_skb)) {
689 if (bcs->tx_skb->len < B_FIFO_SIZE - fcnt) {
690 /* data is suitable for fifo */
691 count = bcs->tx_skb->len;
692
693 new_z1 = *z1t + count; /* new buffer Position */
694 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
695 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
696 src = bcs->tx_skb->data; /* source pointer */
697 dst = bdata + (*z1t - B_SUB_VAL);
698 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - *z1t; /* end of fifo */
699 if (maxlen > count)
700 maxlen = count; /* limit size */
701 memcpy(dst, src, maxlen); /* first copy */
702
703 count -= maxlen; /* remaining bytes */
704 if (count) {
705 dst = bdata; /* start of buffer */
706 src += maxlen; /* new position */
707 memcpy(dst, src, count);
708 }
709 bcs->tx_cnt -= bcs->tx_skb->len;
710 fcnt += bcs->tx_skb->len;
711 *z1t = new_z1; /* now send data */
712 } else if (cs->debug & L1_DEB_HSCX)
713 debugl1(cs, "hfcpci_fill_fifo_trans %d frame length %d discarded",
714 bcs->channel, bcs->tx_skb->len);
715
716 dev_kfree_skb_any(bcs->tx_skb);
717 cli();
718 bcs->tx_skb = skb_dequeue(&bcs->squeue); /* fetch next data */
719 sti();
720 }
721 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
722 restore_flags(flags);
723 return;
724 }
725 if (cs->debug & L1_DEB_HSCX)
726 debugl1(cs, "hfcpci_fill_fifo_hdlc %d f1(%d) f2(%d) z1(f1)(%x)",
727 bcs->channel, bz->f1, bz->f2,
728 bz->za[bz->f1].z1);
729
730 fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
731 if (fcnt < 0)
732 fcnt += (MAX_B_FRAMES + 1); /* if wrap around */
733 if (fcnt > (MAX_B_FRAMES - 1)) {
734 if (cs->debug & L1_DEB_HSCX)
735 debugl1(cs, "hfcpci_fill_Bfifo more as 14 frames");
736 restore_flags(flags);
737 return;
738 }
739 /* now determine free bytes in FIFO buffer */
740 count = bz->za[bz->f1].z2 - bz->za[bz->f1].z1;
741 if (count <= 0)
742 count += B_FIFO_SIZE; /* count now contains available bytes */
743
744 if (cs->debug & L1_DEB_HSCX)
745 debugl1(cs, "hfcpci_fill_fifo %d count(%ld/%d),%lx",
746 bcs->channel, bcs->tx_skb->len,
747 count, current->state);
748
749 if (count < bcs->tx_skb->len) {
750 if (cs->debug & L1_DEB_HSCX)
751 debugl1(cs, "hfcpci_fill_fifo no fifo mem");
752 restore_flags(flags);
753 return;
754 }
755 count = bcs->tx_skb->len; /* get frame len */
756 new_z1 = bz->za[bz->f1].z1 + count; /* new buffer Position */
757 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
758 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
759
760 new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
761 src = bcs->tx_skb->data; /* source pointer */
762 dst = bdata + (bz->za[bz->f1].z1 - B_SUB_VAL);
763 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - bz->za[bz->f1].z1; /* end fifo */
764 if (maxlen > count)
765 maxlen = count; /* limit size */
766 memcpy(dst, src, maxlen); /* first copy */
767
768 count -= maxlen; /* remaining bytes */
769 if (count) {
770 dst = bdata; /* start of buffer */
771 src += maxlen; /* new position */
772 memcpy(dst, src, count);
773 }
774 bcs->tx_cnt -= bcs->tx_skb->len;
775 if (bcs->st->lli.l1writewakeup &&
776 (PACKET_NOACK != bcs->tx_skb->pkt_type))
777 bcs->st->lli.l1writewakeup(bcs->st, bcs->tx_skb->len);
778
779 cli();
780 bz->za[new_f1].z1 = new_z1; /* for next buffer */
781 bz->f1 = new_f1; /* next frame */
782 restore_flags(flags);
783
784 dev_kfree_skb_any(bcs->tx_skb);
785 bcs->tx_skb = NULL;
786 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
787 return;
788 }
789
790 /**********************************************/
791 /* D-channel l1 state call for leased NT-mode */
792 /**********************************************/
793 static void
794 dch_nt_l2l1(struct PStack *st, int pr, void *arg)
795 {
796 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
797
798 switch (pr) {
799 case (PH_DATA | REQUEST):
800 case (PH_PULL | REQUEST):
801 case (PH_PULL | INDICATION):
802 st->l1.l1hw(st, pr, arg);
803 break;
804 case (PH_ACTIVATE | REQUEST):
805 st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
806 break;
807 case (PH_TESTLOOP | REQUEST):
808 if (1 & (long) arg)
809 debugl1(cs, "PH_TEST_LOOP B1");
810 if (2 & (long) arg)
811 debugl1(cs, "PH_TEST_LOOP B2");
812 if (!(3 & (long) arg))
813 debugl1(cs, "PH_TEST_LOOP DISABLED");
814 st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
815 break;
816 default:
817 if (cs->debug)
818 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
819 break;
820 }
821 }
822
823
824
825 /***********************/
826 /* set/reset echo mode */
827 /***********************/
828 static int
829 hfcpci_auxcmd(struct IsdnCardState *cs, isdn_ctrl * ic)
830 {
831 int flags;
832 int i = *(unsigned int *) ic->parm.num;
833
834 if ((ic->arg == 98) &&
835 (!(cs->hw.hfcpci.int_m1 & (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC + HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC)))) {
836 save_flags(flags);
837 cli();
838 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 0); /* HFC ST G0 */
839 udelay(10);
840 cs->hw.hfcpci.sctrl |= SCTRL_MODE_NT;
841 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); /* set NT-mode */
842 udelay(10);
843 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 1); /* HFC ST G1 */
844 udelay(10);
845 Write_hfc(cs, HFCPCI_STATES, 1 | HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
846 cs->dc.hfcpci.ph_state = 1;
847 cs->hw.hfcpci.nt_mode = 1;
848 cs->hw.hfcpci.nt_timer = 0;
849 cs->stlist->l2.l2l1 = dch_nt_l2l1;
850 restore_flags(flags);
851 debugl1(cs, "NT mode activated");
852 return (0);
853 }
854 if ((cs->chanlimit > 1) || (cs->hw.hfcpci.bswapped) ||
855 (cs->hw.hfcpci.nt_mode) || (ic->arg != 12))
856 return (-EINVAL);
857
858 save_flags(flags);
859 cli();
860 if (i) {
861 cs->logecho = 1;
862 cs->hw.hfcpci.trm |= 0x20; /* enable echo chan */
863 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_B2REC;
864 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2RX;
865 } else {
866 cs->logecho = 0;
867 cs->hw.hfcpci.trm &= ~0x20; /* disable echo chan */
868 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_B2REC;
869 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2RX;
870 }
871 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
872 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
873 cs->hw.hfcpci.conn |= 0x10; /* B2-IOM -> B2-ST */
874 cs->hw.hfcpci.ctmt &= ~2;
875 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
876 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
877 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
878 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
879 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
880 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
881 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
882 restore_flags(flags);
883 return (0);
884 } /* hfcpci_auxcmd */
885
886 /*****************************/
887 /* E-channel receive routine */
888 /*****************************/
889 static void
890 receive_emsg(struct IsdnCardState *cs)
891 {
892 long flags;
893 int rcnt;
894 int receive, count = 5;
895 bzfifo_type *bz;
896 u_char *bdata;
897 z_type *zp;
898 u_char *ptr, *ptr1, new_f2;
899 int total, maxlen, new_z2;
900 u_char e_buffer[256];
901
902 save_flags(flags);
903 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
904 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2;
905 Begin:
906 count--;
907 cli();
908 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
909 debugl1(cs, "echo_rec_data blocked");
910 restore_flags(flags);
911 return;
912 }
913 sti();
914 if (bz->f1 != bz->f2) {
915 if (cs->debug & L1_DEB_ISAC)
916 debugl1(cs, "hfcpci e_rec f1(%d) f2(%d)",
917 bz->f1, bz->f2);
918 zp = &bz->za[bz->f2];
919
920 rcnt = zp->z1 - zp->z2;
921 if (rcnt < 0)
922 rcnt += B_FIFO_SIZE;
923 rcnt++;
924 if (cs->debug & L1_DEB_ISAC)
925 debugl1(cs, "hfcpci e_rec z1(%x) z2(%x) cnt(%d)",
926 zp->z1, zp->z2, rcnt);
927 new_z2 = zp->z2 + rcnt; /* new position in fifo */
928 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
929 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
930 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
931 if ((rcnt > 256 + 3) || (count < 4) ||
932 (*(bdata + (zp->z1 - B_SUB_VAL)))) {
933 if (cs->debug & L1_DEB_WARN)
934 debugl1(cs, "hfcpci_empty_echan: incoming packet invalid length %d or crc", rcnt);
935 bz->za[new_f2].z2 = new_z2;
936 bz->f2 = new_f2; /* next buffer */
937 } else {
938 total = rcnt;
939 rcnt -= 3;
940 ptr = e_buffer;
941
942 if (zp->z2 <= B_FIFO_SIZE + B_SUB_VAL)
943 maxlen = rcnt; /* complete transfer */
944 else
945 maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2; /* maximum */
946
947 ptr1 = bdata + (zp->z2 - B_SUB_VAL); /* start of data */
948 memcpy(ptr, ptr1, maxlen); /* copy data */
949 rcnt -= maxlen;
950
951 if (rcnt) { /* rest remaining */
952 ptr += maxlen;
953 ptr1 = bdata; /* start of buffer */
954 memcpy(ptr, ptr1, rcnt); /* rest */
955 }
956 bz->za[new_f2].z2 = new_z2;
957 bz->f2 = new_f2; /* next buffer */
958 if (cs->debug & DEB_DLOG_HEX) {
959 ptr = cs->dlog;
960 if ((total - 3) < MAX_DLOG_SPACE / 3 - 10) {
961 *ptr++ = 'E';
962 *ptr++ = 'C';
963 *ptr++ = 'H';
964 *ptr++ = 'O';
965 *ptr++ = ':';
966 ptr += QuickHex(ptr, e_buffer, total - 3);
967 ptr--;
968 *ptr++ = '\n';
969 *ptr = 0;
970 HiSax_putstatus(cs, NULL, cs->dlog);
971 } else
972 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", total - 3);
973 }
974 }
975
976 rcnt = bz->f1 - bz->f2;
977 if (rcnt < 0)
978 rcnt += MAX_B_FRAMES + 1;
979 if (rcnt > 1)
980 receive = 1;
981 else
982 receive = 0;
983 } else
984 receive = 0;
985 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
986 if (count && receive)
987 goto Begin;
988 restore_flags(flags);
989 return;
990 } /* receive_emsg */
991
992 /*********************/
993 /* Interrupt handler */
994 /*********************/
995 static void
996 hfcpci_interrupt(int intno, void *dev_id, struct pt_regs *regs)
997 {
998 struct IsdnCardState *cs = dev_id;
999 u_char exval;
1000 struct BCState *bcs;
1001 int count = 15;
1002 long flags;
1003 u_char val, stat;
1004
1005 if (!cs) {
1006 printk(KERN_WARNING "HFC-PCI: Spurious interrupt!\n");
1007 return;
1008 }
1009 if (!(cs->hw.hfcpci.int_m2 & 0x08))
1010 return; /* not initialised */
1011
1012 if (HFCPCI_ANYINT & (stat = Read_hfc(cs, HFCPCI_STATUS))) {
1013 val = Read_hfc(cs, HFCPCI_INT_S1);
1014 if (cs->debug & L1_DEB_ISAC)
1015 debugl1(cs, "HFC-PCI: stat(%02x) s1(%02x)", stat, val);
1016 } else
1017 return;
1018
1019 if (cs->debug & L1_DEB_ISAC)
1020 debugl1(cs, "HFC-PCI irq %x %s", val,
1021 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
1022 "locked" : "unlocked");
1023 val &= cs->hw.hfcpci.int_m1;
1024 if (val & 0x40) { /* state machine irq */
1025 exval = Read_hfc(cs, HFCPCI_STATES) & 0xf;
1026 if (cs->debug & L1_DEB_ISAC)
1027 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcpci.ph_state,
1028 exval);
1029 cs->dc.hfcpci.ph_state = exval;
1030 sched_event_D_pci(cs, D_L1STATECHANGE);
1031 val &= ~0x40;
1032 }
1033 if (val & 0x80) { /* timer irq */
1034 if (cs->hw.hfcpci.nt_mode) {
1035 if ((--cs->hw.hfcpci.nt_timer) < 0)
1036 sched_event_D_pci(cs, D_L1STATECHANGE);
1037 }
1038 val &= ~0x80;
1039 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1040 }
1041 while (val) {
1042 save_flags(flags);
1043 cli();
1044 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1045 cs->hw.hfcpci.int_s1 |= val;
1046 restore_flags(flags);
1047 return;
1048 }
1049 if (cs->hw.hfcpci.int_s1 & 0x18) {
1050 exval = val;
1051 val = cs->hw.hfcpci.int_s1;
1052 cs->hw.hfcpci.int_s1 = exval;
1053 }
1054 if (val & 0x08) {
1055 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
1056 if (cs->debug)
1057 debugl1(cs, "hfcpci spurious 0x08 IRQ");
1058 } else
1059 main_rec_hfcpci(bcs);
1060 }
1061 if (val & 0x10) {
1062 if (cs->logecho)
1063 receive_emsg(cs);
1064 else if (!(bcs = Sel_BCS(cs, 1))) {
1065 if (cs->debug)
1066 debugl1(cs, "hfcpci spurious 0x10 IRQ");
1067 } else
1068 main_rec_hfcpci(bcs);
1069 }
1070 if (val & 0x01) {
1071 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) {
1072 if (cs->debug)
1073 debugl1(cs, "hfcpci spurious 0x01 IRQ");
1074 } else {
1075 if (bcs->tx_skb) {
1076 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1077 hfcpci_fill_fifo(bcs);
1078 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1079 } else
1080 debugl1(cs, "fill_data %d blocked", bcs->channel);
1081 } else {
1082 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
1083 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1084 hfcpci_fill_fifo(bcs);
1085 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1086 } else
1087 debugl1(cs, "fill_data %d blocked", bcs->channel);
1088 } else {
1089 hfcpci_sched_event(bcs, B_XMTBUFREADY);
1090 }
1091 }
1092 }
1093 }
1094 if (val & 0x02) {
1095 if (!(bcs = Sel_BCS(cs, 1))) {
1096 if (cs->debug)
1097 debugl1(cs, "hfcpci spurious 0x02 IRQ");
1098 } else {
1099 if (bcs->tx_skb) {
1100 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1101 hfcpci_fill_fifo(bcs);
1102 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1103 } else
1104 debugl1(cs, "fill_data %d blocked", bcs->channel);
1105 } else {
1106 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
1107 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1108 hfcpci_fill_fifo(bcs);
1109 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1110 } else
1111 debugl1(cs, "fill_data %d blocked", bcs->channel);
1112 } else {
1113 hfcpci_sched_event(bcs, B_XMTBUFREADY);
1114 }
1115 }
1116 }
1117 }
1118 if (val & 0x20) { /* receive dframe */
1119 receive_dmsg(cs);
1120 }
1121 if (val & 0x04) { /* dframe transmitted */
1122 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
1123 del_timer(&cs->dbusytimer);
1124 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
1125 sched_event_D_pci(cs, D_CLEARBUSY);
1126 if (cs->tx_skb) {
1127 if (cs->tx_skb->len) {
1128 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1129 hfcpci_fill_dfifo(cs);
1130 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1131 } else {
1132 debugl1(cs, "hfcpci_fill_dfifo irq blocked");
1133 }
1134 goto afterXPR;
1135 } else {
1136 dev_kfree_skb_irq(cs->tx_skb);
1137 cs->tx_cnt = 0;
1138 cs->tx_skb = NULL;
1139 }
1140 }
1141 if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
1142 cs->tx_cnt = 0;
1143 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1144 hfcpci_fill_dfifo(cs);
1145 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1146 } else {
1147 debugl1(cs, "hfcpci_fill_dfifo irq blocked");
1148 }
1149 } else
1150 sched_event_D_pci(cs, D_XMTBUFREADY);
1151 }
1152 afterXPR:
1153 if (cs->hw.hfcpci.int_s1 && count--) {
1154 val = cs->hw.hfcpci.int_s1;
1155 cs->hw.hfcpci.int_s1 = 0;
1156 if (cs->debug & L1_DEB_ISAC)
1157 debugl1(cs, "HFC-PCI irq %x loop %d", val, 15 - count);
1158 } else
1159 val = 0;
1160 restore_flags(flags);
1161 }
1162 }
1163
1164 /********************************************************************/
1165 /* timer callback for D-chan busy resolution. Currently no function */
1166 /********************************************************************/
1167 static void
1168 hfcpci_dbusy_timer(struct IsdnCardState *cs)
1169 {
1170 }
1171
1172 /*************************************/
1173 /* Layer 1 D-channel hardware access */
1174 /*************************************/
1175 static void
1176 HFCPCI_l1hw(struct PStack *st, int pr, void *arg)
1177 {
1178 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
1179 struct sk_buff *skb = arg;
1180 int flags;
1181
1182 switch (pr) {
1183 case (PH_DATA | REQUEST):
1184 if (cs->debug & DEB_DLOG_HEX)
1185 LogFrame(cs, skb->data, skb->len);
1186 if (cs->debug & DEB_DLOG_VERBOSE)
1187 dlogframe(cs, skb, 0);
1188 if (cs->tx_skb) {
1189 skb_queue_tail(&cs->sq, skb);
1190 #ifdef L2FRAME_DEBUG /* psa */
1191 if (cs->debug & L1_DEB_LAPD)
1192 Logl2Frame(cs, skb, "PH_DATA Queued", 0);
1193 #endif
1194 } else {
1195 cs->tx_skb = skb;
1196 cs->tx_cnt = 0;
1197 #ifdef L2FRAME_DEBUG /* psa */
1198 if (cs->debug & L1_DEB_LAPD)
1199 Logl2Frame(cs, skb, "PH_DATA", 0);
1200 #endif
1201 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1202 hfcpci_fill_dfifo(cs);
1203 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1204 } else
1205 debugl1(cs, "hfcpci_fill_dfifo blocked");
1206
1207 }
1208 break;
1209 case (PH_PULL | INDICATION):
1210 if (cs->tx_skb) {
1211 if (cs->debug & L1_DEB_WARN)
1212 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
1213 skb_queue_tail(&cs->sq, skb);
1214 break;
1215 }
1216 if (cs->debug & DEB_DLOG_HEX)
1217 LogFrame(cs, skb->data, skb->len);
1218 if (cs->debug & DEB_DLOG_VERBOSE)
1219 dlogframe(cs, skb, 0);
1220 cs->tx_skb = skb;
1221 cs->tx_cnt = 0;
1222 #ifdef L2FRAME_DEBUG /* psa */
1223 if (cs->debug & L1_DEB_LAPD)
1224 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
1225 #endif
1226 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1227 hfcpci_fill_dfifo(cs);
1228 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1229 } else
1230 debugl1(cs, "hfcpci_fill_dfifo blocked");
1231 break;
1232 case (PH_PULL | REQUEST):
1233 #ifdef L2FRAME_DEBUG /* psa */
1234 if (cs->debug & L1_DEB_LAPD)
1235 debugl1(cs, "-> PH_REQUEST_PULL");
1236 #endif
1237 if (!cs->tx_skb) {
1238 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1239 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1240 } else
1241 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1242 break;
1243 case (HW_RESET | REQUEST):
1244 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3); /* HFC ST 3 */
1245 udelay(6);
1246 Write_hfc(cs, HFCPCI_STATES, 3); /* HFC ST 2 */
1247 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1248 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1249 Write_hfc(cs, HFCPCI_STATES, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
1250 l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
1251 break;
1252 case (HW_ENABLE | REQUEST):
1253 Write_hfc(cs, HFCPCI_STATES, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION);
1254 break;
1255 case (HW_DEACTIVATE | REQUEST):
1256 cs->hw.hfcpci.mst_m &= ~HFCPCI_MASTER;
1257 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1258 break;
1259 case (HW_INFO3 | REQUEST):
1260 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER;
1261 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1262 break;
1263 case (HW_TESTLOOP | REQUEST):
1264 switch ((int) arg) {
1265 case (1):
1266 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* tx slot */
1267 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* rx slot */
1268 save_flags(flags);
1269 cli();
1270 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~7) | 1;
1271 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1272 restore_flags(flags);
1273 break;
1274
1275 case (2):
1276 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* tx slot */
1277 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* rx slot */
1278 save_flags(flags);
1279 cli();
1280 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~0x38) | 0x08;
1281 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1282 restore_flags(flags);
1283 break;
1284
1285 default:
1286 if (cs->debug & L1_DEB_WARN)
1287 debugl1(cs, "hfcpci_l1hw loop invalid %4x", (int) arg);
1288 return;
1289 }
1290 save_flags(flags);
1291 cli();
1292 cs->hw.hfcpci.trm |= 0x80; /* enable IOM-loop */
1293 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm);
1294 restore_flags(flags);
1295 break;
1296 default:
1297 if (cs->debug & L1_DEB_WARN)
1298 debugl1(cs, "hfcpci_l1hw unknown pr %4x", pr);
1299 break;
1300 }
1301 }
1302
1303 /***********************************************/
1304 /* called during init setting l1 stack pointer */
1305 /***********************************************/
1306 void
1307 setstack_hfcpci(struct PStack *st, struct IsdnCardState *cs)
1308 {
1309 st->l1.l1hw = HFCPCI_l1hw;
1310 }
1311
1312 /**************************************/
1313 /* send B-channel data if not blocked */
1314 /**************************************/
1315 static void
1316 hfcpci_send_data(struct BCState *bcs)
1317 {
1318 struct IsdnCardState *cs = bcs->cs;
1319
1320 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1321 hfcpci_fill_fifo(bcs);
1322 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1323 } else
1324 debugl1(cs, "send_data %d blocked", bcs->channel);
1325 }
1326
1327 /***************************************************************/
1328 /* activate/deactivate hardware for selected channels and mode */
1329 /***************************************************************/
1330 void
1331 mode_hfcpci(struct BCState *bcs, int mode, int bc)
1332 {
1333 struct IsdnCardState *cs = bcs->cs;
1334 bzfifo_type *bzr, *bzt;
1335 int flags, fifo2;
1336
1337 if (cs->debug & L1_DEB_HSCX)
1338 debugl1(cs, "HFCPCI bchannel mode %d bchan %d/%d",
1339 mode, bc, bcs->channel);
1340 bcs->mode = mode;
1341 bcs->channel = bc;
1342 fifo2 = bc;
1343 save_flags(flags);
1344 cli();
1345 if (cs->chanlimit > 1) {
1346 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1347 cs->hw.hfcpci.sctrl_e &= ~0x80;
1348 } else {
1349 if (bc) {
1350 if (mode != L1_MODE_NULL) {
1351 cs->hw.hfcpci.bswapped = 1; /* B1 and B2 exchanged */
1352 cs->hw.hfcpci.sctrl_e |= 0x80;
1353 } else {
1354 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1355 cs->hw.hfcpci.sctrl_e &= ~0x80;
1356 }
1357 fifo2 = 0;
1358 } else {
1359 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */
1360 cs->hw.hfcpci.sctrl_e &= ~0x80;
1361 }
1362 }
1363 switch (mode) {
1364 case (L1_MODE_NULL):
1365 if (bc) {
1366 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA;
1367 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA;
1368 } else {
1369 cs->hw.hfcpci.sctrl &= ~SCTRL_B1_ENA;
1370 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B1_ENA;
1371 }
1372 if (fifo2) {
1373 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1374 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1375 } else {
1376 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1377 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1378 }
1379 break;
1380 case (L1_MODE_TRANS):
1381 if (bc) {
1382 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1383 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1384 } else {
1385 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1386 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1387 }
1388 if (fifo2) {
1389 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1390 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1391 cs->hw.hfcpci.ctmt |= 2;
1392 cs->hw.hfcpci.conn &= ~0x18;
1393 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2;
1394 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2;
1395 } else {
1396 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1397 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1398 cs->hw.hfcpci.ctmt |= 1;
1399 cs->hw.hfcpci.conn &= ~0x03;
1400 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1;
1401 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1;
1402 }
1403 bzr->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
1404 bzr->za[MAX_B_FRAMES].z2 = bzr->za[MAX_B_FRAMES].z1;
1405 bzr->f1 = MAX_B_FRAMES;
1406 bzr->f2 = bzr->f1; /* init F pointers to remain constant */
1407 bzt->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1;
1408 bzt->za[MAX_B_FRAMES].z2 = bzt->za[MAX_B_FRAMES].z1;
1409 bzt->f1 = MAX_B_FRAMES;
1410 bzt->f2 = bzt->f1; /* init F pointers to remain constant */
1411 break;
1412 case (L1_MODE_HDLC):
1413 if (bc) {
1414 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1415 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1416 } else {
1417 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1418 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1419 }
1420 if (fifo2) {
1421 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2;
1422 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1423 cs->hw.hfcpci.ctmt &= ~2;
1424 cs->hw.hfcpci.conn &= ~0x18;
1425 } else {
1426 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1;
1427 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1428 cs->hw.hfcpci.ctmt &= ~1;
1429 cs->hw.hfcpci.conn &= ~0x03;
1430 }
1431 break;
1432 case (L1_MODE_EXTRN):
1433 if (bc) {
1434 cs->hw.hfcpci.conn |= 0x10;
1435 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA;
1436 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA;
1437 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2;
1438 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC);
1439 } else {
1440 cs->hw.hfcpci.conn |= 0x02;
1441 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA;
1442 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA;
1443 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1;
1444 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC);
1445 }
1446 break;
1447 }
1448 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e);
1449 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1450 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en);
1451 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl);
1452 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r);
1453 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt);
1454 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn);
1455 restore_flags(flags);
1456 }
1457
1458 /******************************/
1459 /* Layer2 -> Layer 1 Transfer */
1460 /******************************/
1461 static void
1462 hfcpci_l2l1(struct PStack *st, int pr, void *arg)
1463 {
1464 struct sk_buff *skb = arg;
1465 long flags;
1466
1467 switch (pr) {
1468 case (PH_DATA | REQUEST):
1469 save_flags(flags);
1470 cli();
1471 if (st->l1.bcs->tx_skb) {
1472 skb_queue_tail(&st->l1.bcs->squeue, skb);
1473 restore_flags(flags);
1474 } else {
1475 st->l1.bcs->tx_skb = skb;
1476 /* test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1477 */ st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
1478 restore_flags(flags);
1479 }
1480 break;
1481 case (PH_PULL | INDICATION):
1482 if (st->l1.bcs->tx_skb) {
1483 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
1484 break;
1485 }
1486 save_flags(flags);
1487 cli();
1488 /* test_and_set_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1489 */ st->l1.bcs->tx_skb = skb;
1490 st->l1.bcs->cs->BC_Send_Data(st->l1.bcs);
1491 restore_flags(flags);
1492 break;
1493 case (PH_PULL | REQUEST):
1494 if (!st->l1.bcs->tx_skb) {
1495 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1496 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1497 } else
1498 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1499 break;
1500 case (PH_ACTIVATE | REQUEST):
1501 test_and_set_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1502 mode_hfcpci(st->l1.bcs, st->l1.mode, st->l1.bc);
1503 l1_msg_b(st, pr, arg);
1504 break;
1505 case (PH_DEACTIVATE | REQUEST):
1506 l1_msg_b(st, pr, arg);
1507 break;
1508 case (PH_DEACTIVATE | CONFIRM):
1509 test_and_clear_bit(BC_FLG_ACTIV, &st->l1.bcs->Flag);
1510 test_and_clear_bit(BC_FLG_BUSY, &st->l1.bcs->Flag);
1511 mode_hfcpci(st->l1.bcs, 0, st->l1.bc);
1512 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1513 break;
1514 }
1515 }
1516
1517 /******************************************/
1518 /* deactivate B-channel access and queues */
1519 /******************************************/
1520 static void
1521 close_hfcpci(struct BCState *bcs)
1522 {
1523 mode_hfcpci(bcs, 0, bcs->channel);
1524 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1525 discard_queue(&bcs->rqueue);
1526 discard_queue(&bcs->squeue);
1527 if (bcs->tx_skb) {
1528 dev_kfree_skb_any(bcs->tx_skb);
1529 bcs->tx_skb = NULL;
1530 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1531 }
1532 }
1533 }
1534
1535 /*************************************/
1536 /* init B-channel queues and control */
1537 /*************************************/
1538 static int
1539 open_hfcpcistate(struct IsdnCardState *cs, struct BCState *bcs)
1540 {
1541 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1542 skb_queue_head_init(&bcs->rqueue);
1543 skb_queue_head_init(&bcs->squeue);
1544 }
1545 bcs->tx_skb = NULL;
1546 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1547 bcs->event = 0;
1548 bcs->tx_cnt = 0;
1549 return (0);
1550 }
1551
1552 /*********************************/
1553 /* inits the stack for B-channel */
1554 /*********************************/
1555 static int
1556 setstack_2b(struct PStack *st, struct BCState *bcs)
1557 {
1558 bcs->channel = st->l1.bc;
1559 if (open_hfcpcistate(st->l1.hardware, bcs))
1560 return (-1);
1561 st->l1.bcs = bcs;
1562 st->l2.l2l1 = hfcpci_l2l1;
1563 setstack_manager(st);
1564 bcs->st = st;
1565 setstack_l1_B(st);
1566 return (0);
1567 }
1568
1569 /***************************/
1570 /* handle L1 state changes */
1571 /***************************/
1572 static void
1573 hfcpci_bh(struct IsdnCardState *cs)
1574 {
1575 int flags;
1576 /* struct PStack *stptr;
1577 */
1578 if (!cs)
1579 return;
1580 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
1581 if (!cs->hw.hfcpci.nt_mode)
1582 switch (cs->dc.hfcpci.ph_state) {
1583 case (0):
1584 l1_msg(cs, HW_RESET | INDICATION, NULL);
1585 break;
1586 case (3):
1587 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
1588 break;
1589 case (8):
1590 l1_msg(cs, HW_RSYNC | INDICATION, NULL);
1591 break;
1592 case (6):
1593 l1_msg(cs, HW_INFO2 | INDICATION, NULL);
1594 break;
1595 case (7):
1596 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
1597 break;
1598 default:
1599 break;
1600 } else {
1601 switch (cs->dc.hfcpci.ph_state) {
1602 case (2):
1603 save_flags(flags);
1604 cli();
1605 if (cs->hw.hfcpci.nt_timer < 0) {
1606 cs->hw.hfcpci.nt_timer = 0;
1607 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1608 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1609 /* Clear already pending ints */
1610 if (Read_hfc(cs, HFCPCI_INT_S1));
1611
1612 Write_hfc(cs, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
1613 udelay(10);
1614 Write_hfc(cs, HFCPCI_STATES, 4);
1615 cs->dc.hfcpci.ph_state = 4;
1616 } else {
1617 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_TIMER;
1618 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1619 cs->hw.hfcpci.ctmt &= ~HFCPCI_AUTO_TIMER;
1620 cs->hw.hfcpci.ctmt |= HFCPCI_TIM3_125;
1621 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1622 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER);
1623 cs->hw.hfcpci.nt_timer = NT_T1_COUNT;
1624 Write_hfc(cs, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3); /* allow G2 -> G3 transition */
1625 }
1626 restore_flags(flags);
1627 break;
1628 case (1):
1629 case (3):
1630 case (4):
1631 save_flags(flags);
1632 cli();
1633 cs->hw.hfcpci.nt_timer = 0;
1634 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1635 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1636 restore_flags(flags);
1637 break;
1638 default:
1639 break;
1640 }
1641 }
1642 }
1643 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
1644 DChannel_proc_rcv(cs);
1645 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
1646 DChannel_proc_xmt(cs);
1647 }
1648
1649
1650 /********************************/
1651 /* called for card init message */
1652 /********************************/
1653 __initfunc(void
1654 inithfcpci(struct IsdnCardState *cs))
1655 {
1656 cs->setstack_d = setstack_hfcpci;
1657 cs->dbusytimer.function = (void *) hfcpci_dbusy_timer;
1658 cs->dbusytimer.data = (long) cs;
1659 init_timer(&cs->dbusytimer);
1660 cs->tqueue.routine = (void *) (void *) hfcpci_bh;
1661 cs->BC_Send_Data = &hfcpci_send_data;
1662 cs->bcs[0].BC_SetStack = setstack_2b;
1663 cs->bcs[1].BC_SetStack = setstack_2b;
1664 cs->bcs[0].BC_Close = close_hfcpci;
1665 cs->bcs[1].BC_Close = close_hfcpci;
1666 mode_hfcpci(cs->bcs, 0, 0);
1667 mode_hfcpci(cs->bcs + 1, 0, 1);
1668 }
1669
1670
1671
1672 /*******************************************/
1673 /* handle card messages from control layer */
1674 /*******************************************/
1675 static int
1676 hfcpci_card_msg(struct IsdnCardState *cs, int mt, void *arg)
1677 {
1678 long flags;
1679
1680 if (cs->debug & L1_DEB_ISAC)
1681 debugl1(cs, "HFCPCI: card_msg %x", mt);
1682 switch (mt) {
1683 case CARD_RESET:
1684 reset_hfcpci(cs);
1685 return (0);
1686 case CARD_RELEASE:
1687 release_io_hfcpci(cs);
1688 return (0);
1689 case CARD_INIT:
1690 inithfcpci(cs);
1691 save_flags(flags);
1692 sti();
1693 set_current_state(TASK_UNINTERRUPTIBLE);
1694 schedule_timeout((80 * HZ) / 1000); /* Timeout 80ms */
1695 /* now switch timer interrupt off */
1696 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER;
1697 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1698 /* reinit mode reg */
1699 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m);
1700 restore_flags(flags);
1701 return (0);
1702 case CARD_TEST:
1703 return (0);
1704 }
1705 return (0);
1706 }
1707
1708
1709 /* this variable is used as card index when more than one cards are present */
1710 static struct pci_dev *dev_hfcpci __initdata = NULL;
1711
1712 #endif /* CONFIG_PCI */
1713
1714 __initfunc(int
1715 setup_hfcpci(struct IsdnCard *card))
1716 {
1717 struct IsdnCardState *cs = card->cs;
1718 unsigned short cmd;
1719 char tmp[64];
1720 int i;
1721 struct pci_dev *tmp_hfcpci = NULL;
1722
1723 strcpy(tmp, hfcpci_revision);
1724 printk(KERN_INFO "HiSax: HFC-PCI driver Rev. %s\n", HiSax_getrev(tmp));
1725 #if CONFIG_PCI
1726 cs->hw.hfcpci.int_s1 = 0;
1727 cs->dc.hfcpci.ph_state = 0;
1728 cs->hw.hfcpci.fifo = 255;
1729 if (cs->typ == ISDN_CTYPE_HFC_PCI) {
1730 if (!pci_present()) {
1731 printk(KERN_ERR "HFC-PCI: no PCI bus present\n");
1732 return (0);
1733 }
1734 i = 0;
1735 while (id_list[i].vendor_id) {
1736 tmp_hfcpci = pci_find_device(id_list[i].vendor_id,
1737 id_list[i].device_id,
1738 dev_hfcpci);
1739 i++;
1740 if (tmp_hfcpci) {
1741 if ((card->para[0]) && (card->para[0] != (tmp_hfcpci->resource[ 0].start & PCI_BASE_ADDRESS_IO_MASK)))
1742 continue;
1743 else
1744 break;
1745 }
1746 }
1747
1748 if (tmp_hfcpci) {
1749 i--;
1750 dev_hfcpci = tmp_hfcpci; /* old device */
1751 cs->hw.hfcpci.pci_bus = dev_hfcpci->bus->number;
1752 cs->hw.hfcpci.pci_device_fn = dev_hfcpci->devfn;
1753 cs->irq = dev_hfcpci->irq;
1754 if (!cs->irq) {
1755 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
1756 return (0);
1757 }
1758 cs->hw.hfcpci.pci_io = (char *) dev_hfcpci->resource[ 1].start;
1759 printk(KERN_INFO "HiSax: HFC-PCI card manufacturer: %s card name: %s\n", id_list[i].vendor_name, id_list[i].card_name);
1760 } else {
1761 printk(KERN_WARNING "HFC-PCI: No PCI card found\n");
1762 return (0);
1763 }
1764 if (((int) cs->hw.hfcpci.pci_io & (PAGE_SIZE - 1))) {
1765 printk(KERN_WARNING "HFC-PCI shared mem address will be corrected\n");
1766 pcibios_write_config_word(cs->hw.hfcpci.pci_bus,
1767 cs->hw.hfcpci.pci_device_fn,
1768 PCI_COMMAND,
1769 0x0103); /* set SERR */
1770 pcibios_read_config_word(cs->hw.hfcpci.pci_bus,
1771 cs->hw.hfcpci.pci_device_fn,
1772 PCI_COMMAND,
1773 &cmd);
1774 pcibios_write_config_word(cs->hw.hfcpci.pci_bus,
1775 cs->hw.hfcpci.pci_device_fn,
1776 PCI_COMMAND,
1777 cmd & ~2);
1778 (int) cs->hw.hfcpci.pci_io &= ~(PAGE_SIZE - 1);
1779 pcibios_write_config_dword(cs->hw.hfcpci.pci_bus,
1780 cs->hw.hfcpci.pci_device_fn,
1781 PCI_BASE_ADDRESS_1,
1782 (int) cs->hw.hfcpci.pci_io);
1783 pcibios_write_config_word(cs->hw.hfcpci.pci_bus,
1784 cs->hw.hfcpci.pci_device_fn,
1785 PCI_COMMAND,
1786 cmd);
1787 pcibios_read_config_dword(cs->hw.hfcpci.pci_bus,
1788 cs->hw.hfcpci.pci_device_fn,
1789 PCI_BASE_ADDRESS_1,
1790 (void *) &cs->hw.hfcpci.pci_io);
1791 if (((int) cs->hw.hfcpci.pci_io & (PAGE_SIZE - 1))) {
1792 printk(KERN_WARNING "HFC-PCI unable to align address %x\n", (unsigned) cs->hw.hfcpci.pci_io);
1793 return (0);
1794 }
1795 dev_hfcpci->resource[1].start = (int) cs->hw.hfcpci.pci_io;
1796 }
1797 if (!cs->hw.hfcpci.pci_io) {
1798 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
1799 return (0);
1800 }
1801 /* Allocate memory for FIFOS */
1802 /* Because the HFC-PCI needs a 32K physical alignment, we */
1803 /* need to allocate the double mem and align the address */
1804 if (!((void *) cs->hw.hfcpci.share_start = kmalloc(65536, GFP_KERNEL))) {
1805 printk(KERN_WARNING "HFC-PCI: Error allocating memory for FIFO!\n");
1806 return 0;
1807 }
1808 (ulong) cs->hw.hfcpci.fifos =
1809 (((ulong) cs->hw.hfcpci.share_start) & ~0x7FFF) + 0x8000;
1810 pcibios_write_config_dword(cs->hw.hfcpci.pci_bus,
1811 cs->hw.hfcpci.pci_device_fn, 0x80,
1812 (u_int) virt_to_bus(cs->hw.hfcpci.fifos));
1813 cs->hw.hfcpci.pci_io = ioremap((ulong) cs->hw.hfcpci.pci_io, 256);
1814 printk(KERN_INFO
1815 "HFC-PCI: defined at mem %#x fifo %#x(%#x) IRQ %d HZ %d\n",
1816 (u_int) cs->hw.hfcpci.pci_io,
1817 (u_int) cs->hw.hfcpci.fifos,
1818 (u_int) virt_to_bus(cs->hw.hfcpci.fifos),
1819 cs->irq, HZ);
1820 pcibios_write_config_word(cs->hw.hfcpci.pci_bus, cs->hw.hfcpci.pci_device_fn, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped ports, disable busmaster */
1821 cs->hw.hfcpci.int_m2 = 0; /* disable alle interrupts */
1822 cs->hw.hfcpci.int_m1 = 0;
1823 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1);
1824 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2);
1825 /* At this point the needed PCI config is done */
1826 /* fifos are still not enabled */
1827 } else
1828 return (0); /* no valid card type */
1829
1830
1831 cs->readisac = NULL;
1832 cs->writeisac = NULL;
1833 cs->readisacfifo = NULL;
1834 cs->writeisacfifo = NULL;
1835 cs->BC_Read_Reg = NULL;
1836 cs->BC_Write_Reg = NULL;
1837 cs->irq_func = &hfcpci_interrupt;
1838 cs->irq_flags |= SA_SHIRQ;
1839
1840 cs->hw.hfcpci.timer.function = (void *) hfcpci_Timer;
1841 cs->hw.hfcpci.timer.data = (long) cs;
1842 init_timer(&cs->hw.hfcpci.timer);
1843
1844 reset_hfcpci(cs);
1845 cs->cardmsg = &hfcpci_card_msg;
1846 cs->auxcmd = &hfcpci_auxcmd;
1847 return (1);
1848 #else
1849 printk(KERN_WARNING "HFC-PCI: NO_PCI_BIOS\n");
1850 return (0);
1851 #endif /* CONFIG_PCI */
1852 }
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