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Import 2.3.48
[davej-history.git] / drivers / block / sis5513.c
blob942187900337f37f60aff86bd7a0c9f31b1b6b6b
1 /*
2 * linux/drivers/block/sis5513.c Version 0.09 Feb. 10, 2000
3 *
4 * Copyright (C) 1999-2000 Andre Hedrick (andre@suse.com)
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * Thanks to SIS Taiwan for direct support and hardware.
8 * Tested and designed on the SiS620/5513 chipset.
9 */
10
11 #include <linux/config.h>
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/timer.h>
16 #include <linux/mm.h>
17 #include <linux/ioport.h>
18 #include <linux/blkdev.h>
19 #include <linux/hdreg.h>
20
21 #include <linux/interrupt.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
24 #include <linux/ide.h>
25
26 #include <asm/io.h>
27 #include <asm/irq.h>
28
29 #include "ide_modes.h"
30
31 #define DISPLAY_SIS_TIMINGS
32 #define SIS5513_DEBUG_DRIVE_INFO 0
33
34 static struct pci_dev *host_dev = NULL;
35
36 #define arraysize(x) (sizeof(x)/sizeof(*(x)))
37
38 #define SIS5513_FLAG_ATA_00 0x00000000
39 #define SIS5513_FLAG_ATA_16 0x00000001
40 #define SIS5513_FLAG_ATA_33 0x00000002
41 #define SIS5513_FLAG_ATA_66 0x00000004
42 #define SIS5513_FLAG_LATENCY 0x00000010
43
44 static const struct {
45 const char *name;
46 unsigned short host_id;
47 unsigned int flags;
48 } SiSHostChipInfo[] = {
49 { "SiS530", PCI_DEVICE_ID_SI_530, SIS5513_FLAG_ATA_66, },
50 { "SiS540", PCI_DEVICE_ID_SI_540, SIS5513_FLAG_ATA_66, },
51 { "SiS620", PCI_DEVICE_ID_SI_620, SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
52 { "SiS630", PCI_DEVICE_ID_SI_630, SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
53 { "SiS5591", PCI_DEVICE_ID_SI_5591, SIS5513_FLAG_ATA_33, },
54 { "SiS5597", PCI_DEVICE_ID_SI_5597, SIS5513_FLAG_ATA_33, },
55 { "SiS5600", PCI_DEVICE_ID_SI_5600, SIS5513_FLAG_ATA_33, },
56 { "SiS5511", PCI_DEVICE_ID_SI_5511, SIS5513_FLAG_ATA_16, },
57 };
58
59 #if 0
60
61 static struct _pio_mode_mapping {
62 byte data_active;
63 byte recovery;
64 byte pio_mode;
65 } pio_mode_mapping[] = {
66 { 8, 12, 0 },
67 { 6, 7, 1 },
68 { 4, 4, 2 },
69 { 3, 3, 3 },
70 { 3, 1, 4 }
71 };
72
73 static struct _dma_mode_mapping {
74 byte data_active;
75 byte recovery;
76 byte dma_mode;
77 } dma_mode_mapping[] = {
78 { 8, 8, 0 },
79 { 3, 2, 1 },
80 { 3, 1, 2 }
81 };
82
83 static struct _udma_mode_mapping {
84 byte cycle_time;
85 char * udma_mode;
86 } udma_mode_mapping[] = {
87 { 8, "Mode 0" },
88 { 6, "Mode 1" },
89 { 4, "Mode 2" },
90 { 3, "Mode 3" },
91 { 2, "Mode 4" },
92 { 0, "Undefined" }
93 };
94
95 static __inline__ char * find_udma_mode (byte cycle_time)
96 {
97 int n;
98
99 for (n = 0; n <= 4; n++)
100 if (udma_mode_mapping[n].cycle_time <= cycle_time)
101 return udma_mode_mapping[n].udma_mode;
102 return udma_mode_mapping[4].udma_mode;
103 }
104 #endif
105
106 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
107 #include <linux/stat.h>
108 #include <linux/proc_fs.h>
109
110 static int sis_get_info(char *, char **, off_t, int);
111 extern int (*sis_display_info)(char *, char **, off_t, int); /* ide-proc.c */
112 struct pci_dev *bmide_dev;
113
114 static char *cable_type[] = {
115 "80 pins",
116 "40 pins"
117 };
118
119 static char *recovery_time [] ={
120 "12 PCICLK", "1 PCICLK",
121 "2 PCICLK", "3 PCICLK",
122 "4 PCICLK", "5 PCICLCK",
123 "6 PCICLK", "7 PCICLCK",
124 "8 PCICLK", "9 PCICLCK",
125 "10 PCICLK", "11 PCICLK",
126 "13 PCICLK", "14 PCICLK",
127 "15 PCICLK", "15 PCICLK"
128 };
129
130 static char *cycle_time [] = {
131 "Undefined", "2 CLCK",
132 "3 CLK", "4 CLK",
133 "5 CLK", "6 CLK",
134 "7 CLK", "8 CLK"
135 };
136
137 static char *active_time [] = {
138 "8 PCICLK", "1 PCICLCK",
139 "2 PCICLK", "2 PCICLK",
140 "4 PCICLK", "5 PCICLK",
141 "6 PCICLK", "12 PCICLK"
142 };
143
144 static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
145 {
146 int rc;
147 char *p = buffer;
148 byte reg,reg1;
149 u16 reg2, reg3;
150
151 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
152 rc = pci_read_config_byte(bmide_dev, 0x4a, &reg);
153 p += sprintf(p, "Channel Status: %s \t \t \t \t %s \n",
154 (reg & 0x02) ? "On" : "Off",
155 (reg & 0x04) ? "On" : "Off");
156
157 rc = pci_read_config_byte(bmide_dev, 0x09, &reg);
158 p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
159 (reg & 0x01) ? "Native" : "Compatible",
160 (reg & 0x04) ? "Native" : "Compatible");
161
162 rc = pci_read_config_byte(bmide_dev, 0x48, &reg);
163 p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
164 (reg & 0x10) ? cable_type[1] : cable_type[0],
165 (reg & 0x20) ? cable_type[1] : cable_type[0]);
166
167 rc = pci_read_config_word(bmide_dev, 0x4c, &reg2);
168 rc = pci_read_config_word(bmide_dev, 0x4e, &reg3);
169 p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
170 reg2, reg3);
171
172 rc = pci_read_config_byte(bmide_dev, 0x4b, &reg);
173 p += sprintf(p, "Drvie 0: Postwrite %s \t \t Postwrite %s\n",
174 (reg & 0x10) ? "Enabled" : "Disabled",
175 (reg & 0x40) ? "Enabled" : "Disabled");
176 p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
177 (reg & 0x01) ? "Enabled" : "Disabled",
178 (reg & 0x04) ? "Enabled" : "Disabled");
179
180 rc = pci_read_config_byte(bmide_dev, 0x41, &reg);
181 rc = pci_read_config_byte(bmide_dev, 0x45, &reg1);
182 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
183 (reg & 0x80) ? "Enabled" : "Disabled",
184 (reg1 & 0x80) ? "Enabled" : "Disabled");
185 p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n",
186 cycle_time[(reg & 0x70) >> 4], cycle_time[(reg1 & 0x70) >> 4]);
187 p += sprintf(p, " Data Active Time %s \t Data Active Time %s\n",
188 active_time[(reg & 0x07)], active_time[(reg &0x07)] );
189
190 rc = pci_read_config_byte(bmide_dev, 0x40, &reg);
191 rc = pci_read_config_byte(bmide_dev, 0x44, &reg1);
192 p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
193 recovery_time[(reg & 0x0f)], recovery_time[(reg1 & 0x0f)]);
194
195
196 rc = pci_read_config_byte(bmide_dev, 0x4b, &reg);
197 p += sprintf(p, "Drvie 1: Postwrite %s \t \t Postwrite %s\n",
198 (reg & 0x20) ? "Enabled" : "Disabled",
199 (reg & 0x80) ? "Enabled" : "Disabled");
200 p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
201 (reg & 0x02) ? "Enabled" : "Disabled",
202 (reg & 0x08) ? "Enabled" : "Disabled");
203
204 rc = pci_read_config_byte(bmide_dev, 0x43, &reg);
205 rc = pci_read_config_byte(bmide_dev, 0x47, &reg1);
206 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
207 (reg & 0x80) ? "Enabled" : "Disabled",
208 (reg1 & 0x80) ? "Enabled" : "Disabled");
209 p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n",
210 cycle_time[(reg & 0x70) >> 4], cycle_time[(reg1 & 0x70) >> 4]);
211 p += sprintf(p, " Data Active Time %s \t Data Active Time %s\n",
212 active_time[(reg & 0x07)], active_time[(reg &0x07)] );
213
214 rc = pci_read_config_byte(bmide_dev, 0x42, &reg);
215 rc = pci_read_config_byte(bmide_dev, 0x46, &reg1);
216 p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
217 recovery_time[(reg & 0x0f)], recovery_time[(reg1 & 0x0f)]);
218 return p-buffer;
219 }
220 #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
221
222 byte sis_proc = 0;
223 extern char *ide_xfer_verbose (byte xfer_rate);
224
225 /*
226 * ((id->hw_config & 0x2000) && (HWIF(drive)->udma_four))
227 */
228 static int config_chipset_for_dma (ide_drive_t *drive, byte ultra)
229 {
230 struct hd_driveid *id = drive->id;
231 ide_hwif_t *hwif = HWIF(drive);
232 struct pci_dev *dev = hwif->pci_dev;
233
234 byte drive_pci, test1, test2, mask;
235 int err;
236
237 unsigned long dma_base = hwif->dma_base;
238 byte unit = (drive->select.b.unit & 0x01);
239 byte speed = 0x00, unmask = 0xE0, four_two = 0x00;
240 int drive_number = ((hwif->channel ? 2 : 0) + unit);
241 byte udma_66 = ((id->hw_config & 0x2000) && (hwif->udma_four)) ? 1 : 0;
242
243 if (host_dev) {
244 switch(host_dev->device) {
245 case PCI_DEVICE_ID_SI_530:
246 case PCI_DEVICE_ID_SI_540:
247 case PCI_DEVICE_ID_SI_620:
248 case PCI_DEVICE_ID_SI_630:
249 unmask = 0xF0;
250 four_two = 0x01;
251 default:
252 break;
253 }
254 }
255
256 switch(drive_number) {
257 case 0: drive_pci = 0x40;break;
258 case 1: drive_pci = 0x42;break;
259 case 2: drive_pci = 0x44;break;
260 case 3: drive_pci = 0x46;break;
261 default: return ide_dma_off;
262 }
263
264 pci_read_config_byte(dev, drive_pci, &test1);
265 pci_read_config_byte(dev, drive_pci|0x01, &test2);
266
267 if ((!ultra) && (test2 & 0x80)) {
268 pci_write_config_byte(dev, drive_pci|0x01, test2 & ~0x80);
269 pci_read_config_byte(dev, drive_pci|0x01, &test2);
270 }
271
272 if ((id->dma_ultra & 0x0010) && (ultra) && (udma_66) && (four_two)) {
273 if (!(test2 & 0x90)) {
274 pci_write_config_byte(dev, drive_pci|0x01, test2 & ~unmask);
275 pci_write_config_byte(dev, drive_pci|0x01, test2|0x90);
276 }
277 speed = XFER_UDMA_4;
278 } else if ((id->dma_ultra & 0x0008) && (ultra) && (udma_66) && (four_two)) {
279 if (!(test2 & 0xA0)) {
280 pci_write_config_byte(dev, drive_pci|0x01, test2 & ~unmask);
281 pci_write_config_byte(dev, drive_pci|0x01, test2|0xA0);
282 }
283 speed = XFER_UDMA_3;
284 } else if ((id->dma_ultra & 0x0004) && (ultra)) {
285 mask = (four_two) ? 0xB0 : 0xA0;
286 if (!(test2 & mask)) {
287 pci_write_config_byte(dev, drive_pci|0x01, test2 & ~unmask);
288 pci_write_config_byte(dev, drive_pci|0x01, test2|mask);
289 }
290 speed = XFER_UDMA_2;
291 } else if ((id->dma_ultra & 0x0002) && (ultra)) {
292 mask = (four_two) ? 0xD0 : 0xC0;
293 if (!(test2 & mask)) {
294 pci_write_config_byte(dev, drive_pci|0x01, test2 & ~unmask);
295 pci_write_config_byte(dev, drive_pci|0x01, test2|mask);
296 }
297 speed = XFER_UDMA_1;
298 } else if ((id->dma_ultra & 0x0001) && (ultra)) {
299 if (!(test2 & unmask)) {
300 pci_write_config_byte(dev, drive_pci|0x01, test2 & ~unmask);
301 pci_write_config_byte(dev, drive_pci|0x01, test2|unmask);
302 }
303 speed = XFER_UDMA_0;
304 } else if (id->dma_mword & 0x0004) {
305 speed = XFER_MW_DMA_2;
306 } else if (id->dma_mword & 0x0002) {
307 speed = XFER_MW_DMA_1;
308 } else if (id->dma_mword & 0x0001) {
309 speed = XFER_MW_DMA_0;
310 } else if (id->dma_1word & 0x0004) {
311 speed = XFER_SW_DMA_2;
312 } else if (id->dma_1word & 0x0002) {
313 speed = XFER_SW_DMA_1;
314 } else if (id->dma_1word & 0x0001) {
315 speed = XFER_SW_DMA_0;
316 } else {
317 return ((int) ide_dma_off_quietly);
318 }
319
320 outb(inb(dma_base+2)|(1<<(5+unit)), dma_base+2);
321 err = ide_config_drive_speed(drive, speed);
322
323 #if SIS5513_DEBUG_DRIVE_INFO
324 printk("%s: %s drive%d\n", drive->name, ide_xfer_verbose(speed), drive_number);
325 #endif /* SIS5513_DEBUG_DRIVE_INFO */
326
327 return ((int) ((id->dma_ultra >> 11) & 3) ? ide_dma_on :
328 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
329 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
330 ((id->dma_1word >> 8) & 7) ? ide_dma_on :
331 ide_dma_off_quietly);
332 }
333
334 static void config_drive_art_rwp (ide_drive_t *drive)
335 {
336 ide_hwif_t *hwif = HWIF(drive);
337 struct pci_dev *dev = hwif->pci_dev;
338
339 byte timing, pio, drive_pci, test1, test2;
340
341 unsigned short eide_pio_timing[6] = {600, 390, 240, 180, 120, 90};
342 unsigned short xfer_pio = drive->id->eide_pio_modes;
343 int drive_number = ((hwif->channel ? 2 : 0) + (drive->select.b.unit & 0x01));
344
345 if (drive->media == ide_disk) {
346 struct pci_dev *dev = hwif->pci_dev;
347 byte reg4bh = 0;
348 byte rw_prefetch = (0x11 << drive_number);
349
350 pci_read_config_byte(dev, 0x4b, &reg4bh);
351 if ((reg4bh & rw_prefetch) != rw_prefetch)
352 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
353 }
354
355 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
356
357 if (xfer_pio> 4)
358 xfer_pio = 0;
359
360 if (drive->id->eide_pio_iordy > 0) {
361 for (xfer_pio = 5;
362 xfer_pio>0 &&
363 drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
364 xfer_pio--);
365 } else {
366 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
367 (drive->id->eide_pio_modes & 2) ? 0x04 :
368 (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
369 }
370
371 timing = (xfer_pio >= pio) ? xfer_pio : pio;
372
373 /*
374 * Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
375 * Active time 8T (240ns) 6T (180ns) 4T (120ns) 3T (90ns) 3T (90ns)
376 * 0x41 2:0 bits 000 110 100 011 011
377 * Recovery time 12T (360ns) 7T (210ns) 4T (120ns) 3T (90ns) 1T (30ns)
378 * 0x40 3:0 bits 0000 0111 0100 0011 0001
379 * Cycle time 20T (600ns) 13T (390ns) 8T (240ns) 6T (180ns) 4T (120ns)
380 */
381
382 switch(drive_number) {
383 case 0: drive_pci = 0x40;break;
384 case 1: drive_pci = 0x42;break;
385 case 2: drive_pci = 0x44;break;
386 case 3: drive_pci = 0x46;break;
387 default: return;
388 }
389
390 pci_read_config_byte(dev, drive_pci, &test1);
391 pci_read_config_byte(dev, drive_pci|0x01, &test2);
392
393 /*
394 * Do a blanket clear of active and recovery timings.
395 */
396
397 test1 &= ~0x07;
398 test2 &= ~0x0F;
399
400 switch(timing) {
401 case 4: test1 |= 0x01;test2 |= 0x03;break;
402 case 3: test1 |= 0x03;test2 |= 0x03;break;
403 case 2: test1 |= 0x04;test2 |= 0x04;break;
404 case 1: test1 |= 0x07;test2 |= 0x06;break;
405 default: break;
406 }
407
408 pci_write_config_byte(dev, drive_pci, test1);
409 pci_write_config_byte(dev, drive_pci|0x01, test2);
410 }
411
412 static int config_drive_xfer_rate (ide_drive_t *drive)
413 {
414 struct hd_driveid *id = drive->id;
415 ide_dma_action_t dma_func = ide_dma_off_quietly;
416
417 if (id && (id->capability & 1) && HWIF(drive)->autodma) {
418 /* Consult the list of known "bad" drives */
419 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
420 return HWIF(drive)->dmaproc(ide_dma_off, drive);
421 }
422
423 if (id->field_valid & 4) {
424 if (id->dma_ultra & 0x001F) {
425 /* Force if Capable UltraDMA */
426 dma_func = config_chipset_for_dma(drive, 1);
427 if ((id->field_valid & 2) &&
428 (dma_func != ide_dma_on))
429 goto try_dma_modes;
430 }
431 } else if (id->field_valid & 2) {
432 try_dma_modes:
433 if ((id->dma_mword & 0x0007) ||
434 (id->dma_1word & 0x0007)) {
435 /* Force if Capable regular DMA modes */
436 dma_func = config_chipset_for_dma(drive, 0);
437 }
438 } else if ((ide_dmaproc(ide_dma_good_drive, drive)) &&
439 (id->eide_dma_time > 150)) {
440 /* Consult the list of known "good" drives */
441 dma_func = config_chipset_for_dma(drive, 0);
442 }
443 }
444 return HWIF(drive)->dmaproc(dma_func, drive);
445 }
446
447 /*
448 * sis5513_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
449 */
450 int sis5513_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
451 {
452 switch (func) {
453 case ide_dma_check:
454 config_drive_art_rwp(drive);
455 return config_drive_xfer_rate(drive);
456 default:
457 break;
458 }
459 return ide_dmaproc(func, drive); /* use standard DMA stuff */
460 }
461
462 unsigned int __init pci_init_sis5513 (struct pci_dev *dev, const char *name)
463 {
464 struct pci_dev *host;
465 int i = 0;
466 byte latency = 0;
467
468 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &latency);
469
470 for (i = 0; i < arraysize (SiSHostChipInfo) && !host_dev; i++) {
471 host = pci_find_device (PCI_VENDOR_ID_SI,
472 SiSHostChipInfo[i].host_id,
473 NULL);
474 if (!host)
475 continue;
476
477 host_dev = host;
478 printk(SiSHostChipInfo[i].name);
479 printk("\n");
480 if (SiSHostChipInfo[i].flags & SIS5513_FLAG_LATENCY) {
481 if (latency != 0x10)
482 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
483 }
484 }
485
486 if (host_dev) {
487 byte reg52h = 0;
488
489 pci_read_config_byte(dev, 0x52, &reg52h);
490 if (!(reg52h & 0x04)) {
491 /* set IDE controller to operate in Compabitility mode obly */
492 pci_write_config_byte(dev, 0x52, reg52h|0x04);
493 }
494 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
495 sis_proc = 1;
496 bmide_dev = dev;
497 sis_display_info = &sis_get_info;
498 #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
499 }
500 return 0;
501 }
502
503 unsigned int __init ata66_sis5513 (ide_hwif_t *hwif)
504 {
505 byte reg48h = 0, ata66 = 0;
506 byte mask = hwif->channel ? 0x20 : 0x10;
507 pci_read_config_byte(hwif->pci_dev, 0x48, &reg48h);
508
509 if (host_dev) {
510 switch(host_dev->device) {
511 case PCI_DEVICE_ID_SI_530:
512 case PCI_DEVICE_ID_SI_540:
513 case PCI_DEVICE_ID_SI_620:
514 case PCI_DEVICE_ID_SI_630:
515 ata66 = (reg48h & mask) ? 0 : 1;
516 default:
517 break;
518 }
519 }
520 return (ata66);
521 }
522
523 void __init ide_init_sis5513 (ide_hwif_t *hwif)
524 {
525
526 hwif->irq = hwif->channel ? 15 : 14;
527
528 if (!(hwif->dma_base))
529 return;
530
531 if (host_dev) {
532 switch(host_dev->device) {
533 case PCI_DEVICE_ID_SI_530:
534 case PCI_DEVICE_ID_SI_540:
535 case PCI_DEVICE_ID_SI_620:
536 case PCI_DEVICE_ID_SI_630:
537 case PCI_DEVICE_ID_SI_5600:
538 case PCI_DEVICE_ID_SI_5597:
539 case PCI_DEVICE_ID_SI_5591:
540 hwif->autodma = 1;
541 hwif->dmaproc = &sis5513_dmaproc;
542 break;
543 default:
544 hwif->autodma = 0;
545 break;
546 }
547 }
548 return;
549 }
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