drivers/block/opti621.c

   1 /*
   2  *  linux/drivers/block/opti621.c               Version 0.6     Jan 02, 1999
   3  *
   4  *  Copyright (C) 1996-1998  Linus Torvalds & authors (see below)
   5  */
   6
   7 /*
   8  * Authors:
   9  * Jaromir Koutek <miri@punknet.cz>,
  10  * Jan Harkes <jaharkes@cwi.nl>,
  11  * Mark Lord <mlord@pobox.com>
  12  * Some parts of code are from ali14xx.c and from rz1000.c.
  13  *
  14  * OPTi is trademark of OPTi, Octek is trademark of Octek.
  15  *
  16  * I used docs from OPTi databook, from ftp.opti.com, file 9123-0002.ps
  17  * and disassembled/traced setupvic.exe (DOS program).
  18  * It increases kernel code about 2 kB.
  19  * I don't have this card no more, but I hope I can get some in case
  20  * of needed development.
  21  * My card is Octek PIDE 1.01 (on card) or OPTiViC (program).
  22  * It has a place for a secondary connector in circuit, but nothing
  23  * is there. Also BIOS says no address for
  24  * secondary controller (see bellow in ide_init_opti621).
  25  * I've only tested this on my system, which only has one disk.
  26  * It's Western Digital WDAC2850, with PIO mode 3. The PCI bus
  27  * is at 20 MHz (I have DX2/80, I tried PCI at 40, but I got random
  28  * lockups). I tried the OCTEK double speed CD-ROM and
  29  * it does not work! But I can't boot DOS also, so it's probably
  30  * hardware fault. I have connected Conner 80MB, the Seagate 850MB (no
  31  * problems) and Seagate 1GB (as slave, WD as master). My experiences
  32  * with the third, 1GB drive: I got 3MB/s (hdparm), but sometimes
  33  * it slows to about 100kB/s! I don't know why and I have
  34  * not this drive now, so I can't try it again.
  35  * I write this driver because I lost the paper ("manual") with
  36  * settings of jumpers on the card and I have to boot Linux with
  37  * Loadlin except LILO, cause I have to run the setupvic.exe program
  38  * already or I get disk errors (my test: rpm -Vf
  39  * /usr/X11R6/bin/XF86_SVGA - or any big file).
  40  * Some numbers from hdparm -t /dev/hda:
  41  * Timing buffer-cache reads:   32 MB in  3.02 seconds =10.60 MB/sec
  42  * Timing buffered disk reads:  16 MB in  5.52 seconds = 2.90 MB/sec
  43  * I have 4 Megs/s before, but I don't know why (maybe changes
  44  * in hdparm test).
  45  * After release of 0.1, I got some successful reports, so it might work.
  46  *
  47  * The main problem with OPTi is that some timings for master
  48  * and slave must be the same. For example, if you have master
  49  * PIO 3 and slave PIO 0, driver have to set some timings of
  50  * master for PIO 0. Second problem is that opti621_tune_drive
  51  * got only one drive to set, but have to set both drives.
  52  * This is solved in compute_pios. If you don't set
  53  * the second drive, compute_pios use ide_get_best_pio_mode
  54  * for autoselect mode (you can change it to PIO 0, if you want).
  55  * If you then set the second drive to another PIO, the old value
  56  * (automatically selected) will be overrided by yours.
  57  * There is a 25/33MHz switch in configuration
  58  * register, but driver is written for use at any frequency which get
  59  * (use idebus=xx to select PCI bus speed).
  60  * Use ide0=autotune for automatical tune of the PIO modes.
  61  * If you get strange results, do not use this and set PIO manually
  62  * by hdparm.
  63  *
  64  * Version 0.1, Nov 8, 1996
  65  * by Jaromir Koutek, for 2.1.8.
  66  * Initial version of driver.
  67  *
  68  * Version 0.2
  69  * Number 0.2 skipped.
  70  *
  71  * Version 0.3, Nov 29, 1997
  72  * by Mark Lord (probably), for 2.1.68
  73  * Updates for use with new IDE block driver.
  74  *
  75  * Version 0.4, Dec 14, 1997
  76  * by Jan Harkes
  77  * Fixed some errors and cleaned the code.
  78  *
  79  * Version 0.5, Jan 2, 1998
  80  * by Jaromir Koutek
  81  * Updates for use with (again) new IDE block driver.
  82  * Update of documentation.
  83  *
  84  * Version 0.6, Jan 2, 1999
  85  * by Jaromir Koutek
  86  * Reversed to version 0.3 of the driver, because
  87  * 0.5 doesn't work.
  88  */
  89
  90 #undef REALLY_SLOW_IO   /* most systems can safely undef this */
  91 #define OPTI621_DEBUG           /* define for debug messages */
  92
  93 #include <linux/types.h>
  94 #include <linux/kernel.h>
  95 #include <linux/delay.h>
  96 #include <linux/timer.h>
  97 #include <linux/mm.h>
  98 #include <linux/ioport.h>
  99 #include <linux/blkdev.h>
 100 #include <linux/hdreg.h>
 101 #include <linux/ide.h>
 102
 103 #include <asm/io.h>
 104
 105 #include "ide_modes.h"
 106
 107 #define OPTI621_MAX_PIO 3
 108 /* In fact, I do not have any PIO 4 drive
 109  * (address: 25 ns, data: 70 ns, recovery: 35 ns),
 110  * but OPTi 82C621 is programmable and it can do (minimal values):
 111  * on 40MHz PCI bus (pulse 25 ns):
 112  *  address: 25 ns, data: 25 ns, recovery: 50 ns;
 113  * on 20MHz PCI bus (pulse 50 ns):
 114  *  address: 50 ns, data: 50 ns, recovery: 100 ns.
 115  */
 116
 117 /* #define READ_PREFETCH 0 */
 118 /* Uncommnent for disable read prefetch.
 119  * There is some readprefetch capatibility in hdparm,
 120  * but when I type hdparm -P 1 /dev/hda, I got errors
 121  * and till reset drive is inacessible.
 122  * This (hw) read prefetch is safe on my drive.
 123  */
 124
 125 #ifndef READ_PREFETCH
 126 #define READ_PREFETCH 0x40 /* read prefetch is enabled */
 127 #endif /* else read prefetch is disabled */
 128
 129 #define READ_REG 0      /* index of Read cycle timing register */
 130 #define WRITE_REG 1     /* index of Write cycle timing register */
 131 #define CNTRL_REG 3     /* index of Control register */
 132 #define STRAP_REG 5     /* index of Strap register */
 133 #define MISC_REG 6      /* index of Miscellaneous register */
 134
 135 int reg_base;
 136
 137 #define PIO_NOT_EXIST 254
 138 #define PIO_DONT_KNOW 255
 139
 140 /* there are stored pio numbers from other calls of opti621_tune_drive */
 141
 142 static void compute_pios(ide_drive_t *drive, byte pio)
 143 /* Store values into drive->drive_data
 144  *      second_contr - 0 for primary controller, 1 for secondary
 145  *      slave_drive - 0 -> pio is for master, 1 -> pio is for slave
 146  *      pio - PIO mode for selected drive (for other we don't know)
 147  */
 148 {
 149         int d;
 150         ide_hwif_t *hwif = HWIF(drive);
 151
 152         drive->drive_data = ide_get_best_pio_mode(drive, pio, OPTI621_MAX_PIO, NULL);
 153         for (d = 0; d < 2; ++d) {
 154                 drive = &hwif->drives[d];
 155                 if (drive->present) {
 156                         if (drive->drive_data == PIO_DONT_KNOW)
 157                                 drive->drive_data = ide_get_best_pio_mode(drive, 255, OPTI621_MAX_PIO, NULL);
 158 #ifdef OPTI621_DEBUG
 159                         printk("%s: Selected PIO mode %d\n", drive->name, drive->drive_data);
 160 #endif
 161                 } else {
 162                         drive->drive_data = PIO_NOT_EXIST;
 163                 }
 164         }
 165 }
 166
 167 int cmpt_clk(int time, int bus_speed)
 168 /* Returns (rounded up) time in clocks for time in ns,
 169  * with bus_speed in MHz.
 170  * Example: bus_speed = 40 MHz, time = 80 ns
 171  * 1000/40 = 25 ns (clk value),
 172  * 80/25 = 3.2, rounded up to 4 (I hope ;-)).
 173  * Use idebus=xx to select right frequency.
 174  */
 175 {
 176         return ((time*bus_speed+999)/1000);
 177 }
 178
 179 static void write_reg(byte value, int reg)
 180 /* Write value to register reg, base of register
 181  * is at reg_base (0x1f0 primary, 0x170 secondary,
 182  * if not changed by PCI configuration).
 183  * This is from setupvic.exe program.
 184  */
 185 {
 186         inw(reg_base+1);
 187         inw(reg_base+1);
 188         outb(3, reg_base+2);
 189         outb(value, reg_base+reg);
 190         outb(0x83, reg_base+2);
 191 }
 192
 193 static byte read_reg(int reg)
 194 /* Read value from register reg, base of register
 195  * is at reg_base (0x1f0 primary, 0x170 secondary,
 196  * if not changed by PCI configuration).
 197  * This is from setupvic.exe program.
 198  */
 199 {
 200         byte ret;
 201         inw(reg_base+1);
 202         inw(reg_base+1);
 203         outb(3, reg_base+2);
 204         ret=inb(reg_base+reg);
 205         outb(0x83, reg_base+2);
 206         return ret;
 207 }
 208
 209 typedef struct pio_clocks_s {
 210         int     address_time;   /* Address setup (clocks) */
 211         int     data_time;      /* Active/data pulse (clocks) */
 212         int     recovery_time;  /* Recovery time (clocks) */
 213 } pio_clocks_t;
 214
 215 static void compute_clocks(int pio, pio_clocks_t *clks)
 216 {
 217         if (pio != PIO_NOT_EXIST) {
 218                 int adr_setup, data_pls, bus_speed;
 219                 bus_speed = ide_system_bus_speed();
 220                 adr_setup = ide_pio_timings[pio].setup_time;
 221                 data_pls = ide_pio_timings[pio].active_time;
 222                 clks->address_time = cmpt_clk(adr_setup, bus_speed);
 223                 clks->data_time = cmpt_clk(data_pls, bus_speed);
 224                 clks->recovery_time = cmpt_clk(ide_pio_timings[pio].cycle_time
 225                         - adr_setup-data_pls, bus_speed);
 226                 if (clks->address_time<1) clks->address_time = 1;
 227                 if (clks->address_time>4) clks->address_time = 4;
 228                 if (clks->data_time<1) clks->data_time = 1;
 229                 if (clks->data_time>16) clks->data_time = 16;
 230                 if (clks->recovery_time<2) clks->recovery_time = 2;
 231                 if (clks->recovery_time>17) clks->recovery_time = 17;
 232         } else {
 233                 clks->address_time = 1;
 234                 clks->data_time = 1;
 235                 clks->recovery_time = 2;
 236                 /* minimal values */
 237         }
 238
 239 }
 240
 241 /* Main tune procedure, called from tuneproc. */
 242 static void opti621_tune_drive (ide_drive_t *drive, byte pio)
 243 {
 244         /* primary and secondary drives share some registers,
 245          * so we have to program both drives
 246          */
 247         unsigned long flags;
 248         byte pio1, pio2;
 249         pio_clocks_t first, second;
 250         int ax, drdy;
 251         byte cycle1, cycle2, misc;
 252         ide_hwif_t *hwif = HWIF(drive);
 253
 254         /* sets drive->drive_data for both drives */
 255         compute_pios(drive, pio);
 256         pio1 = hwif->drives[0].drive_data;
 257         pio2 = hwif->drives[1].drive_data;
 258
 259         compute_clocks(pio1, &first);
 260         compute_clocks(pio2, &second);
 261
 262         /* ax = max(a1,a2) */
 263         ax = (first.address_time < second.address_time) ? second.address_time : first.address_time;
 264
 265         drdy = 2; /* DRDY is default 2 (by OPTi Databook) */
 266
 267         cycle1 = ((first.data_time-1)<<4)  | (first.recovery_time-2);
 268         cycle2 = ((second.data_time-1)<<4) | (second.recovery_time-2);
 269         misc = READ_PREFETCH | ((ax-1)<<4) | ((drdy-2)<<1);
 270
 271 #ifdef OPTI621_DEBUG
 272         printk("%s: master: address: %d, data: %d, recovery: %d, drdy: %d [clk]\n",
 273                 hwif->name, ax, first.data_time, first.recovery_time, drdy);
 274         printk("%s: slave:  address: %d, data: %d, recovery: %d, drdy: %d [clk]\n",
 275                 hwif->name, ax, second.data_time, second.recovery_time, drdy);
 276 #endif
 277
 278         save_flags(flags);      /* all CPUs */
 279         cli();                  /* all CPUs */
 280
 281         reg_base = hwif->io_ports[IDE_DATA_OFFSET];
 282         outb(0xc0, reg_base+CNTRL_REG); /* allow Register-B */
 283         outb(0xff, reg_base+5);         /* hmm, setupvic.exe does this ;-) */
 284         inb(reg_base+CNTRL_REG);        /* if reads 0xff, adapter not exist? */
 285         read_reg(CNTRL_REG);            /* if reads 0xc0, no interface exist? */
 286         read_reg(STRAP_REG);            /* read version, probably 0 */
 287
 288         /* program primary drive */
 289         write_reg(0,      MISC_REG);    /* select Index-0 for Register-A */
 290         write_reg(cycle1, READ_REG);    /* set read cycle timings */
 291         write_reg(cycle1, WRITE_REG);   /* set write cycle timings */
 292
 293         /* program secondary drive */
 294         write_reg(1,      MISC_REG);    /* select Index-1 for Register-B */
 295         write_reg(cycle2, READ_REG);    /* set read cycle timings */
 296         write_reg(cycle2, WRITE_REG);   /* set write cycle timings */
 297
 298         write_reg(0x85, CNTRL_REG);     /* use Register-A for drive 0 */
 299                                         /* use Register-B for drive 1 */
 300
 301         write_reg(misc, MISC_REG);      /* set address setup, DRDY timings,   */
 302                                         /*  and read prefetch for both drives */
 303
 304         restore_flags(flags);   /* all CPUs */
 305 }
 306
 307 /*
 308  * ide_init_opti621() is called once for each hwif found at boot.
 309  */
 310 void ide_init_opti621 (ide_hwif_t *hwif)
 311 {
 312         hwif->drives[0].drive_data = PIO_DONT_KNOW;
 313         hwif->drives[1].drive_data = PIO_DONT_KNOW;
 314         hwif->tuneproc = &opti621_tune_drive;
 315 }