drivers/block/piix.c

   1 /*
   2  * linux/drivers/block/piix.c   Version 0.23    May 29, 1999
   3  *
   4  *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
   5  *  Copyright (C) 1998-1999 Andre Hedrick, Author and Maintainer
   6  *
   7  *  PIO mode setting function for Intel chipsets.
   8  *  For use instead of BIOS settings.
   9  *
  10  * 40-41
  11  * 42-43
  12  *
  13  *                 41
  14  *                 43
  15  *
  16  * | PIO 0       | c0 | 80 | 0 |        piix_tune_drive(drive, 0);
  17  * | PIO 2 | SW2 | d0 | 90 | 4 |        piix_tune_drive(drive, 2);
  18  * | PIO 3 | MW1 | e1 | a1 | 9 |        piix_tune_drive(drive, 3);
  19  * | PIO 4 | MW2 | e3 | a3 | b |        piix_tune_drive(drive, 4);
  20  *
  21  * sitre = word40 & 0x4000; primary
  22  * sitre = word42 & 0x4000; secondary
  23  *
  24  * 44 8421|8421    hdd|hdb
  25  *
  26  * 48 8421         hdd|hdc|hdb|hda udma enabled
  27  *
  28  *    0001         hda
  29  *    0010         hdb
  30  *    0100         hdc
  31  *    1000         hdd
  32  *
  33  * 4a 84|21        hdb|hda
  34  * 4b 84|21        hdd|hdc
  35  *
  36  *    00|00 udma 0
  37  *    01|01 udma 1
  38  *    10|10 udma 2
  39  *    11|11 reserved
  40  *
  41  * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &reg40);
  42  * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, &reg42);
  43  * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, &reg44);
  44  * pci_read_config_word(HWIF(drive)->pci_dev, 0x48, &reg48);
  45  * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, &reg4a);
  46  *
  47  */
  48
  49 #include <linux/types.h>
  50 #include <linux/kernel.h>
  51 #include <linux/ioport.h>
  52 #include <linux/pci.h>
  53 #include <linux/hdreg.h>
  54 #include <linux/ide.h>
  55
  56 #include <asm/delay.h>
  57 #include <asm/io.h>
  58
  59 #include "ide_modes.h"
  60
  61 #define PIIX_DEBUG_DRIVE_INFO           0
  62
  63 extern char *ide_xfer_verbose (byte xfer_rate);
  64
  65 /*
  66  *
  67  */
  68 static byte piix_dma_2_pio (byte xfer_rate) {
  69         switch(xfer_rate) {
  70                 case XFER_UDMA_4:
  71                 case XFER_UDMA_3:
  72                 case XFER_UDMA_2:
  73                 case XFER_UDMA_1:
  74                 case XFER_UDMA_0:
  75                 case XFER_MW_DMA_2:
  76                 case XFER_PIO_4:
  77                         return 4;
  78                 case XFER_MW_DMA_1:
  79                 case XFER_PIO_3:
  80                         return 3;
  81                 case XFER_SW_DMA_2:
  82                 case XFER_PIO_2:
  83                         return 2;
  84                 case XFER_MW_DMA_0:
  85                 case XFER_SW_DMA_1:
  86                 case XFER_SW_DMA_0:
  87                 case XFER_PIO_1:
  88                 case XFER_PIO_0:
  89                 case XFER_PIO_SLOW:
  90                 default:
  91                         return 0;
  92         }
  93 }
  94
  95 /*
  96  *  Based on settings done by AMI BIOS
  97  *  (might be usefull if drive is not registered in CMOS for any reason).
  98  */
  99 static void piix_tune_drive (ide_drive_t *drive, byte pio)
 100 {
 101         unsigned long flags;
 102         u16 master_data;
 103         byte slave_data;
 104         int is_slave            = (&HWIF(drive)->drives[1] == drive);
 105         int master_port         = HWIF(drive)->index ? 0x42 : 0x40;
 106         int slave_port          = 0x44;
 107                                  /* ISP  RTC */
 108         byte timings[][2]       = { { 0, 0 },
 109                                     { 0, 0 },
 110                                     { 1, 0 },
 111                                     { 2, 1 },
 112                                     { 2, 3 }, };
 113
 114 #if 1
 115         pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
 116 #else
 117         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
 118 #endif
 119         pci_read_config_word(HWIF(drive)->pci_dev, master_port, &master_data);
 120         if (is_slave) {
 121                 master_data = master_data | 0x4000;
 122                 if (pio > 1)
 123                         /* enable PPE, IE and TIME */
 124                         master_data = master_data | 0x0070;
 125                 pci_read_config_byte(HWIF(drive)->pci_dev, slave_port, &slave_data);
 126                 slave_data = slave_data & (HWIF(drive)->index ? 0x0f : 0xf0);
 127                 slave_data = slave_data | ((timings[pio][0] << 2) | (timings[pio][1]
 128                                            << (HWIF(drive)->index ? 4 : 0)));
 129         } else {
 130                 master_data = master_data & 0xccf8;
 131                 if (pio > 1)
 132                         /* enable PPE, IE and TIME */
 133                         master_data = master_data | 0x0007;
 134                 master_data = master_data | (timings[pio][0] << 12) |
 135                               (timings[pio][1] << 8);
 136         }
 137         save_flags(flags);
 138         cli();
 139         pci_write_config_word(HWIF(drive)->pci_dev, master_port, master_data);
 140         if (is_slave)
 141                 pci_write_config_byte(HWIF(drive)->pci_dev, slave_port, slave_data);
 142         restore_flags(flags);
 143 }
 144
 145 static int piix_config_drive_for_dma(ide_drive_t *drive, int ultra)
 146 {
 147         struct hd_driveid *id = drive->id;
 148         ide_hwif_t *hwif = HWIF(drive);
 149         struct pci_dev *dev = hwif->pci_dev;
 150
 151         unsigned long           flags;
 152         int                     sitre;
 153         short                   reg4042, reg44, reg48, reg4a;
 154         byte                    speed;
 155         int                     u_speed;
 156         byte maslave            = hwif->channel ? 0x42 : 0x40;
 157         int drive_number        = ((hwif->channel ? 2 : 0) + (drive->select.b.unit & 0x01));
 158         int a_speed             = 2 << (drive_number * 4);
 159         int u_flag              = 1 << drive_number;
 160
 161         pci_read_config_word(dev, maslave, &reg4042);
 162         sitre =  (reg4042 & 0x4000) ? 1 : 0;
 163         pci_read_config_word(dev, 0x44, &reg44);
 164         pci_read_config_word(dev, 0x48, &reg48);
 165         pci_read_config_word(dev, 0x4a, &reg4a);
 166
 167         save_flags(flags);
 168         cli();
 169
 170         if (id->dma_ultra && (ultra)) {
 171                 if (!(reg48 & u_flag)) {
 172                         pci_write_config_word(dev, 0x48, reg48|u_flag);
 173                 }
 174         } else {
 175                 if (reg48 & u_flag) {
 176                         pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
 177                 }
 178         }
 179
 180         if ((id->dma_ultra & 0x0004) && (ultra)) {
 181                 drive->id->dma_mword &= ~0x0F00;
 182                 drive->id->dma_1word &= ~0x0F00;
 183                 if (!((id->dma_ultra >> 8) & 4)) {
 184                         drive->id->dma_ultra &= ~0x0F00;
 185                         drive->id->dma_ultra |= 0x0404;
 186                 }
 187                 u_speed = 2 << (drive_number * 4);
 188                 if (!(reg4a & u_speed)) {
 189                         pci_write_config_word(dev, 0x4a, reg4a|u_speed);
 190                 }
 191                 speed = XFER_UDMA_2;
 192         } else if ((id->dma_ultra & 0x0002) && (ultra)) {
 193                 drive->id->dma_mword &= ~0x0F00;
 194                 drive->id->dma_1word &= ~0x0F00;
 195                 if (!((id->dma_ultra >> 8) & 2)) {
 196                         drive->id->dma_ultra &= ~0x0F00;
 197                         drive->id->dma_ultra |= 0x0202;
 198                 }
 199                 u_speed = 1 << (drive_number * 4);
 200                 if (!(reg4a & u_speed)) {
 201                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 202                         pci_write_config_word(dev, 0x4a, reg4a|u_speed);
 203                 }
 204                 speed = XFER_UDMA_1;
 205         } else if ((id->dma_ultra & 0x0001) && (ultra)) {
 206                 drive->id->dma_mword &= ~0x0F00;
 207                 drive->id->dma_1word &= ~0x0F00;
 208                 if (!((id->dma_ultra >> 8) & 1)) {
 209                         drive->id->dma_ultra &= ~0x0F00;
 210                         drive->id->dma_ultra |= 0x0101;
 211                 }
 212                 u_speed = 0 << (drive_number * 4);
 213                 if (!(reg4a & u_speed)) {
 214                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 215                         pci_write_config_word(dev, 0x4a, reg4a|u_speed);
 216                 }
 217                 speed = XFER_UDMA_0;
 218         } else if (id->dma_mword & 0x0004) {
 219                 if (reg4a & a_speed)
 220                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 221                 drive->id->dma_ultra &= ~0x0F00;
 222                 drive->id->dma_1word &= ~0x0F00;
 223                 if (!((id->dma_mword >> 8) & 4)) {
 224                         drive->id->dma_mword &= ~0x0F00;
 225                         drive->id->dma_mword |= 0x0404;
 226                 }
 227                 speed = XFER_MW_DMA_2;
 228         } else if (id->dma_mword & 0x0002) {
 229                 if (reg4a & a_speed)
 230                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 231                 drive->id->dma_ultra &= ~0x0F00;
 232                 drive->id->dma_1word &= ~0x0F00;
 233                 if (!((id->dma_mword >> 8) & 2)) {
 234                         drive->id->dma_mword &= ~0x0F00;
 235                         drive->id->dma_mword |= 0x0202;
 236                 }
 237                 speed = XFER_MW_DMA_1;
 238         } else if (id->dma_1word & 0x0004) {
 239                 if (reg4a & a_speed)
 240                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 241                 drive->id->dma_ultra &= ~0x0F00;
 242                 drive->id->dma_mword &= ~0x0F00;
 243                 if (!((id->dma_1word >> 8) & 4)) {
 244                         drive->id->dma_1word &= ~0x0F00;
 245                         drive->id->dma_1word |= 0x0404;
 246                 }
 247                 speed = XFER_SW_DMA_2;
 248         } else {
 249 #if 0
 250                 speed = XFER_PIO_0;
 251 #else
 252                 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
 253 #endif
 254         }
 255
 256         restore_flags(flags);
 257         piix_tune_drive(drive, piix_dma_2_pio(speed));
 258
 259         (void) ide_wait_cmd(drive, WIN_SETFEATURES, speed, SETFEATURES_XFER, 0, NULL);
 260
 261 #if PIIX_DEBUG_DRIVE_INFO
 262         printk("%s: %s drive%d ",
 263                 drive->name,
 264                 ide_xfer_verbose(speed),
 265                 drive_number);
 266         printk("\n");
 267 #endif /* PIIX_DEBUG_DRIVE_INFO */
 268
 269         return ((int)   ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
 270                         ((id->dma_mword >> 8) & 7) ? ide_dma_on :
 271                         ((id->dma_1word >> 8) & 7) ? ide_dma_on :
 272                                                      ide_dma_off_quietly);
 273 }
 274
 275 static int piix_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
 276 {
 277         int ultra = (HWIF(drive)->pci_dev->device == PCI_DEVICE_ID_INTEL_82371AB) ? 1 : 0;
 278         switch (func) {
 279                 case ide_dma_check:
 280                          return ide_dmaproc((ide_dma_action_t) piix_config_drive_for_dma(drive, ultra), drive);
 281                 default :
 282                         break;
 283         }
 284         /* Other cases are done by generic IDE-DMA code. */
 285         return ide_dmaproc(func, drive);
 286 }
 287
 288 void ide_init_piix (ide_hwif_t *hwif)
 289 {
 290         hwif->tuneproc = &piix_tune_drive;
 291         if (hwif->dma_base) {
 292                 hwif->dmaproc = &piix_dmaproc;
 293         }
 294 }