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Import 2.3.9pre5
[davej-history.git] / drivers / block / pdc202xx.c
blobf0591397c01b7592f38cbf60759204edf6102d81
1 /*
2 * linux/drivers/block/pdc202xx.c Version 0.26 May 12, 1999
3 *
4 * Copyright (C) 1998-99 Andre Hedrick
5 * (hedrick@astro.dyer.vanderbilt.edu)
6 *
7 * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
8 * compiled into the kernel if you have more than one card installed.
9 * Note that BIOS v1.29 is reported to fix the problem. Since this is
10 * safe chipset tuning, including this support is harmless
11 *
12 * The latest chipset code will support the following ::
13 * Three Ultra33 controllers and 12 drives.
14 * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
15 * The 8/4 ratio is a BIOS code limit by promise.
16 *
17 * UNLESS you enable "PDC202XX_FORCE_BURST_BIT"
18 *
19 * There is only one BIOS in the three contollers.
20 *
21 * May 8 20:56:17 Orion kernel:
22 * Uniform Multi-Platform E-IDE driver Revision: 6.19
23 * PDC20246: IDE controller on PCI bus 00 dev a0
24 * PDC20246: not 100% native mode: will probe irqs later
25 * PDC20246: ROM enabled at 0xfebd0000
26 * PDC20246: (U)DMA Burst Bit ENABLED Primary PCI Mode Secondary PCI Mode.
27 * ide0: BM-DMA at 0xef80-0xef87, BIOS settings: hda:DMA, hdb:DMA
28 * ide1: BM-DMA at 0xef88-0xef8f, BIOS settings: hdc:pio, hdd:pio
29 * PDC20246: IDE controller on PCI bus 00 dev 98
30 * PDC20246: not 100% native mode: will probe irqs later
31 * PDC20246: ROM enabled at 0xfebc0000
32 * PDC20246: (U)DMA Burst Bit ENABLED Primary PCI Mode Secondary PCI Mode.
33 * ide2: BM-DMA at 0xef40-0xef47, BIOS settings: hde:DMA, hdf:DMA
34 * ide3: BM-DMA at 0xef48-0xef4f, BIOS settings: hdg:DMA, hdh:DMA
35 * PDC20246: IDE controller on PCI bus 00 dev 90
36 * PDC20246: not 100% native mode: will probe irqs later
37 * PDC20246: ROM enabled at 0xfebb0000
38 * PDC20246: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode.
39 * PDC20246: FORCING BURST BIT 0x00 -> 0x01 ACTIVE
40 * ide4: BM-DMA at 0xef00-0xef07, BIOS settings: hdi:DMA, hdj:pio
41 * ide5: BM-DMA at 0xef08-0xef0f, BIOS settings: hdk:pio, hdl:pio
42 * PIIX3: IDE controller on PCI bus 00 dev 39
43 * PIIX3: device not capable of full native PCI mode
44 *
45 * ide0 at 0xeff0-0xeff7,0xefe6 on irq 19
46 * ide1 at 0xefa8-0xefaf,0xebe6 on irq 19
47 * ide2 at 0xefa0-0xefa7,0xef7e on irq 18
48 * ide3 at 0xef68-0xef6f,0xef66 on irq 18
49 * ide4 at 0xef38-0xef3f,0xef62 on irq 17
50 * hda: QUANTUM FIREBALL ST6.4A, 6149MB w/81kB Cache, CHS=13328/15/63, UDMA(33)
51 * hdb: QUANTUM FIREBALL ST3.2A, 3079MB w/81kB Cache, CHS=6256/16/63, UDMA(33)
52 * hde: Maxtor 72004 AP, 1916MB w/128kB Cache, CHS=3893/16/63, DMA
53 * hdf: Maxtor 71626 A, 1554MB w/64kB Cache, CHS=3158/16/63, DMA
54 * hdi: Maxtor 90680D4, 6485MB w/256kB Cache, CHS=13176/16/63, UDMA(33)
55 * hdj: Maxtor 90680D4, 6485MB w/256kB Cache, CHS=13176/16/63, UDMA(33)
56 *
57 * Promise Ultra66 cards with BIOS v1.11 this
58 * compiled into the kernel if you have more than one card installed.
59 *
60 * PDC20262: IDE controller on PCI bus 00 dev a0
61 * PDC20262: not 100% native mode: will probe irqs later
62 * PDC20262: ROM enabled at 0xfebb0000
63 * PDC20262: (U)DMA Burst Bit ENABLED Primary PCI Mode Secondary PCI Mode.
64 * ide0: BM-DMA at 0xef00-0xef07, BIOS settings: hda:pio, hdb:pio
65 * ide1: BM-DMA at 0xef08-0xef0f, BIOS settings: hdc:pio, hdd:pio
66 *
67 * UDMA 4/2 and UDMA 3/1 only differ by the testing bit 13 in word93.
68 * Chipset timing speeds must be identical
69 *
70 * drive_number
71 * = ((HWIF(drive)->channel ? 2 : 0) + (drive->select.b.unit & 0x01));
72 * = ((hwif->channel ? 2 : 0) + (drive->select.b.unit & 0x01));
73 */
74
75 #include <linux/types.h>
76 #include <linux/kernel.h>
77 #include <linux/delay.h>
78 #include <linux/timer.h>
79 #include <linux/mm.h>
80 #include <linux/ioport.h>
81 #include <linux/blkdev.h>
82 #include <linux/hdreg.h>
83 #include <linux/interrupt.h>
84 #include <linux/pci.h>
85 #include <linux/init.h>
86 #include <linux/ide.h>
87
88 #include <asm/io.h>
89 #include <asm/irq.h>
90
91 #define PDC202XX_DEBUG_DRIVE_INFO 0
92 #define PDC202XX_DECODE_REGISTER_INFO 0
93 #define PDC202XX_FORCE_BURST_BIT 0
94 #define PDC202XX_FORCE_MASTER_MODE 0
95
96 extern char *ide_xfer_verbose (byte xfer_rate);
97
98 /* A Register */
99 #define SYNC_ERRDY_EN 0xC0
100
101 #define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
102 #define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
103 #define IORDY_EN 0x20 /* PIO: IOREADY */
104 #define PREFETCH_EN 0x10 /* PIO: PREFETCH */
105
106 #define PA3 0x08 /* PIO"A" timing */
107 #define PA2 0x04 /* PIO"A" timing */
108 #define PA1 0x02 /* PIO"A" timing */
109 #define PA0 0x01 /* PIO"A" timing */
110
111 /* B Register */
112
113 #define MB2 0x80 /* DMA"B" timing */
114 #define MB1 0x40 /* DMA"B" timing */
115 #define MB0 0x20 /* DMA"B" timing */
116
117 #define PB4 0x10 /* PIO_FORCE 1:0 */
118
119 #define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
120 #define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
121 #define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
122 #define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
123
124 /* C Register */
125 #define IORDYp_NO_SPEED 0x4F
126 #define SPEED_DIS 0x0F
127
128 #define DMARQp 0x80
129 #define IORDYp 0x40
130 #define DMAR_EN 0x20
131 #define DMAW_EN 0x10
132
133 #define MC3 0x08 /* DMA"C" timing */
134 #define MC2 0x04 /* DMA"C" timing */
135 #define MC1 0x02 /* DMA"C" timing */
136 #define MC0 0x01 /* DMA"C" timing */
137
138 #if PDC202XX_DECODE_REGISTER_INFO
139
140 #define REG_A 0x01
141 #define REG_B 0x02
142 #define REG_C 0x04
143 #define REG_D 0x08
144
145 static void decode_registers (byte registers, byte value)
146 {
147 byte bit = 0, bit1 = 0, bit2 = 0;
148
149 switch(registers) {
150 case REG_A:
151 bit2 = 0;
152 printk("A Register ");
153 if (value & 0x80) printk("SYNC_IN ");
154 if (value & 0x40) printk("ERRDY_EN ");
155 if (value & 0x20) printk("IORDY_EN ");
156 if (value & 0x10) printk("PREFETCH_EN ");
157 if (value & 0x08) { printk("PA3 ");bit2 |= 0x08; }
158 if (value & 0x04) { printk("PA2 ");bit2 |= 0x04; }
159 if (value & 0x02) { printk("PA1 ");bit2 |= 0x02; }
160 if (value & 0x01) { printk("PA0 ");bit2 |= 0x01; }
161 printk("PIO(A) = %d ", bit2);
162 break;
163 case REG_B:
164 bit1 = 0;bit2 = 0;
165 printk("B Register ");
166 if (value & 0x80) { printk("MB2 ");bit1 |= 0x80; }
167 if (value & 0x40) { printk("MB1 ");bit1 |= 0x40; }
168 if (value & 0x20) { printk("MB0 ");bit1 |= 0x20; }
169 printk("DMA(B) = %d ", bit1 >> 5);
170 if (value & 0x10) printk("PIO_FORCED/PB4 ");
171 if (value & 0x08) { printk("PB3 ");bit2 |= 0x08; }
172 if (value & 0x04) { printk("PB2 ");bit2 |= 0x04; }
173 if (value & 0x02) { printk("PB1 ");bit2 |= 0x02; }
174 if (value & 0x01) { printk("PB0 ");bit2 |= 0x01; }
175 printk("PIO(B) = %d ", bit2);
176 break;
177 case REG_C:
178 bit2 = 0;
179 printk("C Register ");
180 if (value & 0x80) printk("DMARQp ");
181 if (value & 0x40) printk("IORDYp ");
182 if (value & 0x20) printk("DMAR_EN ");
183 if (value & 0x10) printk("DMAW_EN ");
184
185 if (value & 0x08) { printk("MC3 ");bit2 |= 0x08; }
186 if (value & 0x04) { printk("MC2 ");bit2 |= 0x04; }
187 if (value & 0x02) { printk("MC1 ");bit2 |= 0x02; }
188 if (value & 0x01) { printk("MC0 ");bit2 |= 0x01; }
189 printk("DMA(C) = %d ", bit2);
190 break;
191 case REG_D:
192 printk("D Register ");
193 break;
194 default:
195 return;
196 }
197 printk("\n %s ", (registers & REG_D) ? "DP" :
198 (registers & REG_C) ? "CP" :
199 (registers & REG_B) ? "BP" :
200 (registers & REG_A) ? "AP" : "ERROR");
201 for (bit=128;bit>0;bit/=2)
202 printk("%s", (value & bit) ? "1" : "0");
203 printk("\n");
204 }
205
206 #endif /* PDC202XX_DECODE_REGISTER_INFO */
207
208 static int config_chipset_for_dma (ide_drive_t *drive, byte ultra)
209 {
210 struct hd_driveid *id = drive->id;
211 ide_hwif_t *hwif = HWIF(drive);
212 struct pci_dev *dev = hwif->pci_dev;
213
214 int err;
215 unsigned int drive_conf;
216 byte drive_pci;
217 byte test1, test2, speed;
218 byte AP, BP, CP, DP, EP;
219 int drive_number = ((hwif->channel ? 2 : 0) + (drive->select.b.unit & 0x01));
220 byte udma_66 = ((id->word93 & 0x2000) && (dev->device == PCI_DEVICE_ID_PROMISE_20262)) ? 1 : 0;
221 byte udma_33 = ultra ? (inb((dev->base_address[4] & PCI_BASE_ADDRESS_IO_MASK) + 0x001f) & 1) : 0;
222
223 pci_read_config_byte(dev, 0x50, &EP);
224
225 switch(drive_number) {
226 case 0: drive_pci = 0x60;
227 pci_read_config_dword(dev, drive_pci, &drive_conf);
228 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
229 goto chipset_is_set;
230 pci_read_config_byte(dev, (drive_pci), &test1);
231 if (!(test1 & SYNC_ERRDY_EN))
232 pci_write_config_byte(dev, (drive_pci), test1|SYNC_ERRDY_EN);
233 break;
234 case 1: drive_pci = 0x64;
235 pci_read_config_dword(dev, drive_pci, &drive_conf);
236 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
237 goto chipset_is_set;
238 pci_read_config_byte(dev, 0x60, &test1);
239 pci_read_config_byte(dev, (drive_pci), &test2);
240 if ((test1 & SYNC_ERRDY_EN) && !(test2 & SYNC_ERRDY_EN))
241 pci_write_config_byte(dev, (drive_pci), test2|SYNC_ERRDY_EN);
242 break;
243 case 2: drive_pci = 0x68;
244 pci_read_config_dword(dev, drive_pci, &drive_conf);
245 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
246 goto chipset_is_set;
247 pci_read_config_byte(dev, (drive_pci), &test1);
248 if (!(test1 & SYNC_ERRDY_EN))
249 pci_write_config_byte(dev, (drive_pci), test1|SYNC_ERRDY_EN);
250 break;
251 case 3: drive_pci = 0x6c;
252 pci_read_config_dword(dev, drive_pci, &drive_conf);
253 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
254 goto chipset_is_set;
255 pci_read_config_byte(dev, 0x68, &test1);
256 pci_read_config_byte(dev, (drive_pci), &test2);
257 if ((test1 & SYNC_ERRDY_EN) && !(test2 & SYNC_ERRDY_EN))
258 pci_write_config_byte(dev, (drive_pci), test2|SYNC_ERRDY_EN);
259 break;
260 default:
261 return ide_dma_off;
262 }
263
264 if (drive->media != ide_disk)
265 return ide_dma_off_quietly;
266
267 pci_read_config_byte(dev, (drive_pci), &AP);
268 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
269 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
270 pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
271
272 if (id->capability & 4) { /* IORDY_EN */
273 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
274 pci_read_config_byte(dev, (drive_pci), &AP);
275 }
276
277 if (drive->media == ide_disk) { /* PREFETCH_EN */
278 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
279 pci_read_config_byte(dev, (drive_pci), &AP);
280 }
281
282 if ((BP & 0xF0) && (CP & 0x0F)) {
283 /* clear DMA modes of upper 842 bits of B Register */
284 /* clear PIO forced mode upper 1 bit of B Register */
285 pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0xF0);
286 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
287
288 /* clear DMA modes of lower 8421 bits of C Register */
289 pci_write_config_byte(dev, (drive_pci)|0x02, CP & ~0x0F);
290 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
291 }
292
293 pci_read_config_byte(dev, (drive_pci), &AP);
294 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
295 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
296
297 if ((id->dma_ultra & 0x0010) && (udma_66) && (udma_33)) {
298 if (!((id->dma_ultra >> 8) & 16)) {
299 drive->id->dma_ultra &= ~0xFF00;
300 drive->id->dma_ultra |= 0x1010;
301 drive->id->dma_mword &= ~0x0F00;
302 drive->id->dma_1word &= ~0x0F00;
303 }
304 /* speed 8 == UDMA mode 4 == speed 6 plus cable */
305 pci_write_config_byte(dev, (drive_pci)|0x01, BP|0x20);
306 pci_write_config_byte(dev, (drive_pci)|0x02, CP|0x01);
307 speed = XFER_UDMA_4;
308 } else if ((id->dma_ultra & 0x0008) && (udma_66) && (udma_33)) {
309 if (!((id->dma_ultra >> 8) & 8)) {
310 drive->id->dma_ultra &= ~0xFF00;
311 drive->id->dma_ultra |= 0x0808;
312 drive->id->dma_mword &= ~0x0F00;
313 drive->id->dma_1word &= ~0x0F00;
314 }
315 /* speed 7 == UDMA mode 3 == speed 5 plus cable */
316 pci_write_config_byte(dev, (drive_pci)|0x01, BP|0x40);
317 pci_write_config_byte(dev, (drive_pci)|0x02, CP|0x02);
318 speed = XFER_UDMA_3;
319 } else if ((id->dma_ultra & 0x0004) && (udma_33)) {
320 if (!((id->dma_ultra >> 8) & 4)) {
321 drive->id->dma_ultra &= ~0x0F00;
322 drive->id->dma_ultra |= 0x0404;
323 drive->id->dma_mword &= ~0x0F00;
324 drive->id->dma_1word &= ~0x0F00;
325 }
326 /* speed 6 == UDMA mode 2 */
327 pci_write_config_byte(dev, (drive_pci)|0x01, BP|0x20);
328 pci_write_config_byte(dev, (drive_pci)|0x02, CP|0x01);
329 speed = XFER_UDMA_2;
330 } else if ((id->dma_ultra & 0x0002) && (udma_33)) {
331 if (!((id->dma_ultra >> 8) & 2)) {
332 drive->id->dma_ultra &= ~0x0F00;
333 drive->id->dma_ultra |= 0x0202;
334 drive->id->dma_mword &= ~0x0F00;
335 drive->id->dma_1word &= ~0x0F00;
336 }
337 /* speed 5 == UDMA mode 1 */
338 pci_write_config_byte(dev, (drive_pci)|0x01, BP|0x40);
339 pci_write_config_byte(dev, (drive_pci)|0x02, CP|0x02);
340 speed = XFER_UDMA_1;
341 } else if ((id->dma_ultra & 0x0001) && (udma_33)) {
342 if (!((id->dma_ultra >> 8) & 1)) {
343 drive->id->dma_ultra &= ~0x0F00;
344 drive->id->dma_ultra |= 0x0101;
345 drive->id->dma_mword &= ~0x0F00;
346 drive->id->dma_1word &= ~0x0F00;
347 }
348 /* speed 4 == UDMA mode 0 */
349 pci_write_config_byte(dev, (drive_pci)|0x01, BP|0x60);
350 pci_write_config_byte(dev, (drive_pci)|0x02, CP|0x03);
351 speed = XFER_UDMA_0;
352 } else if (id->dma_mword & 0x0004) {
353 if (!((id->dma_mword >> 8) & 4)) {
354 drive->id->dma_mword &= ~0x0F00;
355 drive->id->dma_mword |= 0x0404;
356 drive->id->dma_1word &= ~0x0F00;
357 }
358 /* speed 4 == DMA mode 2 multi-word */
359 pci_write_config_byte(dev, (drive_pci)|0x01, BP|0x60);
360 pci_write_config_byte(dev, (drive_pci)|0x02, CP|0x03);
361 speed = XFER_MW_DMA_2;
362 } else if (id->dma_mword & 0x0002) {
363 if (!((id->dma_mword >> 8) & 2)) {
364 drive->id->dma_mword &= ~0x0F00;
365 drive->id->dma_mword |= 0x0202;
366 drive->id->dma_1word &= ~0x0F00;
367 }
368 /* speed 3 == DMA mode 1 multi-word */
369 pci_write_config_byte(dev, (drive_pci)|0x01, BP|0x60);
370 pci_write_config_byte(dev, (drive_pci)|0x02, CP|0x04);
371 speed = XFER_MW_DMA_1;
372 } else if (id->dma_mword & 0x0001) {
373 if (!((id->dma_mword >> 8) & 1)) {
374 drive->id->dma_mword &= ~0x0F00;
375 drive->id->dma_mword |= 0x0101;
376 drive->id->dma_1word &= ~0x0F00;
377 }
378 /* speed 2 == DMA mode 0 multi-word */
379 pci_write_config_byte(dev, (drive_pci)|0x01, BP|0x60);
380 pci_write_config_byte(dev, (drive_pci)|0x02, CP|0x05);
381 speed = XFER_MW_DMA_0;
382 } else if (id->dma_1word & 0x0004) {
383 if (!((id->dma_1word >> 8) & 4)) {
384 drive->id->dma_mword &= ~0x0F00;
385 drive->id->dma_1word &= ~0x0F00;
386 drive->id->dma_1word |= 0x0404;
387 }
388 /* speed 2 == DMA mode 2 single-word */
389 pci_write_config_byte(dev, (drive_pci)|0x01, BP|0x60);
390 pci_write_config_byte(dev, (drive_pci)|0x02, CP|0x05);
391 speed = XFER_SW_DMA_2;
392 } else if (id->dma_1word & 0x0002) {
393 if (!((id->dma_1word >> 8) & 2)) {
394 drive->id->dma_mword &= ~0x0F00;
395 drive->id->dma_1word &= ~0x0F00;
396 drive->id->dma_1word |= 0x0202;
397 }
398 /* speed 1 == DMA mode 1 single-word */
399 pci_write_config_byte(dev, (drive_pci)|0x01, BP|0x80);
400 pci_write_config_byte(dev, (drive_pci)|0x02, CP|0x06);
401 speed = XFER_SW_DMA_1;
402 } else if (id->dma_1word & 0x0001) {
403 if (!((id->dma_1word >> 8) & 1)) {
404 drive->id->dma_mword &= ~0x0F00;
405 drive->id->dma_1word &= ~0x0F00;
406 drive->id->dma_1word |= 0x0101;
407 }
408 /* speed 0 == DMA mode 0 single-word */
409 pci_write_config_byte(dev, (drive_pci)|0x01, BP|0xC0);
410 pci_write_config_byte(dev, (drive_pci)|0x02, CP|0x0B);
411 speed = XFER_SW_DMA_0;
412 } else {
413 /* restore original pci-config space */
414 pci_write_config_dword(dev, drive_pci, drive_conf);
415 return ide_dma_off_quietly;
416 }
417
418 err = ide_wait_cmd(drive, WIN_SETFEATURES, speed, SETFEATURES_XFER, 0, NULL);
419
420 #if PDC202XX_DECODE_REGISTER_INFO
421 pci_read_config_byte(dev, (drive_pci), &AP);
422 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
423 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
424
425 decode_registers(REG_A, AP);
426 decode_registers(REG_B, BP);
427 decode_registers(REG_C, CP);
428 decode_registers(REG_D, DP);
429 #endif /* PDC202XX_DECODE_REGISTER_INFO */
430
431 #if PDC202XX_DEBUG_DRIVE_INFO
432 printk("%s: %s drive%d 0x%08x ",
433 drive->name, ide_xfer_verbose(speed),
434 drive_number, drive_conf);
435 pci_read_config_dword(dev, drive_pci, &drive_conf);
436 printk("0x%08x\n", drive_conf);
437 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
438
439 chipset_is_set:
440
441 return ((int) ((id->dma_ultra >> 11) & 3) ? ide_dma_on :
442 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
443 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
444 ((id->dma_1word >> 8) & 7) ? ide_dma_on :
445 ide_dma_off_quietly);
446 }
447
448 /* 0 1 2 3 4 5 6 7 8
449 * 960, 480, 390, 300, 240, 180, 120, 90, 60
450 * 180, 150, 120, 90, 60
451 * DMA_Speed
452 * 180, 120, 90, 90, 90, 60, 30
453 * 11, 5, 4, 3, 2, 1, 0
454 */
455
456 static int config_drive_xfer_rate (ide_drive_t *drive)
457 {
458 struct hd_driveid *id = drive->id;
459 ide_hwif_t *hwif = HWIF(drive);
460 ide_dma_action_t dma_func = ide_dma_off_quietly;
461
462 if (id && (id->capability & 1) && hwif->autodma) {
463 /* Consult the list of known "bad" drives */
464 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
465 return HWIF(drive)->dmaproc(ide_dma_off, drive);
466 }
467
468 if (id->field_valid & 4) {
469 if (id->dma_ultra & 0x001F) {
470 /* Force if Capable UltraDMA */
471 dma_func = config_chipset_for_dma(drive, 1);
472 if ((id->field_valid & 2) &&
473 (dma_func != ide_dma_on))
474 goto try_dma_modes;
475 }
476 } else if (id->field_valid & 2) {
477 try_dma_modes:
478 if ((id->dma_mword & 0x0004) ||
479 (id->dma_1word & 0x0004)) {
480 /* Force if Capable regular DMA modes */
481 dma_func = config_chipset_for_dma(drive, 0);
482 }
483 } else if ((ide_dmaproc(ide_dma_good_drive, drive)) &&
484 (id->eide_dma_time > 150)) {
485 /* Consult the list of known "good" drives */
486 dma_func = config_chipset_for_dma(drive, 0);
487 }
488 }
489 return HWIF(drive)->dmaproc(dma_func, drive);
490 }
491
492 /*
493 * pdc202xx_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
494 */
495 int pdc202xx_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
496 {
497 switch (func) {
498 case ide_dma_check:
499 return config_drive_xfer_rate(drive);
500 default:
501 break;
502 }
503 return ide_dmaproc(func, drive); /* use standard DMA stuff */
504 }
505
506 __initfunc(unsigned int pci_init_pdc202xx (struct pci_dev *dev, const char *name))
507 {
508 unsigned long high_16 = dev->base_address[4] & PCI_BASE_ADDRESS_IO_MASK;
509 byte udma_speed_flag = inb(high_16 + 0x001f);
510 byte primary_mode = inb(high_16 + 0x001a);
511 byte secondary_mode = inb(high_16 + 0x001b);
512
513 if (dev->rom_address) {
514 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->rom_address | PCI_ROM_ADDRESS_ENABLE);
515 printk("%s: ROM enabled at 0x%08lx\n", name, dev->rom_address);
516 }
517
518 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
519 byte irq = 0, irq2 = 0;
520 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
521 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2); /* 0xbc */
522 if (irq != irq2) {
523 pci_write_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
524 printk("%s: pci-config space interrupt mirror fixed.\n", name);
525 }
526 }
527
528 printk("%s: (U)DMA Burst Bit %sABLED " \
529 "Primary %s Mode " \
530 "Secondary %s Mode.\n",
531 name,
532 (udma_speed_flag & 1) ? "EN" : "DIS",
533 (primary_mode & 1) ? "MASTER" : "PCI",
534 (secondary_mode & 1) ? "MASTER" : "PCI" );
535
536 #if PDC202XX_FORCE_BURST_BIT
537 if (!(udma_speed_flag & 1)) {
538 printk("%s: FORCING BURST BIT 0x%02x -> 0x%02x ", name, udma_speed_flag, (udma_speed_flag|1));
539 outb(udma_speed_flag|1, high_16 + 0x001f);
540 printk("%sCTIVE\n", (inb(high_16 + 0x001f) & 1) ? "A" : "INA");
541 }
542 #endif /* PDC202XX_FORCE_BURST_BIT */
543
544 #if PDC202XX_FORCE_MASTER_MODE
545 if (!(primary_mode & 1)) {
546 printk("%s: FORCING PRIMARY MODE BIT 0x%02x -> 0x%02x ",
547 name, primary_mode, (primary_mode|1));
548 outb(primary_mode|1, high_16 + 0x001a);
549 printk("%s\n", (inb(high_16 + 0x001a) & 1) ? "MASTER" : "PCI");
550 }
551
552 if (!(secondary_mode & 1)) {
553 printk("%s: FORCING SECONDARY MODE BIT 0x%02x -> 0x%02x ",
554 name, secondary_mode, (secondary_mode|1));
555 outb(secondary_mode|1, high_16 + 0x001b);
556 printk("%s\n", (inb(high_16 + 0x001b) & 1) ? "MASTER" : "PCI");
557 }
558 #endif /* PDC202XX_FORCE_MASTER_MODE */
559 return dev->irq;
560 }
561
562 __initfunc(void ide_init_pdc202xx (ide_hwif_t *hwif))
563 {
564 if (hwif->dma_base) {
565 hwif->dmaproc = &pdc202xx_dmaproc;
566 }
567 }
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