drivers/block/cy82c693.c

   1 /*
   2  * linux/drivers/block/cy82c693.c       Version 0.33    Jan. 23, 1999
   3  *
   4  *  Copyright (C) 1998, 1999 Andreas S. Krebs (akrebs@altavista.net), Maintainer
   5  *  Copyright (C) 1998 Andre Hedrick, Integrater
   6  *
   7  * CYPRESS CY82C693 chipset IDE controller
   8  *
   9  * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
  10  * Writting the driver was quite simple, since most of the job is
  11  * done by the generic pci-ide support.
  12  * The hard part was finding the CY82C693's datasheet on Cypress's
  13  * web page :-(. But Altavista solved this problem :-).
  14  *
  15  *
  16  * Notes:
  17  * - I recently got a 16.8G IBM DTTA, so I was able to test it with
  18  *   a large and fast disk - the results look great, so I'd say the
  19  *   driver is working fine :-)
  20  *   hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
  21  * - this is my first linux driver, so there's probably a lot  of room
  22  *   for optimizations and bug fixing, so feel free to do it.
  23  * - use idebus=xx parameter to set PCI bus speed - needed to calc
  24  *   timings for PIO modes (default will be 40)
  25  * - if using PIO mode it's a good idea to set the PIO mode and
  26  *   32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
  27  * - I had some problems with my IBM DHEA with PIO modes < 2
  28  *   (lost interrupts) ?????
  29  * - first tests with DMA look okay, they seem to work, but there is a
  30  *   problem with sound - the BusMaster IDE TimeOut should fixed this
  31  *
  32  *
  33  * History:
  34  * ASK@1999-01-23: v0.33 made a few minor code clean ups
  35  *                       removed DMA clock speed setting by default
  36  *                       added boot message
  37  * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
  38  *                       added support to set DMA Controller Clock Speed
  39  * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes on some drive
  40  * ASK@1998-10-29: v0.3 added support to set DMA modes
  41  * ASK@1998-10-28: v0.2 added support to set PIO modes
  42  * ASK@1998-10-27: v0.1 first version - chipset detection
  43  *
  44  */
  45
  46 #include <linux/types.h>
  47 #include <linux/pci.h>
  48 #include <linux/delay.h>
  49 #include <linux/ide.h>
  50
  51 #include <asm/io.h>
  52
  53 #include "ide_modes.h"
  54
  55 /* the current version */
  56 #define CY82_VERSION    "CY82C693U driver v0.33 99-01-23 Andreas S. Krebs (akrebs@altavista.net)"
  57
  58 /*
  59  *      The following are used to debug the driver.
  60  */
  61 #define CY82C693_DEBUG_LOGS     0
  62 #define CY82C693_DEBUG_INFO     0
  63
  64 /* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
  65 #undef CY82C693_SETDMA_CLOCK
  66
  67 /*
  68  * note: the value for busmaster timeout is tricky and i got it by trial and error !
  69  *       using a to low value will cause DMA timeouts and drop IDE performance
  70  *       using a to high value will cause audio playback to scatter
  71  *       if you know a better value or how to calc it, please let me know
  72  */
  73 #define BUSMASTER_TIMEOUT       0x50    /* twice the value written in cy82c693ub datasheet */
  74 /*
  75  * the value above was tested on my machine and it seems to work okay
  76  */
  77
  78 /* here are the offset definitions for the registers */
  79 #define CY82_IDE_CMDREG         0x04
  80 #define CY82_IDE_ADDRSETUP      0x48
  81 #define CY82_IDE_MASTER_IOR     0x4C
  82 #define CY82_IDE_MASTER_IOW     0x4D
  83 #define CY82_IDE_SLAVE_IOR      0x4E
  84 #define CY82_IDE_SLAVE_IOW      0x4F
  85 #define CY82_IDE_MASTER_8BIT    0x50
  86 #define CY82_IDE_SLAVE_8BIT     0x51
  87
  88 #define CY82_INDEX_PORT         0x22
  89 #define CY82_DATA_PORT          0x23
  90
  91 #define CY82_INDEX_CTRLREG1     0x01
  92 #define CY82_INDEX_CHANNEL0     0x30
  93 #define CY82_INDEX_CHANNEL1     0x31
  94 #define CY82_INDEX_TIMEOUT      0x32
  95
  96 /* the max PIO mode - from datasheet */
  97 #define CY82C693_MAX_PIO        4
  98
  99 /* the min and max PCI bus speed in MHz - from datasheet */
 100 #define CY82C963_MIN_BUS_SPEED  25
 101 #define CY82C963_MAX_BUS_SPEED  33
 102
 103 /* the struct for the PIO mode timings */
 104 typedef struct pio_clocks_s {
 105         byte    address_time;           /* Address setup (clocks) */
 106         byte    time_16r;               /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
 107         byte    time_16w;               /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
 108         byte    time_8;                 /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
 109 } pio_clocks_t;
 110
 111 /*
 112  * calc clocks using bus_speed
 113  * returns (rounded up) time in bus clocks for time in ns
 114  */
 115 static int calc_clk (int time, int bus_speed)
 116 {
 117         int clocks;
 118
 119         clocks = (time*bus_speed+999)/1000 -1;
 120
 121         if (clocks < 0)
 122                 clocks = 0;
 123
 124         if (clocks > 0x0F)
 125                 clocks = 0x0F;
 126
 127         return clocks;
 128 }
 129
 130 /*
 131  * compute the values for the clock registers for PIO
 132  * mode and pci_clk [MHz] speed
 133  *
 134  * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
 135  *       for mode 3 and 4 drives 8 and 16-bit timings are the same
 136  *
 137  */
 138 static void compute_clocks (byte pio, pio_clocks_t *p_pclk)
 139 {
 140         int clk1, clk2;
 141         int bus_speed;
 142
 143         bus_speed = ide_system_bus_speed();     /* get speed of PCI bus */
 144         /* we don't check against CY82C693's min and max speed,
 145          * so you can play with the idebus=xx parameter
 146          */
 147
 148         if (pio > CY82C693_MAX_PIO)
 149                 pio = CY82C693_MAX_PIO;
 150
 151         /* let's calc the address setup time clocks */
 152         p_pclk->address_time = (byte)calc_clk(ide_pio_timings[pio].setup_time, bus_speed);
 153
 154         /* let's calc the active and recovery time clocks */
 155         clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed);
 156
 157         /* calc recovery timing */
 158         clk2 =  ide_pio_timings[pio].cycle_time -
 159                 ide_pio_timings[pio].active_time -
 160                 ide_pio_timings[pio].setup_time;
 161
 162         clk2 = calc_clk(clk2, bus_speed);
 163
 164         clk1 = (clk1<<4)|clk2;  /* combine active and recovery clocks */
 165
 166         /* note: we use the same values for 16bit IOR and IOW
 167          *      those are all the same, since I don't have other
 168          *      timings than those from ide_modes.h
 169          */
 170
 171         p_pclk->time_16r = (byte)clk1;
 172         p_pclk->time_16w = (byte)clk1;
 173
 174         /* what are good values for 8bit ?? */
 175         p_pclk->time_8 = (byte)clk1;
 176 }
 177
 178 /*
 179  * set DMA mode a specific channel for CY82C693
 180  */
 181 static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
 182 {
 183         byte index;
 184         byte data;
 185
 186         if (mode>2)     /* make sure we set a valid mode */
 187                 mode = 2;
 188
 189         if (mode > drive->id->tDMA)  /* to be absolutly sure we have a valid mode */
 190                 mode = drive->id->tDMA;
 191
 192         index = (HWIF(drive)->channel==0) ? CY82_INDEX_CHANNEL0 : CY82_INDEX_CHANNEL1;
 193
 194 #if CY82C693_DEBUG_LOGS
 195         /* for debug let's show the previous values */
 196
 197         OUT_BYTE(index, CY82_INDEX_PORT);
 198         data = IN_BYTE(CY82_DATA_PORT);
 199
 200         printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n", drive->name, HWIF(drive)->channel, drive->select.b.unit, (data&0x3), ((data>>2)&1));
 201 #endif /* CY82C693_DEBUG_LOGS */
 202
 203         data = (byte)mode|(byte)(single<<2);
 204
 205         OUT_BYTE(index, CY82_INDEX_PORT);
 206         OUT_BYTE(data, CY82_DATA_PORT);
 207
 208 #if CY82C693_DEBUG_INFO
 209         printk (KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n", drive->name, HWIF(drive)->channel, drive->select.b.unit, mode, single);
 210 #endif /* CY82C693_DEBUG_INFO */
 211
 212         /*
 213          * note: below we set the value for Bus Master IDE TimeOut Register
 214          * I'm not absolutly sure what this does, but it solved my problem
 215          * with IDE DMA and sound, so I now can play sound and work with
 216          * my IDE driver at the same time :-)
 217          *
 218          * If you know the correct (best) value for this register please
 219          * let me know - ASK
 220          */
 221
 222         data = BUSMASTER_TIMEOUT;
 223         OUT_BYTE(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
 224         OUT_BYTE(data, CY82_DATA_PORT);
 225
 226 #if CY82C693_DEBUG_INFO
 227         printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n", drive->name, data);
 228 #endif /* CY82C693_DEBUG_INFO */
 229 }
 230
 231 /*
 232  * used to set DMA mode for CY82C693 (single and multi modes)
 233  */
 234 static int cy82c693_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
 235 {
 236         /*
 237          * if the function is dma on, set dma mode for drive everything
 238          * else is done by the defaul func
 239          */
 240         if (func == ide_dma_on) {
 241                 struct hd_driveid *id = drive->id;
 242
 243 #if CY82C693_DEBUG_INFO
 244                 printk (KERN_INFO "dma_on: %s\n", drive->name);
 245 #endif /* CY82C693_DEBUG_INFO */
 246
 247                 if (id != NULL) {
 248                        /* Enable DMA on any drive that has DMA (multi or single) enabled */
 249                        if (id->field_valid & 2) {       /* regular DMA */
 250                                int mmode, smode;
 251
 252                                mmode = id->dma_mword & (id->dma_mword >> 8);
 253                                smode = id->dma_1word & (id->dma_1word >> 8);
 254
 255                                if (mmode != 0)
 256                                      cy82c693_dma_enable(drive, (mmode >> 1), 0); /* enable multi */
 257                                else if (smode != 0)
 258                                      cy82c693_dma_enable(drive, (smode >> 1), 1); /* enable single */
 259                         }
 260                 }
 261         }
 262         return ide_dmaproc(func, drive);
 263 }
 264
 265 /*
 266  * tune ide drive - set PIO mode
 267  */
 268 static void cy82c693_tune_drive (ide_drive_t *drive, byte pio)
 269 {
 270         ide_hwif_t *hwif = HWIF(drive);
 271         struct pci_dev *dev = hwif->pci_dev;
 272         pio_clocks_t pclk;
 273         unsigned int addrCtrl;
 274
 275         /* select primary or secondary channel */
 276         if (hwif->index > 0)  /* drive is on the secondary channel */
 277                 dev = dev->next;
 278
 279 #if CY82C693_DEBUG_LOGS
 280         /* for debug let's show the register values */
 281
 282         if (drive->select.b.unit == 0) {
 283                 /*
 284                  * get master drive registers
 285                  * address setup control register
 286                  * is 32 bit !!!
 287                  */
 288                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 289                 addrCtrl &= 0x0F;
 290
 291                 /* now let's get the remaining registers */
 292                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
 293                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
 294                 pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
 295         } else {
 296                 /*
 297                  * set slave drive registers
 298                  * address setup control register
 299                  * is 32 bit !!!
 300                  */
 301                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 302
 303                 addrCtrl &= 0xF0;
 304                 addrCtrl >>= 4;
 305
 306                 /* now let's get the remaining registers */
 307                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
 308                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
 309                 pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
 310         }
 311
 312         printk (KERN_INFO "%s (ch=%d, dev=%d): PIO timing is (addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n", drive->name, hwif->channel, drive->select.b.unit, addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 313 #endif /* CY82C693_DEBUG_LOGS */
 314
 315         /* first let's calc the pio modes */
 316         pio = ide_get_best_pio_mode(drive, pio, CY82C693_MAX_PIO, NULL);
 317
 318 #if CY82C693_DEBUG_INFO
 319         printk (KERN_INFO "%s: Selected PIO mode %d\n", drive->name, pio);
 320 #endif /* CY82C693_DEBUG_INFO */
 321
 322         compute_clocks(pio, &pclk);  /* let's calc the values for this PIO mode */
 323
 324         /* now let's write  the clocks registers */
 325         if (drive->select.b.unit == 0) {
 326                 /*
 327                  * set master drive
 328                  * address setup control register
 329                  * is 32 bit !!!
 330                  */
 331                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 332
 333                 addrCtrl &= (~0xF);
 334                 addrCtrl |= (unsigned int)pclk.address_time;
 335                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 336
 337                 /* now let's set the remaining registers */
 338                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
 339                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
 340                 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
 341
 342                 addrCtrl &= 0xF;
 343         } else {
 344                 /*
 345                  * set slave drive
 346                  * address setup control register
 347                  * is 32 bit !!!
 348                  */
 349                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 350
 351                 addrCtrl &= (~0xF0);
 352                 addrCtrl |= ((unsigned int)pclk.address_time<<4);
 353                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 354
 355                 /* now let's set the remaining registers */
 356                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
 357                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
 358                 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
 359
 360                 addrCtrl >>= 4;
 361                 addrCtrl &= 0xF;
 362         }
 363
 364 #if CY82C693_DEBUG_INFO
 365         printk (KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to (addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n", drive->name, hwif->channel, drive->select.b.unit, addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 366 #endif /* CY82C693_DEBUG_INFO */
 367 }
 368
 369 /*
 370  * this function is called during init and is used to setup the cy82c693 chip
 371  */
 372 static void init_cy82c693_chip (struct pci_dev *dev)
 373 {
 374         static int initDone = 0;
 375 #ifdef CY82C693_SETDMA_CLOCK
 376         byte data;
 377 #endif /* CY82C693_SETDMA_CLOCK */
 378
 379         if (initDone != 0)      /* only perform setup once */
 380                 return;
 381         initDone = 1;
 382
 383         /* write info about this verion of the driver */
 384         printk (KERN_INFO CY82_VERSION "\n");
 385
 386 #ifdef CY82C693_SETDMA_CLOCK
 387        /* okay let's set the DMA clock speed */
 388
 389         OUT_BYTE(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 390         data = IN_BYTE(CY82_DATA_PORT);
 391
 392 #if CY82C693_DEBUG_INFO
 393         printk (KERN_INFO "CY82U693: Peripheral Configuration Register: 0x%X\n", data);
 394 #endif /* CY82C693_DEBUG_INFO */
 395
 396         /*
 397          * for some reason sometimes the DMA controller
 398          * speed is set to ATCLK/2 ???? - we fix this here
 399          *
 400          * note: i don't know what causes this strange behaviour,
 401          *       but even changing the dma speed doesn't solve it :-(
 402          *       the ide performance is still only half the normal speed
 403          *
 404          *       if anybody knows what goes wrong with my machine, please
 405          *       let me know - ASK
 406          */
 407
 408         data |= 0x03;
 409
 410         OUT_BYTE(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 411         OUT_BYTE(data, CY82_DATA_PORT);
 412
 413 #if CY82C693_DEBUG_INFO
 414         printk (KERN_INFO "CY82U693: New Peripheral Configuration Register: 0x%X\n", data);
 415 #endif /* CY82C693_DEBUG_INFO */
 416
 417 #endif /* CY82C693_SETDMA_CLOCK */
 418 }
 419
 420 /*
 421  * the init function - called for each ide channel once
 422  */
 423 __initfunc(void ide_init_cy82c693(ide_hwif_t *hwif))
 424 {
 425         hwif->chipset = ide_cy82c693;
 426         if (hwif->dma_base)
 427                 hwif->dmaproc = &cy82c693_dmaproc;
 428         hwif->tuneproc = &cy82c693_tune_drive;
 429
 430         init_cy82c693_chip(hwif->pci_dev);
 431 }
 432