drivers/block/cmd646.c

   1 /* $Id: cmd646.c,v 1.13 1999/05/27 04:49:38 davem Exp $
   2  * cmd646.c: Enable interrupts at initialization time on Ultra/PCI machines.
   3  *           Note, this driver is not used at all on other systems because
   4  *           there the "BIOS" has done all of the following already.
   5  *           Due to massive hardware bugs, UltraDMA is only supported
   6  *           on the 646U2 and not on the 646U.
   7  *
   8  * Copyright (C) 1998       Eddie C. Dost  (ecd@skynet.be)
   9  * Copyright (C) 1998       David S. Miller (davem@dm.cobaltmicro.com)
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/pci.h>
  14 #include <linux/delay.h>
  15 #include <linux/hdreg.h>
  16 #include <linux/ide.h>
  17
  18 #include <asm/io.h>
  19
  20 static int cmd646_config_drive_for_dma(ide_drive_t *drive)
  21 {
  22         struct hd_driveid *id = drive->id;
  23         ide_hwif_t *hwif = HWIF(drive);
  24
  25         /* Even if the drive is not _currently_ in a DMA
  26          * mode, we succeed, and we'll enable it manually
  27          * below in cmd646_dma_onoff.
  28          *
  29          * This is done for disks only, CDROMs and other
  30          * IDE devices are just too quirky.
  31          */
  32         if((id != NULL) &&
  33            ((id->capability & 1) != 0) &&
  34            hwif->autodma &&
  35            (drive->media == ide_disk)) {
  36                 if(id->field_valid & 0x0004) {
  37                         if(id->dma_ultra & 0x0007)
  38                                 return hwif->dmaproc(ide_dma_on, drive);
  39                 }
  40                 if(id->field_valid & 0x0002)
  41                         if((id->dma_mword & 0x0004) || (id->dma_1word & 0x0004))
  42                                 return hwif->dmaproc(ide_dma_on, drive);
  43         }
  44         return hwif->dmaproc(ide_dma_off_quietly, drive);
  45 }
  46
  47 /* This is fun.  -DaveM */
  48 #define IDE_SETXFER             SETFEATURES_XFER
  49 #define IDE_SETFEATURE          WIN_SETFEATURES
  50 #define IDE_DMA2_ENABLE         XFER_MW_DMA_2
  51 #define IDE_DMA1_ENABLE         XFER_MW_DMA_1
  52 #define IDE_DMA0_ENABLE         XFER_MW_DMA_0
  53 #define IDE_UDMA2_ENABLE        XFER_UDMA_2
  54 #define IDE_UDMA1_ENABLE        XFER_UDMA_1
  55 #define IDE_UDMA0_ENABLE        XFER_UDMA_0
  56
  57 static __inline__ unsigned char dma2_bits_to_command(unsigned char bits)
  58 {
  59         if(bits & 0x04)
  60                 return IDE_DMA2_ENABLE;
  61         if(bits & 0x02)
  62                 return IDE_DMA1_ENABLE;
  63         return IDE_DMA0_ENABLE;
  64 }
  65
  66 static __inline__ unsigned char udma2_bits_to_command(unsigned char bits)
  67 {
  68         if(bits & 0x04)
  69                 return IDE_UDMA2_ENABLE;
  70         if(bits & 0x02)
  71                 return IDE_UDMA1_ENABLE;
  72         return IDE_UDMA0_ENABLE;
  73 }
  74
  75 static __inline__ int wait_for_ready(ide_drive_t *drive)
  76 {
  77         int timeout = 100;
  78         byte stat;
  79
  80         while(--timeout) {
  81                 stat = GET_STAT();
  82
  83                 printk("STAT(%2x) ", stat);
  84                 if(!(stat & BUSY_STAT)) {
  85                         if((stat & READY_STAT) || (stat & ERR_STAT))
  86                                 break;
  87                 }
  88                 udelay(100);
  89         }
  90         if((stat & ERR_STAT) || timeout <= 0)
  91                 return 1;
  92         return 0;
  93 }
  94
  95 static void cmd646_do_setfeature(ide_drive_t *drive, byte command)
  96 {
  97         unsigned long flags;
  98         byte old_select;
  99
 100         save_flags(flags);
 101         cli();
 102         printk("SELECT ");
 103         old_select = IN_BYTE(IDE_SELECT_REG);
 104         OUT_BYTE(drive->select.all, IDE_SELECT_REG);
 105         printk("SETXFER ");
 106         OUT_BYTE(IDE_SETXFER, IDE_FEATURE_REG);
 107         printk("CMND ");
 108         OUT_BYTE(command, IDE_NSECTOR_REG);
 109         printk("wait ");
 110         if(wait_for_ready(drive))
 111                 goto out;
 112         printk("SETFEATURE ");
 113         OUT_BYTE(IDE_SETFEATURE, IDE_COMMAND_REG);
 114         printk("wait ");
 115         (void) wait_for_ready(drive);
 116 out:
 117         OUT_BYTE(old_select, IDE_SELECT_REG);
 118         restore_flags(flags);
 119 }
 120
 121 static void cmd646_dma2_enable(ide_drive_t *drive, unsigned long dma_base)
 122 {
 123         byte unit = (drive->select.b.unit & 0x01);
 124         byte bits = (drive->id->dma_mword | drive->id->dma_1word) & 0x07;
 125
 126         printk("CMD646: MDMA enable [");
 127         if((((drive->id->dma_mword & 0x0007) << 8) !=
 128             (drive->id->dma_mword & 0x0700)))
 129                 cmd646_do_setfeature(drive, dma2_bits_to_command(bits));
 130         printk("DMA_CAP ");
 131         outb(inb(dma_base+2)|(1<<(5+unit)), dma_base+2);
 132         printk("DONE]\n");
 133 }
 134
 135 static void cmd646_udma_enable(ide_drive_t *drive, unsigned long dma_base)
 136 {
 137         byte unit = (drive->select.b.unit & 0x01);
 138         byte udma_ctrl, bits = drive->id->dma_ultra & 0x07;
 139         byte udma_timing_bits;
 140
 141         printk("CMD646: UDMA enable [");
 142         if(((drive->id->dma_ultra & 0x0007) << 8) !=
 143            (drive->id->dma_ultra & 0x0700))
 144                 cmd646_do_setfeature(drive, udma2_bits_to_command(bits));
 145
 146         /* Enable DMA and UltraDMA */
 147         printk("DMA_CAP ");
 148         outb(inb(dma_base+2)|(1<<(5+unit)), dma_base+2);
 149
 150         udma_ctrl = inb(dma_base + 3);
 151
 152         /* Put this channel into UDMA mode. */
 153         printk("UDMA_CTRL ");
 154         udma_ctrl |= (1 << unit);
 155
 156         /* Set UDMA2 usable timings. */
 157         if(bits & 0x04)
 158                 udma_timing_bits = 0x10;
 159         else if(bits & 0x02)
 160                 udma_timing_bits = 0x20;
 161         else
 162                 udma_timing_bits = 0x30;
 163         udma_ctrl &= ~(0x30 << (unit * 2));
 164         udma_ctrl |=  (udma_timing_bits << (unit * 2));
 165
 166         outb(udma_ctrl, dma_base+3);
 167         printk("DONE]\n");
 168 }
 169
 170 static int cmd646_dma_onoff(ide_drive_t *drive, int enable)
 171 {
 172         if(enable) {
 173                 ide_hwif_t *hwif = HWIF(drive);
 174                 unsigned long dma_base = hwif->dma_base;
 175                 struct hd_driveid *id = drive->id;
 176                 unsigned int class_rev;
 177
 178                 /* UltraDMA only supported on PCI646U and PCI646U2,
 179                  * which correspond to revisions 0x03 and 0x05 respectively.
 180                  * Actually, although the CMD tech support people won't
 181                  * tell me the details, the 0x03 revision cannot support
 182                  * UDMA correctly without hardware modifications, and even
 183                  * then it only works with Quantum disks due to some
 184                  * hold time assumptions in the 646U part which are fixed
 185                  * in the 646U2.
 186                  * So we only do UltraDMA on revision 0x05 chipsets.
 187                  */
 188                 pci_read_config_dword(hwif->pci_dev,
 189                                       PCI_CLASS_REVISION,
 190                                       &class_rev);
 191                 class_rev &= 0xff;
 192                 if((class_rev == 0x05) &&
 193                    (id->field_valid & 0x0004) &&
 194                    (id->dma_ultra & 0x07)) {
 195                         /* UltraDMA modes. */
 196                         cmd646_udma_enable(drive, dma_base);
 197                 } else {
 198                         /* Normal MultiWord DMA modes. */
 199                         cmd646_dma2_enable(drive, dma_base);
 200                 }
 201         }
 202         drive->using_dma = enable;
 203         return 0;
 204 }
 205
 206 static int cmd646_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
 207 {
 208         if(func == ide_dma_check)
 209                 return cmd646_config_drive_for_dma(drive);
 210         else if(func == ide_dma_on || func == ide_dma_off || func == ide_dma_off_quietly)
 211                 return cmd646_dma_onoff(drive, (func == ide_dma_on));
 212
 213         /* Other cases are done by generic IDE-DMA code. */
 214         return ide_dmaproc(func, drive);
 215 }
 216
 217 /*
 218  * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
 219  * event order for DMA transfers.
 220  */
 221 static int cmd646_1_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
 222 {
 223         ide_hwif_t *hwif = HWIF(drive);
 224         unsigned long dma_base = hwif->dma_base;
 225         byte dma_stat;
 226
 227         if (func == ide_dma_end) {
 228                 drive->waiting_for_dma = 0;
 229                 dma_stat = inb(dma_base+2);             /* get DMA status */
 230                 outb(inb(dma_base)&~1, dma_base);       /* stop DMA */
 231                 outb(dma_stat|6, dma_base+2);   /* clear the INTR & ERROR bits */
 232                 return (dma_stat & 7) != 4;     /* verify good DMA status */
 233         }
 234
 235         /* Other cases are done by generic IDE-DMA code. */
 236         return cmd646_dmaproc(func, drive);
 237 }
 238
 239 __initfunc(void ide_init_cmd646 (ide_hwif_t *hwif))
 240 {
 241         struct pci_dev *dev = hwif->pci_dev;
 242         unsigned char mrdmode;
 243         unsigned int class_rev;
 244
 245         pci_read_config_dword(hwif->pci_dev, PCI_CLASS_REVISION, &class_rev);
 246         class_rev &= 0xff;
 247
 248         hwif->chipset = ide_cmd646;
 249
 250         /* Set a good latency timer and cache line size value. */
 251         (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 252 #ifdef __sparc_v9__
 253         (void) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x10);
 254 #endif
 255
 256         /* Setup interrupts. */
 257         (void) pci_read_config_byte(dev, 0x71, &mrdmode);
 258         mrdmode &= ~(0x30);
 259         (void) pci_write_config_byte(dev, 0x71, mrdmode);
 260
 261         /* Use MEMORY READ LINE for reads.
 262          * NOTE: Although not mentioned in the PCI0646U specs,
 263          *       these bits are write only and won't be read
 264          *       back as set or not.  The PCI0646U2 specs clarify
 265          *       this point.
 266          */
 267         (void) pci_write_config_byte(dev, 0x71, mrdmode | 0x02);
 268
 269         /* Set reasonable active/recovery/address-setup values. */
 270         (void) pci_write_config_byte(dev, 0x53, 0x40);
 271         (void) pci_write_config_byte(dev, 0x54, 0x3f);
 272         (void) pci_write_config_byte(dev, 0x55, 0x40);
 273         (void) pci_write_config_byte(dev, 0x56, 0x3f);
 274         (void) pci_write_config_byte(dev, 0x57, 0x5c);
 275         (void) pci_write_config_byte(dev, 0x58, 0x3f);
 276         (void) pci_write_config_byte(dev, 0x5b, 0x3f);
 277
 278         if (hwif->dma_base) {
 279                 if (class_rev == 0x01) {
 280                         hwif->dmaproc = &cmd646_1_dmaproc;
 281                 } else {
 282                         hwif->dmaproc = &cmd646_dmaproc;
 283                 }
 284         }
 285 }