arch/mips/kernel/r4k_fpu.S

   1 /*
   2  * r4k_fpu.S: Save/restore floating point context for signal handlers.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1996, 1998 by Ralf Baechle
   9  *
  10  * Multi-arch abstraction and asm macros for easier reading:
  11  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
  12  *
  13  * $Id: r4k_fpu.S,v 1.5 1999/05/01 22:40:36 ralf Exp $
  14  */
  15 #include <asm/asm.h>
  16 #include <asm/fpregdef.h>
  17 #include <asm/mipsregs.h>
  18 #include <asm/offset.h>
  19 #include <asm/regdef.h>
  20
  21 #define EX(a,b)                                                 \
  22 9:      a,##b;                                                  \
  23         .section __ex_table,"a";                                \
  24         PTR     9b,bad_stack;                                   \
  25         .previous
  26
  27         .set    noreorder
  28         .set    mips3
  29         /* Save floating point context */
  30 LEAF(r4k_save_fp_context)
  31         mfc0    t1,CP0_STATUS
  32          sll    t2,t1,5
  33
  34         bgez    t2,1f
  35          cfc1   t1,fcr31
  36         /* Store the 16 odd double precision registers */
  37         EX(sdc1 $f1,(SC_FPREGS+8)(a0))
  38         EX(sdc1 $f3,(SC_FPREGS+24)(a0))
  39         EX(sdc1 $f5,(SC_FPREGS+40)(a0))
  40         EX(sdc1 $f7,(SC_FPREGS+56)(a0))
  41         EX(sdc1 $f9,(SC_FPREGS+72)(a0))
  42         EX(sdc1 $f11,(SC_FPREGS+88)(a0))
  43         EX(sdc1 $f13,(SC_FPREGS+104)(a0))
  44         EX(sdc1 $f15,(SC_FPREGS+120)(a0))
  45         EX(sdc1 $f17,(SC_FPREGS+136)(a0))
  46         EX(sdc1 $f19,(SC_FPREGS+152)(a0))
  47         EX(sdc1 $f21,(SC_FPREGS+168)(a0))
  48         EX(sdc1 $f23,(SC_FPREGS+184)(a0))
  49         EX(sdc1 $f25,(SC_FPREGS+200)(a0))
  50         EX(sdc1 $f27,(SC_FPREGS+216)(a0))
  51         EX(sdc1 $f29,(SC_FPREGS+232)(a0))
  52         EX(sdc1 $f31,(SC_FPREGS+248)(a0))
  53
  54         /* Store the 16 even double precision registers */
  55 1:
  56         EX(sdc1 $f0,(SC_FPREGS+0)(a0))
  57         EX(sdc1 $f2,(SC_FPREGS+16)(a0))
  58         EX(sdc1 $f4,(SC_FPREGS+32)(a0))
  59         EX(sdc1 $f6,(SC_FPREGS+48)(a0))
  60         EX(sdc1 $f8,(SC_FPREGS+64)(a0))
  61         EX(sdc1 $f10,(SC_FPREGS+80)(a0))
  62         EX(sdc1 $f12,(SC_FPREGS+96)(a0))
  63         EX(sdc1 $f14,(SC_FPREGS+112)(a0))
  64         EX(sdc1 $f16,(SC_FPREGS+128)(a0))
  65         EX(sdc1 $f18,(SC_FPREGS+144)(a0))
  66         EX(sdc1 $f20,(SC_FPREGS+160)(a0))
  67         EX(sdc1 $f22,(SC_FPREGS+176)(a0))
  68         EX(sdc1 $f24,(SC_FPREGS+192)(a0))
  69         EX(sdc1 $f26,(SC_FPREGS+208)(a0))
  70         EX(sdc1 $f28,(SC_FPREGS+224)(a0))
  71         EX(sdc1 $f30,(SC_FPREGS+240)(a0))
  72         EX(sw   t1,SC_FPC_CSR(a0))
  73         cfc1    t0,$0                           # implementation/version
  74
  75         jr      ra
  76         .set    nomacro
  77          EX(sw  t0,SC_FPC_EIR(a0))
  78         .set    macro
  79         END(r4k_save_fp_context)
  80
  81 /*
  82  * Restore FPU state:
  83  *  - fp gp registers
  84  *  - cp1 status/control register
  85  *
  86  * We base the decision which registers to restore from the signal stack
  87  * frame on the current content of c0_status, not on the content of the
  88  * stack frame which might have been changed by the user.
  89  */
  90 LEAF(r4k_restore_fp_context)
  91         mfc0    t1, CP0_STATUS
  92         sll     t0,t1,5
  93         bgez    t0,1f
  94          EX(lw  t0,SC_FPC_CSR(a0))
  95
  96         /* Restore the 16 odd double precision registers only
  97          * when enabled in the cp0 status register.
  98          */
  99         EX(ldc1 $f1,(SC_FPREGS+8)(a0))
 100         EX(ldc1 $f3,(SC_FPREGS+24)(a0))
 101         EX(ldc1 $f5,(SC_FPREGS+40)(a0))
 102         EX(ldc1 $f7,(SC_FPREGS+56)(a0))
 103         EX(ldc1 $f9,(SC_FPREGS+72)(a0))
 104         EX(ldc1 $f11,(SC_FPREGS+88)(a0))
 105         EX(ldc1 $f13,(SC_FPREGS+104)(a0))
 106         EX(ldc1 $f15,(SC_FPREGS+120)(a0))
 107         EX(ldc1 $f17,(SC_FPREGS+136)(a0))
 108         EX(ldc1 $f19,(SC_FPREGS+152)(a0))
 109         EX(ldc1 $f21,(SC_FPREGS+168)(a0))
 110         EX(ldc1 $f23,(SC_FPREGS+184)(a0))
 111         EX(ldc1 $f25,(SC_FPREGS+200)(a0))
 112         EX(ldc1 $f27,(SC_FPREGS+216)(a0))
 113         EX(ldc1 $f29,(SC_FPREGS+232)(a0))
 114         EX(ldc1 $f31,(SC_FPREGS+248)(a0))
 115
 116         /*
 117          * Restore the 16 even double precision registers
 118          * when cp1 was enabled in the cp0 status register.
 119          */
 120 1:      EX(ldc1 $f0,(SC_FPREGS+0)(a0))
 121         EX(ldc1 $f2,(SC_FPREGS+16)(a0))
 122         EX(ldc1 $f4,(SC_FPREGS+32)(a0))
 123         EX(ldc1 $f6,(SC_FPREGS+48)(a0))
 124         EX(ldc1 $f8,(SC_FPREGS+64)(a0))
 125         EX(ldc1 $f10,(SC_FPREGS+80)(a0))
 126         EX(ldc1 $f12,(SC_FPREGS+96)(a0))
 127         EX(ldc1 $f14,(SC_FPREGS+112)(a0))
 128         EX(ldc1 $f16,(SC_FPREGS+128)(a0))
 129         EX(ldc1 $f18,(SC_FPREGS+144)(a0))
 130         EX(ldc1 $f20,(SC_FPREGS+160)(a0))
 131         EX(ldc1 $f22,(SC_FPREGS+176)(a0))
 132         EX(ldc1 $f24,(SC_FPREGS+192)(a0))
 133         EX(ldc1 $f26,(SC_FPREGS+208)(a0))
 134         EX(ldc1 $f28,(SC_FPREGS+224)(a0))
 135         EX(ldc1 $f30,(SC_FPREGS+240)(a0))
 136         jr      ra
 137          ctc1   t0,fcr31
 138         END(r4k_restore_fp_context)