arch/mips/dec/setup.c

   1 /*
   2  * Setup the interrupt stuff.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1998 Harald Koerfgen
   9  */
  10 #include <linux/sched.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/mc146818rtc.h>
  13 #include <linux/param.h>
  14 #include <asm/mipsregs.h>
  15 #include <asm/bootinfo.h>
  16 #include <asm/init.h>
  17 #include <asm/irq.h>
  18 #include <asm/reboot.h>
  19
  20 #include <asm/dec/interrupts.h>
  21 #include <asm/dec/kn01.h>
  22 #include <asm/dec/kn02.h>
  23 #include <asm/dec/kn02xa.h>
  24 #include <asm/dec/kn03.h>
  25 #include <asm/dec/ioasic_ints.h>
  26
  27 extern asmlinkage void decstation_handle_int(void);
  28
  29 void dec_init_kn01(void);
  30 void dec_init_kn230(void);
  31 void dec_init_kn02(void);
  32 void dec_init_kn02ba(void);
  33 void dec_init_kn02ca(void);
  34 void dec_init_kn03(void);
  35
  36 char *dec_rtc_base = (char *) KN01_RTC_BASE;    /* Assume DS2100/3100 initially */
  37
  38 decint_t dec_interrupt[NR_INTS];
  39
  40 /*
  41  * Information regarding the IRQ Controller
  42  *
  43  * isr and imr are also hardcoded for different machines in int_handler.S
  44  */
  45
  46 volatile unsigned int *isr = 0L;        /* address of the interrupt status register     */
  47 volatile unsigned int *imr = 0L;        /* address of the interrupt mask register       */
  48
  49 extern void dec_machine_restart(char *command);
  50 extern void dec_machine_halt(void);
  51 extern void dec_machine_power_off(void);
  52
  53 extern void wbflush_setup(void);
  54
  55 extern struct rtc_ops dec_rtc_ops;
  56
  57 extern void intr_halt(void);
  58
  59 extern int setup_dec_irq(int, struct irqaction *);
  60
  61 void (*board_time_init) (struct irqaction * irq);
  62
  63 __initfunc(static void dec_irq_setup(void))
  64 {
  65     switch (mips_machtype) {
  66     case MACH_DS23100:
  67         dec_init_kn01();
  68         break;
  69     case MACH_DS5100:           /*  DS5100 MIPSMATE */
  70         dec_init_kn230();
  71         break;
  72     case MACH_DS5000_200:       /* DS5000 3max */
  73         dec_init_kn02();
  74         break;
  75     case MACH_DS5000_1XX:       /* DS5000/100 3min */
  76         dec_init_kn02ba();
  77         break;
  78     case MACH_DS5000_2X0:       /* DS5000/240 3max+ */
  79         dec_init_kn03();
  80         break;
  81     case MACH_DS5000_XX:        /* Personal DS5000/2x */
  82         dec_init_kn02ca();
  83         break;
  84     case MACH_DS5800:           /* DS5800 Isis */
  85         panic("Don't know how to set this up!");
  86         break;
  87     case MACH_DS5400:           /* DS5400 MIPSfair */
  88         panic("Don't know how to set this up!");
  89         break;
  90     case MACH_DS5500:           /* DS5500 MIPSfair-2 */
  91         panic("Don't know how to set this up!");
  92         break;
  93     }
  94     set_except_vector(0, decstation_handle_int);
  95 }
  96
  97 /*
  98  * enable the periodic interrupts
  99  */
 100 __initfunc(static void dec_time_init(struct irqaction *irq))
 101 {
 102     /*
 103      * Here we go, enable periodic rtc interrupts.
 104      */
 105
 106 #ifndef LOG_2_HZ
 107 #  define LOG_2_HZ 7
 108 #endif
 109
 110     CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - LOG_2_HZ), RTC_REG_A);
 111     CMOS_WRITE(CMOS_READ(RTC_REG_B) | RTC_PIE, RTC_REG_B);
 112     setup_dec_irq(CLOCK, irq);
 113 }
 114
 115 __initfunc(void decstation_setup(void))
 116 {
 117     irq_setup = dec_irq_setup;
 118     board_time_init = dec_time_init;
 119
 120     wbflush_setup();
 121
 122     _machine_restart = dec_machine_restart;
 123     _machine_halt = dec_machine_halt;
 124     _machine_power_off = dec_machine_power_off;
 125
 126     rtc_ops = &dec_rtc_ops;
 127 }
 128
 129 /*
 130  * Machine-specific initialisation for kn01, aka Pmax, aka DS2100, DS3100,
 131  * and possibly also the DS5100.
 132  */
 133 __initfunc(void dec_init_kn01(void))
 134 {
 135     /*
 136      * Setup some memory addresses.
 137      */
 138     dec_rtc_base = (char *) KN01_RTC_BASE;
 139
 140     /*
 141      * Setup interrupt structure
 142      */
 143     dec_interrupt[CLOCK].cpu_mask = IE_IRQ3;
 144     dec_interrupt[CLOCK].iemask = 0;
 145     cpu_mask_tbl[0] = IE_IRQ3;
 146     cpu_irq_nr[0] = CLOCK;
 147
 148     dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0;
 149     dec_interrupt[SCSI_INT].iemask = 0;
 150     cpu_mask_tbl[1] = IE_IRQ0;
 151     cpu_irq_nr[1] = SCSI_INT;
 152
 153     dec_interrupt[ETHER].cpu_mask = IE_IRQ1;
 154     dec_interrupt[ETHER].iemask = 0;
 155     cpu_mask_tbl[2] = IE_IRQ1;
 156     cpu_irq_nr[2] = ETHER;
 157
 158     dec_interrupt[SERIAL].cpu_mask = IE_IRQ2;
 159     dec_interrupt[SERIAL].iemask = 0;
 160     cpu_mask_tbl[3] = IE_IRQ2;
 161     cpu_irq_nr[3] = SERIAL;
 162
 163     dec_interrupt[MEMORY].cpu_mask = IE_IRQ4;
 164     dec_interrupt[MEMORY].iemask = 0;
 165     cpu_mask_tbl[4] = IE_IRQ4;
 166     cpu_irq_nr[4] = MEMORY;
 167
 168     dec_interrupt[FPU].cpu_mask = IE_IRQ5;
 169     dec_interrupt[FPU].iemask = 0;
 170     cpu_mask_tbl[5] = IE_IRQ5;
 171     cpu_irq_nr[5] = FPU;
 172 }                               /* dec_init_kn01 */
 173
 174 /*
 175  * Machine-specific initialisation for kn230, aka MIPSmate, aka DS5100
 176  *
 177  * There are a lot of experiments to do, this is definitely incomplete.
 178  */
 179 __initfunc(void dec_init_kn230(void))
 180 {
 181     /*
 182      * Setup some memory addresses.
 183      */
 184     dec_rtc_base = (char *) KN01_RTC_BASE;
 185
 186     /*
 187      * Setup interrupt structure
 188      */
 189     dec_interrupt[CLOCK].cpu_mask = IE_IRQ2;
 190     dec_interrupt[CLOCK].iemask = 0;
 191     cpu_mask_tbl[0] = IE_IRQ2;
 192     cpu_irq_nr[0] = CLOCK;
 193
 194     dec_interrupt[FPU].cpu_mask = IE_IRQ5;
 195     dec_interrupt[FPU].iemask = 0;
 196     cpu_mask_tbl[5] = IE_IRQ5;
 197     cpu_irq_nr[5] = FPU;
 198 }                               /* dec_init_kn230 */
 199
 200 /*
 201  * Machine-specific initialisation for kn02, aka 3max, aka DS5000/2xx.
 202  */
 203 __initfunc(void dec_init_kn02(void))
 204 {
 205     /*
 206      * Setup some memory addresses. FIXME: probably incomplete!
 207      */
 208     dec_rtc_base = (char *) KN02_RTC_BASE;
 209     isr = (volatile unsigned int *) KN02_CSR_ADDR;
 210     imr = (volatile unsigned int *) KN02_CSR_ADDR;
 211
 212     /*
 213      * Setup IOASIC interrupt
 214      */
 215     cpu_ivec_tbl[1] = kn02_io_int;
 216     cpu_mask_tbl[1] = IE_IRQ0;
 217     cpu_irq_nr[1] = -1;
 218     *imr = *imr & 0xff00ff00;
 219
 220     /*
 221      * Setup interrupt structure
 222      */
 223     dec_interrupt[CLOCK].cpu_mask = IE_IRQ1;
 224     dec_interrupt[CLOCK].iemask = 0;
 225     cpu_mask_tbl[0] = IE_IRQ1;
 226     cpu_irq_nr[0] = CLOCK;
 227
 228     dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0;
 229     dec_interrupt[SCSI_INT].iemask = KN02_SLOT5;
 230     asic_mask_tbl[0] = KN02_SLOT5;
 231     asic_irq_nr[0] = SCSI_INT;
 232
 233     dec_interrupt[ETHER].cpu_mask = IE_IRQ0;
 234     dec_interrupt[ETHER].iemask = KN02_SLOT6;
 235     asic_mask_tbl[1] = KN02_SLOT6;
 236     asic_irq_nr[1] = ETHER;
 237
 238     dec_interrupt[SERIAL].cpu_mask = IE_IRQ0;
 239     dec_interrupt[SERIAL].iemask = KN02_SLOT7;
 240     asic_mask_tbl[2] = KN02_SLOT7;
 241     asic_irq_nr[2] = SERIAL;
 242
 243     dec_interrupt[TC0].cpu_mask = IE_IRQ0;
 244     dec_interrupt[TC0].iemask = KN02_SLOT0;
 245     asic_mask_tbl[3] = KN02_SLOT0;
 246     asic_irq_nr[3] = TC0;
 247
 248     dec_interrupt[TC1].cpu_mask = IE_IRQ0;
 249     dec_interrupt[TC1].iemask = KN02_SLOT1;
 250     asic_mask_tbl[4] = KN02_SLOT1;
 251     asic_irq_nr[4] = TC1;
 252
 253     dec_interrupt[TC2].cpu_mask = IE_IRQ0;
 254     dec_interrupt[TC2].iemask = KN02_SLOT2;
 255     asic_mask_tbl[5] = KN02_SLOT2;
 256     asic_irq_nr[5] = TC2;
 257
 258     dec_interrupt[MEMORY].cpu_mask = IE_IRQ3;
 259     dec_interrupt[MEMORY].iemask = 0;
 260     cpu_mask_tbl[2] = IE_IRQ3;
 261     cpu_irq_nr[2] = MEMORY;
 262
 263     dec_interrupt[FPU].cpu_mask = IE_IRQ5;
 264     dec_interrupt[FPU].iemask = 0;
 265     cpu_mask_tbl[3] = IE_IRQ5;
 266     cpu_irq_nr[3] = FPU;
 267
 268 }                               /* dec_init_kn02 */
 269
 270 /*
 271  * Machine-specific initialisation for kn02ba, aka 3min, aka DS5000/1xx.
 272  */
 273 __initfunc(void dec_init_kn02ba(void))
 274 {
 275     /*
 276      * Setup some memory addresses.
 277      */
 278     dec_rtc_base = (char *) KN02XA_RTC_BASE;
 279     isr = (volatile unsigned int *) KN02XA_SIR_ADDR;
 280     imr = (volatile unsigned int *) KN02XA_SIRM_ADDR;
 281
 282     /*
 283      * Setup IOASIC interrupt
 284      */
 285     cpu_mask_tbl[0] = IE_IRQ3;
 286     cpu_irq_nr[0] = -1;
 287     cpu_ivec_tbl[0] = kn02ba_io_int;
 288     *imr = 0;
 289
 290     /*
 291      * Setup interrupt structure
 292      */
 293     dec_interrupt[CLOCK].cpu_mask = IE_IRQ3;
 294     dec_interrupt[CLOCK].iemask = KMIN_CLOCK;
 295     asic_mask_tbl[0] = KMIN_CLOCK;
 296     asic_irq_nr[0] = CLOCK;
 297
 298     dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ3;
 299     dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS;
 300     asic_mask_tbl[1] = SCSI_DMA_INTS;
 301     asic_irq_nr[1] = SCSI_DMA_INT;
 302
 303     dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ3;
 304     dec_interrupt[SCSI_INT].iemask = SCSI_CHIP;
 305     asic_mask_tbl[2] = SCSI_CHIP;
 306     asic_irq_nr[2] = SCSI_INT;
 307
 308     dec_interrupt[ETHER].cpu_mask = IE_IRQ3;
 309     dec_interrupt[ETHER].iemask = LANCE_INTS;
 310     asic_mask_tbl[3] = LANCE_INTS;
 311     asic_irq_nr[3] = ETHER;
 312
 313     dec_interrupt[SERIAL].cpu_mask = IE_IRQ3;
 314     dec_interrupt[SERIAL].iemask = SERIAL_INTS;
 315     asic_mask_tbl[4] = SERIAL_INTS;
 316     asic_irq_nr[4] = SERIAL;
 317
 318     dec_interrupt[MEMORY].cpu_mask = IE_IRQ3;
 319     dec_interrupt[MEMORY].iemask = KMIN_TIMEOUT;
 320     asic_mask_tbl[5] = KMIN_TIMEOUT;
 321     asic_irq_nr[5] = MEMORY;
 322
 323     dec_interrupt[TC0].cpu_mask = IE_IRQ0;
 324     dec_interrupt[TC0].iemask = 0;
 325     cpu_mask_tbl[1] = IE_IRQ0;
 326     cpu_irq_nr[1] = TC0;
 327
 328     dec_interrupt[TC1].cpu_mask = IE_IRQ1;
 329     dec_interrupt[TC1].iemask = 0;
 330     cpu_mask_tbl[2] = IE_IRQ1;
 331     cpu_irq_nr[2] = TC1;
 332
 333     dec_interrupt[TC2].cpu_mask = IE_IRQ2;
 334     dec_interrupt[TC2].iemask = 0;
 335     cpu_mask_tbl[3] = IE_IRQ2;
 336     cpu_irq_nr[3] = TC2;
 337
 338     dec_interrupt[HALT].cpu_mask = IE_IRQ4;
 339     dec_interrupt[HALT].iemask = 0;
 340     cpu_mask_tbl[4] = IE_IRQ4;
 341     cpu_irq_nr[4] = HALT;
 342
 343     dec_interrupt[FPU].cpu_mask = IE_IRQ5;
 344     dec_interrupt[FPU].iemask = 0;
 345     cpu_mask_tbl[5] = IE_IRQ5;
 346     cpu_irq_nr[5] = FPU;
 347
 348 }                               /* dec_init_kn02ba */
 349
 350 /*
 351  * Machine-specific initialisation for kn02ca, aka maxine, aka DS5000/2x.
 352  */
 353 __initfunc(void dec_init_kn02ca(void))
 354 {
 355     /*
 356      * Setup some memory addresses. FIXME: probably incomplete!
 357      */
 358     dec_rtc_base = (char *) KN02XA_RTC_BASE;
 359     isr = (volatile unsigned int *) KN02XA_SIR_ADDR;
 360     imr = (volatile unsigned int *) KN02XA_SIRM_ADDR;
 361
 362     /*
 363      * Setup IOASIC interrupt
 364      */
 365     cpu_ivec_tbl[1] = kn02ba_io_int;
 366     cpu_irq_nr[1] = -1;
 367     cpu_mask_tbl[1] = IE_IRQ3;
 368     *imr = 0;
 369
 370     /*
 371      * Setup interrupt structure
 372      */
 373     dec_interrupt[CLOCK].cpu_mask = IE_IRQ1;
 374     dec_interrupt[CLOCK].iemask = 0;
 375     cpu_mask_tbl[0] = IE_IRQ1;
 376     cpu_irq_nr[0] = CLOCK;
 377
 378     dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ3;
 379     dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS;
 380     asic_mask_tbl[0] = SCSI_DMA_INTS;
 381     asic_irq_nr[0] = SCSI_DMA_INT;
 382
 383     dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ3;
 384     dec_interrupt[SCSI_INT].iemask = SCSI_CHIP;
 385     asic_mask_tbl[1] = SCSI_CHIP;
 386     asic_irq_nr[1] = SCSI_INT;
 387
 388     dec_interrupt[ETHER].cpu_mask = IE_IRQ3;
 389     dec_interrupt[ETHER].iemask = LANCE_INTS;
 390     asic_mask_tbl[2] = LANCE_INTS;
 391     asic_irq_nr[2] = ETHER;
 392
 393     dec_interrupt[SERIAL].cpu_mask = IE_IRQ3;
 394     dec_interrupt[SERIAL].iemask = XINE_SERIAL_INTS;
 395     asic_mask_tbl[3] = XINE_SERIAL_INTS;
 396     asic_irq_nr[3] = SERIAL;
 397
 398     dec_interrupt[TC0].cpu_mask = IE_IRQ3;
 399     dec_interrupt[TC0].iemask = MAXINE_TC0;
 400     asic_mask_tbl[4] = MAXINE_TC0;
 401     asic_irq_nr[4] = TC0;
 402
 403     dec_interrupt[TC1].cpu_mask = IE_IRQ3;
 404     dec_interrupt[TC1].iemask = MAXINE_TC1;
 405     asic_mask_tbl[5] = MAXINE_TC1;
 406     asic_irq_nr[5] = TC1;
 407
 408     dec_interrupt[MEMORY].cpu_mask = IE_IRQ2;
 409     dec_interrupt[MEMORY].iemask = 0;
 410     cpu_mask_tbl[2] = IE_IRQ2;
 411     cpu_irq_nr[2] = MEMORY;
 412
 413     dec_interrupt[HALT].cpu_mask = IE_IRQ4;
 414     dec_interrupt[HALT].iemask = 0;
 415     cpu_mask_tbl[3] = IE_IRQ4;
 416     cpu_irq_nr[3] = HALT;
 417
 418     dec_interrupt[FPU].cpu_mask = IE_IRQ5;
 419     dec_interrupt[FPU].iemask = 0;
 420     cpu_mask_tbl[4] = IE_IRQ5;
 421     cpu_irq_nr[4] = FPU;
 422
 423 }                               /* dec_init_kn02ca */
 424
 425 /*
 426  * Machine-specific initialisation for kn03, aka 3max+, aka DS5000/240.
 427  */
 428 __initfunc(void dec_init_kn03(void))
 429 {
 430     /*
 431      * Setup some memory addresses. FIXME: probably incomplete!
 432      */
 433     dec_rtc_base = (char *) KN03_RTC_BASE;
 434     isr = (volatile unsigned int *) KN03_SIR_ADDR;
 435     imr = (volatile unsigned int *) KN03_SIRM_ADDR;
 436
 437     /*
 438      * Setup IOASIC interrupt
 439      */
 440     cpu_ivec_tbl[1] = kn03_io_int;
 441     cpu_mask_tbl[1] = IE_IRQ0;
 442     cpu_irq_nr[1] = -1;
 443     *imr = 0;
 444
 445     /*
 446      * Setup interrupt structure
 447      */
 448     dec_interrupt[CLOCK].cpu_mask = IE_IRQ1;
 449     dec_interrupt[CLOCK].iemask = 0;
 450     cpu_mask_tbl[0] = IE_IRQ1;
 451     cpu_irq_nr[0] = CLOCK;
 452
 453     dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ0;
 454     dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS;
 455     asic_mask_tbl[0] = SCSI_DMA_INTS;
 456     asic_irq_nr[0] = SCSI_DMA_INT;
 457
 458     dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0;
 459     dec_interrupt[SCSI_INT].iemask = SCSI_CHIP;
 460     asic_mask_tbl[1] = SCSI_CHIP;
 461     asic_irq_nr[1] = SCSI_INT;
 462
 463     dec_interrupt[ETHER].cpu_mask = IE_IRQ0;
 464     dec_interrupt[ETHER].iemask = LANCE_INTS;
 465     asic_mask_tbl[2] = LANCE_INTS;
 466     asic_irq_nr[2] = ETHER;
 467
 468     dec_interrupt[SERIAL].cpu_mask = IE_IRQ0;
 469     dec_interrupt[SERIAL].iemask = SERIAL_INTS;
 470     asic_mask_tbl[3] = SERIAL_INTS;
 471     asic_irq_nr[3] = SERIAL;
 472
 473     dec_interrupt[TC0].cpu_mask = IE_IRQ0;
 474     dec_interrupt[TC0].iemask = KN03_TC0;
 475     asic_mask_tbl[4] = KN03_TC0;
 476     asic_irq_nr[4] = TC0;
 477
 478     dec_interrupt[TC1].cpu_mask = IE_IRQ0;
 479     dec_interrupt[TC1].iemask = KN03_TC1;
 480     asic_mask_tbl[5] = KN03_TC1;
 481     asic_irq_nr[5] = TC1;
 482
 483     dec_interrupt[TC2].cpu_mask = IE_IRQ0;
 484     dec_interrupt[TC2].iemask = KN03_TC2;
 485     asic_mask_tbl[6] = KN03_TC2;
 486     asic_irq_nr[6] = TC2;
 487
 488     dec_interrupt[MEMORY].cpu_mask = IE_IRQ3;
 489     dec_interrupt[MEMORY].iemask = 0;
 490     cpu_mask_tbl[2] = IE_IRQ3;
 491     cpu_irq_nr[2] = MEMORY;
 492
 493     dec_interrupt[HALT].cpu_mask = IE_IRQ4;
 494     dec_interrupt[HALT].iemask = 0;
 495     cpu_mask_tbl[3] = IE_IRQ4;
 496     cpu_irq_nr[3] = HALT;
 497
 498     dec_interrupt[FPU].cpu_mask = IE_IRQ5;
 499     dec_interrupt[FPU].iemask = 0;
 500     cpu_mask_tbl[4] = IE_IRQ5;
 501     cpu_irq_nr[4] = FPU;
 502
 503 }                               /* dec_init_kn03 */