include/linux/openpic.h

   1 /*
   2  *  linux/openpic.h -- OpenPIC definitions
   3  *
   4  *  Copyright (C) 1997 Geert Uytterhoeven
   5  *
   6  *  This file is based on the following documentation:
   7  *
   8  *      The Open Programmable Interrupt Controller (PIC)
   9  *      Register Interface Specification Revision 1.2
  10  *
  11  *      Issue Date: October 1995
  12  *
  13  *      Issued jointly by Advanced Micro Devices and Cyrix Corporation
  14  *
  15  *      AMD is a registered trademark of Advanced Micro Devices, Inc.
  16  *      Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc.
  17  *      All Rights Reserved.
  18  *
  19  *  To receive a copy of this documentation, send an email to openpic@amd.com.
  20  *
  21  *  This file is subject to the terms and conditions of the GNU General Public
  22  *  License.  See the file COPYING in the main directory of this archive
  23  *  for more details.
  24  */
  25
  26 #ifndef _LINUX_OPENPIC_H
  27 #define _LINUX_OPENPIC_H
  28
  29 #if !defined(__powerpc__) && !defined(__i386__)
  30 #error Unsupported OpenPIC platform
  31 #endif
  32
  33
  34 #ifdef __KERNEL__
  35
  36     /*
  37      *  OpenPIC supports up to 2048 interrupt sources and up to 32 processors
  38      */
  39
  40 #define OPENPIC_MAX_SOURCES     2048
  41 #define OPENPIC_MAX_PROCESSORS  32
  42
  43 #define OPENPIC_NUM_TIMERS      4
  44 #define OPENPIC_NUM_IPI         4
  45 #define OPENPIC_NUM_PRI         16
  46 #define OPENPIC_NUM_VECTORS     256
  47
  48
  49     /*
  50      *  Vector numbers
  51      */
  52
  53 #define OPENPIC_VEC_SOURCE      16    /* and up */
  54 #define OPENPIC_VEC_TIMER       64    /* and up */
  55 #define OPENPIC_VEC_IPI         72    /* and up */
  56 #define OPENPIC_VEC_SPURIOUS    127
  57
  58
  59     /*
  60      *  OpenPIC Registers are 32 bits and aligned on 128 bit boundaries
  61      */
  62
  63 typedef struct _OpenPIC_Reg {
  64     u_int Reg;                                  /* Little endian! */
  65     char Pad[0xc];
  66 } OpenPIC_Reg;
  67
  68
  69     /*
  70      *  Per Processor Registers
  71      */
  72
  73 typedef struct _OpenPIC_Processor {
  74     /*
  75      *  Private Shadow Registers (for SLiC backwards compatibility)
  76      */
  77     u_int IPI0_Dispatch_Shadow;                 /* Write Only */
  78     char Pad1[0x4];
  79     u_int IPI0_Vector_Priority_Shadow;          /* Read/Write */
  80     char Pad2[0x34];
  81     /*
  82      *  Interprocessor Interrupt Command Ports
  83      */
  84     OpenPIC_Reg _IPI_Dispatch[OPENPIC_NUM_IPI]; /* Write Only */
  85     /*
  86      *  Current Task Priority Register
  87      */
  88     OpenPIC_Reg _Current_Task_Priority;         /* Read/Write */
  89 #ifndef __powerpc__
  90     /*
  91      *  Who Am I Register
  92      */
  93     OpenPIC_Reg _Who_Am_I;                      /* Read Only */
  94 #else
  95     char Pad3[0x10];
  96 #endif
  97 #ifndef __i386__
  98     /*
  99      *  Interrupt Acknowledge Register
 100      */
 101     OpenPIC_Reg _Interrupt_Acknowledge;         /* Read Only */
 102 #else
 103     char Pad4[0x10];
 104 #endif
 105     /*
 106      *  End of Interrupt (EOI) Register
 107      */
 108     OpenPIC_Reg _EOI;                           /* Read/Write */
 109     char Pad5[0xf40];
 110 } OpenPIC_Processor;
 111
 112
 113     /*
 114      *  Timer Registers
 115      */
 116
 117 typedef struct _OpenPIC_Timer {
 118     OpenPIC_Reg _Current_Count;                 /* Read Only */
 119     OpenPIC_Reg _Base_Count;                    /* Read/Write */
 120     OpenPIC_Reg _Vector_Priority;               /* Read/Write */
 121     OpenPIC_Reg _Destination;                   /* Read/Write */
 122 } OpenPIC_Timer;
 123
 124
 125     /*
 126      *  Global Registers
 127      */
 128
 129 typedef struct _OpenPIC_Global {
 130     /*
 131      *  Feature Reporting Registers
 132      */
 133     OpenPIC_Reg _Feature_Reporting0;            /* Read Only */
 134     OpenPIC_Reg _Feature_Reporting1;            /* Future Expansion */
 135     /*
 136      *  Global Configuration Registers
 137      */
 138     OpenPIC_Reg _Global_Configuration0;         /* Read/Write */
 139     OpenPIC_Reg _Global_Configuration1;         /* Future Expansion */
 140     /*
 141      *  Vendor Specific Registers
 142      */
 143     OpenPIC_Reg _Vendor_Specific[4];
 144     /*
 145      *  Vendor Identification Register
 146      */
 147     OpenPIC_Reg _Vendor_Identification;         /* Read Only */
 148     /*
 149      *  Processor Initialization Register
 150      */
 151     OpenPIC_Reg _Processor_Initialization;      /* Read/Write */
 152     /*
 153      *  IPI Vector/Priority Registers
 154      */
 155     OpenPIC_Reg _IPI_Vector_Priority[OPENPIC_NUM_IPI];  /* Read/Write */
 156     /*
 157      *  Spurious Vector Register
 158      */
 159     OpenPIC_Reg _Spurious_Vector;               /* Read/Write */
 160     /*
 161      *  Global Timer Registers
 162      */
 163     OpenPIC_Reg _Timer_Frequency;               /* Read/Write */
 164     OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS];
 165     char Pad1[0xee00];
 166 } OpenPIC_Global;
 167
 168
 169     /*
 170      *  Interrupt Source Registers
 171      */
 172
 173 typedef struct _OpenPIC_Source {
 174     OpenPIC_Reg _Vector_Priority;               /* Read/Write */
 175     OpenPIC_Reg _Destination;                   /* Read/Write */
 176 } OpenPIC_Source;
 177
 178
 179     /*
 180      *  OpenPIC Register Map
 181      */
 182
 183 struct OpenPIC {
 184 #ifndef __powerpc__
 185     /*
 186      *  Per Processor Registers --- Private Access
 187      */
 188     OpenPIC_Processor Private;
 189 #else
 190     char Pad1[0x1000];
 191 #endif
 192     /*
 193      *  Global Registers
 194      */
 195     OpenPIC_Global Global;
 196     /*
 197      *  Interrupt Source Configuration Registers
 198      */
 199     OpenPIC_Source Source[OPENPIC_MAX_SOURCES];
 200     /*
 201      *  Per Processor Registers
 202      */
 203     OpenPIC_Processor Processor[OPENPIC_MAX_PROCESSORS];
 204 };
 205
 206 extern volatile struct OpenPIC *OpenPIC;
 207 extern u_int OpenPIC_NumInitSenses;
 208 extern u_char *OpenPIC_InitSenses;
 209
 210
 211     /*
 212      *  Current Task Priority Register
 213      */
 214
 215 #define OPENPIC_CURRENT_TASK_PRIORITY_MASK      0x0000000f
 216
 217     /*
 218      *  Who Am I Register
 219      */
 220
 221 #define OPENPIC_WHO_AM_I_ID_MASK                0x0000001f
 222
 223     /*
 224      *  Feature Reporting Register 0
 225      */
 226
 227 #define OPENPIC_FEATURE_LAST_SOURCE_MASK        0x07ff0000
 228 #define OPENPIC_FEATURE_LAST_SOURCE_SHIFT       16
 229 #define OPENPIC_FEATURE_LAST_PROCESSOR_MASK     0x00001f00
 230 #define OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT    8
 231 #define OPENPIC_FEATURE_VERSION_MASK            0x000000ff
 232
 233     /*
 234      *  Global Configuration Register 0
 235      */
 236
 237 #define OPENPIC_CONFIG_RESET                    0x80000000
 238 #define OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE 0x20000000
 239 #define OPENPIC_CONFIG_BASE_MASK                0x000fffff
 240
 241     /*
 242      *  Vendor Identification Register
 243      */
 244
 245 #define OPENPIC_VENDOR_ID_STEPPING_MASK         0x00ff0000
 246 #define OPENPIC_VENDOR_ID_STEPPING_SHIFT        16
 247 #define OPENPIC_VENDOR_ID_DEVICE_ID_MASK        0x0000ff00
 248 #define OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT       8
 249 #define OPENPIC_VENDOR_ID_VENDOR_ID_MASK        0x000000ff
 250
 251     /*
 252      *  Vector/Priority Registers
 253      */
 254
 255 #define OPENPIC_MASK                            0x80000000
 256 #define OPENPIC_ACTIVITY                        0x40000000      /* Read Only */
 257 #define OPENPIC_PRIORITY_MASK                   0x000f0000
 258 #define OPENPIC_PRIORITY_SHIFT                  16
 259 #define OPENPIC_VECTOR_MASK                     0x000000ff
 260
 261
 262     /*
 263      *  Interrupt Source Registers
 264      */
 265
 266 #define OPENPIC_POLARITY_POSITIVE               0x00800000
 267 #define OPENPIC_POLARITY_NEGATIVE               0x00000000
 268 #define OPENPIC_POLARITY_MASK                   0x00800000
 269 #define OPENPIC_SENSE_LEVEL                     0x00400000
 270 #define OPENPIC_SENSE_EDGE                      0x00000000
 271 #define OPENPIC_SENSE_MASK                      0x00400000
 272
 273
 274     /*
 275      *  Timer Registers
 276      */
 277
 278 #define OPENPIC_COUNT_MASK                      0x7fffffff
 279 #define OPENPIC_TIMER_TOGGLE                    0x80000000
 280 #define OPENPIC_TIMER_COUNT_INHIBIT             0x80000000
 281
 282
 283     /*
 284      *  Aliases to make life simpler
 285      */
 286
 287 /* Per Processor Registers */
 288 #define IPI_Dispatch(i)                 _IPI_Dispatch[i].Reg
 289 #define Current_Task_Priority           _Current_Task_Priority.Reg
 290 #ifndef __powerpc__
 291 #define Who_Am_I                        _Who_Am_I.Reg
 292 #endif
 293 #ifndef __i386__
 294 #define Interrupt_Acknowledge           _Interrupt_Acknowledge.Reg
 295 #endif
 296 #define EOI                             _EOI.Reg
 297
 298 /* Global Registers */
 299 #define Feature_Reporting0              _Feature_Reporting0.Reg
 300 #define Feature_Reporting1              _Feature_Reporting1.Reg
 301 #define Global_Configuration0           _Global_Configuration0.Reg
 302 #define Global_Configuration1           _Global_Configuration1.Reg
 303 #define Vendor_Specific(i)              _Vendor_Specific[i].Reg
 304 #define Vendor_Identification           _Vendor_Identification.Reg
 305 #define Processor_Initialization        _Processor_Initialization.Reg
 306 #define IPI_Vector_Priority(i)          _IPI_Vector_Priority[i].Reg
 307 #define Spurious_Vector                 _Spurious_Vector.Reg
 308 #define Timer_Frequency                 _Timer_Frequency.Reg
 309
 310 /* Timer Registers */
 311 #define Current_Count                   _Current_Count.Reg
 312 #define Base_Count                      _Base_Count.Reg
 313 #define Vector_Priority                 _Vector_Priority.Reg
 314 #define Destination                     _Destination.Reg
 315
 316 /* Interrupt Source Registers */
 317 #define Vector_Priority                 _Vector_Priority.Reg
 318 #define Destination                     _Destination.Reg
 319
 320     /*
 321      *  OpenPIC Operations
 322      */
 323
 324 /* Global Operations */
 325 extern void openpic_init(int);
 326 extern void openpic_reset(void);
 327 extern void openpic_enable_8259_pass_through(void);
 328 extern void openpic_disable_8259_pass_through(void);
 329 #ifndef __i386__
 330 extern u_int openpic_irq(u_int cpu);
 331 #endif
 332 #ifndef __powerpc__
 333 extern void openpic_eoi(void);
 334 extern u_int openpic_get_priority(void);
 335 extern void openpic_set_priority(u_int pri);
 336 #else
 337 extern void openpic_eoi(u_int cpu);
 338 extern u_int openpic_get_priority(u_int cpu);
 339 extern void openpic_set_priority(u_int cpu, u_int pri);
 340 #endif
 341 extern u_int openpic_get_spurious(void);
 342 extern void openpic_set_spurious(u_int vector);
 343 extern void openpic_init_processor(u_int cpumask);
 344
 345 /* Interprocessor Interrupts */
 346 extern void openpic_initipi(u_int ipi, u_int pri, u_int vector);
 347 #ifndef __powerpc__
 348 extern void openpic_cause_IPI(u_int ipi, u_int cpumask);
 349 #else
 350 extern void openpic_cause_IPI(u_int cpu, u_int ipi, u_int cpumask);
 351 #endif
 352
 353 /* Timer Interrupts */
 354 extern void openpic_inittimer(u_int timer, u_int pri, u_int vector);
 355 extern void openpic_maptimer(u_int timer, u_int cpumask);
 356
 357 /* Interrupt Sources */
 358 extern void openpic_enable_irq(u_int irq);
 359 extern void openpic_disable_irq(u_int irq);
 360 extern void openpic_initirq(u_int irq, u_int pri, u_int vector, int polarity,
 361                             int is_level);
 362 extern void openpic_mapirq(u_int irq, u_int cpumask);
 363 extern void openpic_set_sense(u_int irq, int sense);
 364
 365 #endif /* __KERNEL__ */
 366
 367 #endif /* _LINUX_OPENPIC_H */