1 /* $Id: asm.h,v 1.2 1999/12/04 03:59:12 ralf Exp $
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (C) 1995, 1996, 1997, 1999 by Ralf Baechle
8 * Copyright (C) 1999 by Silicon Graphics, Inc.
10 * Some useful macros for MIPS assembler code
12 * Some of the routines below contain useless nops that will be optimized
13 * away by gas in -O mode. These nops are however required to fill delay
14 * slots in noreorder mode.
19 #include <asm/sgidefs.h>
22 * PIC specific declarations
23 * Not used for the kernel but here seems to be the right place.
26 #define CPRESTORE(register) \
28 #define CPADD(register) \
30 #define CPLOAD(register) \
33 #define CPRESTORE(register)
34 #define CPADD(register)
35 #define CPLOAD(register)
39 * LEAF - declare leaf routine
41 #define LEAF(symbol) \
44 .type symbol,@function; \
46 symbol: .frame sp,0,ra
49 * NESTED - declare nested routine entry point
51 #define NESTED(symbol, framesize, rpc) \
54 .type symbol,@function; \
56 symbol: .frame sp, framesize, rpc
59 * END - mark end of function
61 #define END(function) \
63 .size function,.-function
66 * EXPORT - export definition of symbol
68 #define EXPORT(symbol) \
73 * FEXPORT - export definition of a function symbol
75 #define FEXPORT(symbol) \
77 .type symbol,@function; \
81 * ABS - export absolute symbol
83 #define ABS(symbol,value) \
97 * Print formated string
99 #define PRINT(string) \
108 * Print formated string
110 #define PROM_PRINT(string) \
126 #define TTABLE(string) \
135 * MIPS IV pref instruction.
136 * Use with .set noreorder only!
138 * MIPS IV implementations are free to treat this as a nop. The R5000
139 * is one of them. So we should have an option not to use this instruction.
141 #if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5)
142 #define PREF(hint,addr) \
144 #define PREFX(hint,addr) \
152 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
154 #if _MIPS_ISA == _MIPS_ISA_MIPS1
155 #define MOVN(rd,rs,rt) \
162 #define MOVZ(rd,rs,rt) \
169 #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
170 #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
171 #define MOVN(rd,rs,rt) \
178 #define MOVZ(rd,rs,rt) \
185 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
186 #if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5)
187 #define MOVN(rd,rs,rt) \
189 #define MOVZ(rd,rs,rt) \
191 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) */
196 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2)
200 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
201 (_MIPS_ISA == _MIPS_ISA_MIPS5)
216 * Use the following macros in assemblercode to load/store registers,
219 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2)
222 #define PTR_SUBU dsubu
223 #define PTR_ADDU daddu
225 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
226 (_MIPS_ISA == _MIPS_ISA_MIPS5)
229 /* We still live in a 32 bit address space ... */
230 #define PTR_SUBU dsubu
231 #define PTR_ADDU daddu
235 * How to add/sub/load/store/shift C int variables.
237 #if (_MIPS_SZINT == 32)
239 #define INT_ADDI addi
240 #define INT_ADDU addu
241 #define INT_ADDIU addiu
243 #define INT_SUBI subi
244 #define INT_SUBU subu
245 #define INT_SUBIU subu
250 #if (_MIPS_SZINT == 64)
252 #define INT_ADDI daddi
253 #define INT_ADDU daddu
254 #define INT_ADDIU daddiu
256 #define INT_SUBI dsubi
257 #define INT_SUBU dsubu
258 #define INT_SUBIU dsubu
264 * How to add/sub/load/store/shift C long variables.
266 #if (_MIPS_SZLONG == 32)
268 #define LONG_ADDI addi
269 #define LONG_ADDU addu
270 #define LONG_ADDIU addiu
272 #define LONG_SUBI subi
273 #define LONG_SUBU subu
274 #define LONG_SUBIU subu
278 #define LONG_SLLV sllv
280 #define LONG_SRLV srlv
282 #define LONG_SRAV srav
285 #if (_MIPS_SZLONG == 64)
286 #define LONG_ADD dadd
287 #define LONG_ADDI daddi
288 #define LONG_ADDU daddu
289 #define LONG_ADDIU daddiu
290 #define LONG_SUB dadd
291 #define LONG_SUBI dsubi
292 #define LONG_SUBU dsubu
293 #define LONG_SUBIU dsubu
296 #define LONG_SLL dsll
297 #define LONG_SLLV dsllv
298 #define LONG_SRL dsrl
299 #define LONG_SRLV dsrlv
300 #define LONG_SRA dsra
301 #define LONG_SRAV dsrav
305 * How to add/sub/load/store/shift pointers.
307 #if (_MIPS_SZPTR == 32)
309 #define PTR_ADDI addi
310 #define PTR_ADDU addu
311 #define PTR_ADDIU addiu
313 #define PTR_SUBI subi
314 #define PTR_SUBU subu
315 #define PTR_SUBIU subu
319 #define PTR_SLLV sllv
321 #define PTR_SRLV srlv
323 #define PTR_SRAV srav
325 #define PTR_SCALESHIFT 2
332 #if (_MIPS_SZPTR == 64)
334 #define PTR_ADDI daddi
335 #define PTR_ADDU daddu
336 #define PTR_ADDIU daddiu
338 #define PTR_SUBI dsubi
339 #define PTR_SUBU dsubu
340 #define PTR_SUBIU dsubu
344 #define PTR_SLLV dsllv
346 #define PTR_SRLV dsrlv
348 #define PTR_SRAV dsrav
350 #define PTR_SCALESHIFT 3
358 * Some cp0 registers were extended to 64bit for MIPS III.
360 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2)
364 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
365 (_MIPS_ISA == _MIPS_ISA_MIPS5)
370 #endif /* _ASM_ASM_H */