drivers/usb/serial/mct_u232.h

   1 /*
   2  * Definitions for MCT (Magic Control Technology) USB-RS232 Converter Driver
   3  *
   4  *   Copyright (C) 2000 Wolfgang Grandegger (wolfgang@ces.ch)
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation; either version 2 of the License, or
   9  *   (at your option) any later version.
  10  *
  11  * This driver is for the device MCT USB-RS232 Converter (25 pin, Model No.
  12  * U232-P25) from Magic Control Technology Corp. (there is also a 9 pin
  13  * Model No. U232-P9). See http://www.mct.com.tw/p_u232.html for further
  14  * information. The properties of this device are listed at the end of this
  15  * file. This device is available from various distributors. I know Hana,
  16  * http://www.hana.de and D-Link, http://www.dlink.com/products/usb/dsbs25.
  17  *
  18  * All of the information about the device was acquired by using SniffUSB
  19  * on Windows98. The technical details of the reverse engineering are
  20  * summarized at the end of this file.
  21  */
  22
  23 #ifndef __LINUX_USB_SERIAL_MCT_U232_H
  24 #define __LINUX_USB_SERIAL_MCT_U232_H
  25
  26 #define MCT_U232_VID                    0x0711  /* Vendor Id */
  27 #define MCT_U232_PID                    0x0210  /* Product Id */
  28
  29 /*
  30  * Vendor Request Interface
  31  */
  32 #define MCT_U232_SET_REQUEST_TYPE       0x40
  33 #define MCT_U232_GET_REQUEST_TYPE       0xc0
  34
  35 #define MCT_U232_GET_MODEM_STAT_REQUEST 2  /* Get Modem Status Register (MSR) */
  36 #define MCT_U232_GET_MODEM_STAT_SIZE    1
  37
  38 #define MCT_U232_GET_LINE_CTRL_REQUEST  6  /* Get Line Control Register (LCR) */
  39 #define MCT_U232_GET_LINE_CTRL_SIZE     1  /* ... not used by this driver */
  40
  41 #define MCT_U232_SET_BAUD_RATE_REQUEST  5  /* Set Baud Rate Divisor */
  42 #define MCT_U232_SET_BAUD_RATE_SIZE     4
  43
  44 #define MCT_U232_SET_LINE_CTRL_REQUEST  7  /* Set Line Control Register (LCR) */
  45 #define MCT_U232_SET_LINE_CTRL_SIZE     1
  46
  47 #define MCT_U232_SET_MODEM_CTRL_REQUEST 10 /* Set Modem Control Register (MCR) */
  48 #define MCT_U232_SET_MODEM_CTRL_SIZE    1
  49
  50 /*
  51  * Baud rate (divisor)
  52  */
  53 #define MCT_U232_BAUD_RATE(b)           (115200/b)
  54
  55 /*
  56  * Line Control Register (LCR)
  57  */
  58 #define MCT_U232_SET_BREAK              0x40
  59
  60 #define MCT_U232_PARITY_SPACE           0x38
  61 #define MCT_U232_PARITY_MARK            0x28
  62 #define MCT_U232_PARITY_EVEN            0x18
  63 #define MCT_U232_PARITY_ODD             0x08
  64 #define MCT_U232_PARITY_NONE            0x00
  65
  66 #define MCT_U232_DATA_BITS_5            0x00
  67 #define MCT_U232_DATA_BITS_6            0x01
  68 #define MCT_U232_DATA_BITS_7            0x02
  69 #define MCT_U232_DATA_BITS_8            0x03
  70
  71 #define MCT_U232_STOP_BITS_2            0x04
  72 #define MCT_U232_STOP_BITS_1            0x00
  73
  74 /*
  75  * Modem Control Register (MCR)
  76  */
  77 #define MCT_U232_MCR_NONE               0x8     /* Deactivate DTR and RTS */
  78 #define MCT_U232_MCR_RTS                0xa     /* Activate RTS */
  79 #define MCT_U232_MCR_DTR                0x9     /* Activate DTR */
  80
  81 /*
  82  * Modem Status Register (MSR)
  83  */
  84 #define MCT_U232_MSR_INDEX              0x0     /* data[index] */
  85 #define MCT_U232_MSR_CD                 0x80    /* Current CD */
  86 #define MCT_U232_MSR_RI                 0x40    /* Current RI */
  87 #define MCT_U232_MSR_DSR                0x20    /* Current DSR */
  88 #define MCT_U232_MSR_CTS                0x10    /* Current CTS */
  89 #define MCT_U232_MSR_DCD                0x08    /* Delta CD */
  90 #define MCT_U232_MSR_DRI                0x04    /* Delta RI */
  91 #define MCT_U232_MSR_DDSR               0x02    /* Delta DSR */
  92 #define MCT_U232_MSR_DCTS               0x01    /* Delta CTS */
  93
  94 /*
  95  * Line Status Register (LSR)
  96  */
  97 #define MCT_U232_LSR_INDEX              1       /* data[index] */
  98 #define MCT_U232_LSR_ERR                0x80    /* OE | PE | FE | BI */
  99 #define MCT_U232_LSR_TEMT               0x40    /* transmit register empty */
 100 #define MCT_U232_LSR_THRE               0x20    /* transmit holding register empty */
 101 #define MCT_U232_LSR_BI                 0x10    /* break indicator */
 102 #define MCT_U232_LSR_FE                 0x08    /* framing error */
 103 #define MCT_U232_LSR_OE                 0x02    /* overrun error */
 104 #define MCT_U232_LSR_PE                 0x04    /* parity error */
 105 #define MCT_U232_LSR_OE                 0x02    /* overrun error */
 106 #define MCT_U232_LSR_DR                 0x01    /* receive data ready */
 107
 108
 109 /* -----------------------------------------------------------------------------
 110  * Technical Specification reverse engineered with SniffUSB on Windows98
 111  * =====================================================================
 112  *
 113  *  The technical details of the device have been acquired be using "SniffUSB"
 114  *  and the vendor-supplied device driver (version 2.3A) under Windows98. To
 115  *  identify the USB vendor-specific requests and to assign them to terminal
 116  *  settings (flow control, baud rate, etc.) the program "SerialSettings" from
 117  *  William G. Greathouse has been proven to be very useful. I also used the
 118  *  Win98 "HyperTerminal" and "usb-robot" on Linux for testing. The results and
 119  *  observations are summarized below:
 120  *
 121  *  The USB requests seem to be directly mapped to the registers of a 8250,
 122  *  16450 or 16550 UART. The FreeBSD handbook (appendix F.4 "Input/Output
 123  *  devices") contains a comprehensive description of UARTs and its registers.
 124  *  The bit descriptions are actually taken from there.
 125  *
 126  *
 127  * Baud rate (divisor)
 128  * -------------------
 129  *
 130  *   BmRequestType:  0x4 (0100 0000B)
 131  *   bRequest:       0x5
 132  *   wValue:         0x0
 133  *   wIndex:         0x0
 134  *   wLength:        0x4
 135  *   Data:           divisor = 115200 / baud_rate
 136  *
 137  *
 138  * Line Control Register (LCR)
 139  * ---------------------------
 140  *
 141  *  BmRequestType:  0x4 (0100 0000B)    0xc (1100 0000B)
 142  *  bRequest:       0x7                 0x6
 143  *  wValue:         0x0
 144  *  wIndex:         0x0
 145  *  wLength:        0x1
 146  *  Data:           LCR (see below)
 147  *
 148  *  Bit 7: Divisor Latch Access Bit (DLAB). When set, access to the data
 149  *         transmit/receive register (THR/RBR) and the Interrupt Enable Register
 150  *         (IER) is disabled. Any access to these ports is now redirected to the
 151  *         Divisor Latch Registers. Setting this bit, loading the Divisor
 152  *         Registers, and clearing DLAB should be done with interrupts disabled.
 153  *  Bit 6: Set Break. When set to "1", the transmitter begins to transmit
 154  *         continuous Spacing until this bit is set to "0". This overrides any
 155  *         bits of characters that are being transmitted.
 156  *  Bit 5: Stick Parity. When parity is enabled, setting this bit causes parity
 157  *         to always be "1" or "0", based on the value of Bit 4.
 158  *  Bit 4: Even Parity Select (EPS). When parity is enabled and Bit 5 is "0",
 159  *         setting this bit causes even parity to be transmitted and expected.
 160  *         Otherwise, odd parity is used.
 161  *  Bit 3: Parity Enable (PEN). When set to "1", a parity bit is inserted
 162  *         between the last bit of the data and the Stop Bit. The UART will also
 163  *         expect parity to be present in the received data.
 164  *  Bit 2: Number of Stop Bits (STB). If set to "1" and using 5-bit data words,
 165  *         1.5 Stop Bits are transmitted and expected in each data word. For
 166  *         6, 7 and 8-bit data words, 2 Stop Bits are transmitted and expected.
 167  *         When this bit is set to "0", one Stop Bit is used on each data word.
 168  *  Bit 1: Word Length Select Bit #1 (WLSB1)
 169  *  Bit 0: Word Length Select Bit #0 (WLSB0)
 170  *         Together these bits specify the number of bits in each data word.
 171  *           1 0  Word Length
 172  *           0 0  5 Data Bits
 173  *           0 1  6 Data Bits
 174  *           1 0  7 Data Bits
 175  *           1 1  8 Data Bits
 176  *
 177  *  SniffUSB observations: Bit 7 seems not to be used. There seem to be two bugs
 178  *  in the Win98 driver: the break does not work (bit 6 is not asserted) and the
 179  *  sticky parity bit is not cleared when set once. The LCR can also be read
 180  *  back with USB request 6 but this has never been observed with SniffUSB.
 181  *
 182  *
 183  * Modem Control Register (MCR)
 184  * ----------------------------
 185  *
 186  *  BmRequestType:  0x4  (0100 0000B)
 187  *  bRequest:       0xa
 188  *  wValue:         0x0
 189  *  wIndex:         0x0
 190  *  wLength:        0x1
 191  *  Data:           MCR (Bit 4..7, see below)
 192  *
 193  *  Bit 7: Reserved, always 0.
 194  *  Bit 6: Reserved, always 0.
 195  *  Bit 5: Reserved, always 0.
 196  *  Bit 4: Loop-Back Enable. When set to "1", the UART transmitter and receiver
 197  *         are internally connected together to allow diagnostic operations. In
 198  *         addition, the UART modem control outputs are connected to the UART
 199  *         modem control inputs. CTS is connected to RTS, DTR is connected to
 200  *         DSR, OUT1 is connected to RI, and OUT 2 is connected to DCD.
 201  *  Bit 3: OUT 2. An auxiliary output that the host processor may set high or
 202  *         low. In the IBM PC serial adapter (and most clones), OUT 2 is used
 203  *         to tri-state (disable) the interrupt signal from the
 204  *         8250/16450/16550 UART.
 205  *  Bit 2: OUT 1. An auxiliary output that the host processor may set high or
 206  *         low. This output is not used on the IBM PC serial adapter.
 207  *  Bit 1: Request to Send (RTS). When set to "1", the output of the UART -RTS
 208  *         line is Low (Active).
 209  *  Bit 0: Data Terminal Ready (DTR). When set to "1", the output of the UART
 210  *         -DTR line is Low (Active).
 211  *
 212  *  SniffUSB observations: Bit 2 and 4 seem not to be used but bit 3 has been
 213  *  seen _always_ set.
 214  *
 215  *
 216  * Modem Status Register (MSR)
 217  * ---------------------------
 218  *
 219  *  BmRequestType:  0xc  (1100 0000B)
 220  *  bRequest:       0x2
 221  *  wValue:         0x0
 222  *  wIndex:         0x0
 223  *  wLength:        0x1
 224  *  Data:           MSR (see below)
 225  *
 226  *  Bit 7: Data Carrier Detect (CD). Reflects the state of the DCD line on the
 227  *         UART.
 228  *  Bit 6: Ring Indicator (RI). Reflects the state of the RI line on the UART.
 229  *  Bit 5: Data Set Ready (DSR). Reflects the state of the DSR line on the UART.
 230  *  Bit 4: Clear To Send (CTS). Reflects the state of the CTS line on the UART.
 231  *  Bit 3: Delta Data Carrier Detect (DDCD). Set to "1" if the -DCD line has
 232  *         changed state one more more times since the last time the MSR was
 233  *         read by the host.
 234  *  Bit 2: Trailing Edge Ring Indicator (TERI). Set to "1" if the -RI line has
 235  *         had a low to high transition since the last time the MSR was read by
 236  *         the host.
 237  *  Bit 1: Delta Data Set Ready (DDSR). Set to "1" if the -DSR line has changed
 238  *         state one more more times since the last time the MSR was read by the
 239  *         host.
 240  *  Bit 0: Delta Clear To Send (DCTS). Set to "1" if the -CTS line has changed
 241  *         state one more times since the last time the MSR was read by the
 242  *         host.
 243  *
 244  *  SniffUSB observations: the MSR is also returned as first byte on the
 245  *  interrupt-in endpoint 0x83 to signal changes of modem status lines. The USB
 246  *  request to read MSR cannot be applied during normal device operation.
 247  *
 248  *
 249  * Line Status Register (LSR)
 250  * --------------------------
 251  *
 252  *  Bit 7   Error in Receiver FIFO. On the 8250/16450 UART, this bit is zero.
 253  *          This bit is set to "1" when any of the bytes in the FIFO have one or
 254  *          more of the following error conditions: PE, FE, or BI.
 255  *  Bit 6   Transmitter Empty (TEMT). When set to "1", there are no words
 256  *          remaining in the transmit FIFO or the transmit shift register. The
 257  *          transmitter is completely idle.
 258  *  Bit 5   Transmitter Holding Register Empty (THRE). When set to "1", the FIFO
 259  *          (or holding register) now has room for at least one additional word
 260  *          to transmit. The transmitter may still be transmitting when this bit
 261  *          is set to "1".
 262  *  Bit 4   Break Interrupt (BI). The receiver has detected a Break signal.
 263  *  Bit 3   Framing Error (FE). A Start Bit was detected but the Stop Bit did not
 264  *          appear at the expected time. The received word is probably garbled.
 265  *  Bit 2   Parity Error (PE). The parity bit was incorrect for the word received.
 266  *  Bit 1   Overrun Error (OE). A new word was received and there was no room in
 267  *          the receive buffer. The newly-arrived word in the shift register is
 268  *          discarded. On 8250/16450 UARTs, the word in the holding register is
 269  *          discarded and the newly- arrived word is put in the holding register.
 270  *  Bit 0   Data Ready (DR). One or more words are in the receive FIFO that the
 271  *          host may read. A word must be completely received and moved from the
 272  *          shift register into the FIFO (or holding register for 8250/16450
 273  *          designs) before this bit is set.
 274  *
 275  *  SniffUSB observations: the LSR is returned as second byte on the interrupt-in
 276  *  endpoint 0x83 to signal error conditions. Such errors have been seen with
 277  *  minicom/zmodem transfers (CRC errors).
 278  *
 279  *
 280  * Flow control
 281  * ------------
 282  *
 283  *  SniffUSB observations: no flow control specific requests have been realized
 284  *  apart from DTR/RTS settings. Both signals are dropped for no flow control
 285  *  but asserted for hardware or software flow control.
 286  *
 287  *
 288  * Endpoint usage
 289  * --------------
 290  *
 291  *  SniffUSB observations: the bulk-out endpoint 0x1 and interrupt-in endpoint
 292  *  0x81 is used to transmit and receive characters. The second interrupt-in
 293  *  endpoint 0x83 signals exceptional conditions like modem line changes and
 294  *  errors. The first byte returned is the MSR and the second byte the LSR.
 295  *
 296  *
 297  * Other observations
 298  * ------------------
 299  *
 300  *  Queued bulk transfers like used in visor.c did not work.
 301  *
 302  *
 303  * Properties of the USB device used (as found in /var/log/messages)
 304  * -----------------------------------------------------------------
 305  *
 306  *  Manufacturer: MCT Corporation.
 307  *  Product: USB-232 Interfact Controller
 308  *  SerialNumber: U2S22050
 309  *
 310  *    Length              = 18
 311  *    DescriptorType      = 01
 312  *    USB version         = 1.00
 313  *    Vendor:Product      = 0711:0210
 314  *    MaxPacketSize0      = 8
 315  *    NumConfigurations   = 1
 316  *    Device version      = 1.02
 317  *    Device Class:SubClass:Protocol = 00:00:00
 318  *      Per-interface classes
 319  *  Configuration:
 320  *    bLength             =    9
 321  *    bDescriptorType     =   02
 322  *    wTotalLength        = 0027
 323  *    bNumInterfaces      =   01
 324  *    bConfigurationValue =   01
 325  *    iConfiguration      =   00
 326  *    bmAttributes        =   c0
 327  *    MaxPower            =  100mA
 328  *
 329  *    Interface: 0
 330  *    Alternate Setting:  0
 331  *      bLength             =    9
 332  *      bDescriptorType     =   04
 333  *      bInterfaceNumber    =   00
 334  *      bAlternateSetting   =   00
 335  *      bNumEndpoints       =   03
 336  *      bInterface Class:SubClass:Protocol =   00:00:00
 337  *      iInterface          =   00
 338  *      Endpoint:
 339  *        bLength             =    7
 340  *        bDescriptorType     =   05
 341  *        bEndpointAddress    =   81 (in)
 342  *        bmAttributes        =   03 (Interrupt)
 343  *        wMaxPacketSize      = 0040
 344  *        bInterval           =   02
 345  *      Endpoint:
 346  *        bLength             =    7
 347  *        bDescriptorType     =   05
 348  *        bEndpointAddress    =   01 (out)
 349  *        bmAttributes        =   02 (Bulk)
 350  *        wMaxPacketSize      = 0040
 351  *        bInterval           =   00
 352  *      Endpoint:
 353  *        bLength             =    7
 354  *        bDescriptorType     =   05
 355  *        bEndpointAddress    =   83 (in)
 356  *        bmAttributes        =   03 (Interrupt)
 357  *        wMaxPacketSize      = 0002
 358  *        bInterval           =   02
 359  */
 360
 361 #endif /* __LINUX_USB_SERIAL_MCT_U232_H */
 362