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- Stephen Rothwell: APM updates
[davej-history.git] / drivers / sound / cs4281.c
blob661caa2144ab15fbae7fae4ecf4eb1950daace53
1 //*****************************************************************************
2 //
3 // "cs4281.c" -- Cirrus Logic-Crystal CS4281 linux audio driver.
4 //
5 // Copyright (C) 2000 Cirrus Logic Corp.
6 // -- adapted from drivers by Thomas Sailer,
7 // -- but don't bug him; Problems should go to:
8 // -- gw boynton (wesb@crystal.cirrus.com) or
9 // -- tom woller (twoller@crystal.cirrus.com).
10 //
11 // This program is free software; you can redistribute it and/or modify
12 // it under the terms of the GNU General Public License as published by
13 // the Free Software Foundation; either version 2 of the License, or
14 // (at your option) any later version.
15 //
16 // This program is distributed in the hope that it will be useful,
17 // but WITHOUT ANY WARRANTY; without even the implied warranty of
18 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 // GNU General Public License for more details.
20 //
21 // You should have received a copy of the GNU General Public License
22 // along with this program; if not, write to the Free Software
23 // Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 //
25 // Module command line parameters:
26 // none
27 //
28 // Supported devices:
29 // /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
30 // /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
31 // /dev/midi simple MIDI UART interface, no ioctl
32 //
33 // Modification History
34 // 08/20/00 trw - silence and no stopping DAC until release
35 // 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
36 // 09/18/00 trw - added 16bit only record with conversion
37 // 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
38 // capture/playback rates)
39 // 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
40 // libOSSm.so)
41 // 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
42 // 11/03/00 trw - fixed interrupt loss/stutter, added debug.
43 // 11/10/00 bkz - added __devinit to cs4281_hw_init()
44 //
45 // *****************************************************************************
46
47 #include <linux/config.h>
48 #include <linux/version.h>
49 #include <linux/module.h>
50 #include <linux/string.h>
51 #include <linux/ioport.h>
52 #include <linux/sched.h>
53 #include <linux/delay.h>
54 #include <linux/sound.h>
55 #include <linux/malloc.h>
56 #include <linux/soundcard.h>
57 #include <linux/pci.h>
58 #include <linux/bitops.h>
59 #include <linux/spinlock.h>
60 #include <asm/io.h>
61 #include <asm/dma.h>
62 #include <linux/init.h>
63 #include <linux/poll.h>
64 #include <linux/smp_lock.h>
65 #include <linux/wrapper.h>
66 #include <asm/uaccess.h>
67 #include <asm/hardirq.h>
68 //#include <linux/vmalloc.h>
69 #include "dm.h"
70 #include "cs4281_hwdefs.h"
71
72 EXPORT_NO_SYMBOLS;
73
74 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
75
76 // ---------------------------------------------------------------------
77
78 #ifndef PCI_VENDOR_ID_CIRRUS
79 #define PCI_VENDOR_ID_CIRRUS 0x1013
80 #endif
81 #ifndef PCI_DEVICE_ID_CRYSTAL_CS4281
82 #define PCI_DEVICE_ID_CRYSTAL_CS4281 0x6005
83 #endif
84
85 #define CS4281_MAGIC ((PCI_DEVICE_ID_CRYSTAL_CS4281<<16) | PCI_VENDOR_ID_CIRRUS)
86
87 // Turn on/off debugging compilation by using 1/0 respectively for CSDEBUG
88 //
89 #define CSDEBUG_INTERFACE 1
90 #define CSDEBUG 1
91 //
92 // CSDEBUG is usual mode is set to 1, then use the
93 // cs_debuglevel and cs_debugmask to turn on or off debugging.
94 // Debug level of 1 has been defined to be kernel errors and info
95 // that should be printed on any released driver.
96 //
97 #if CSDEBUG
98 extern unsigned long cs_debugmask;
99 extern unsigned long cs_debuglevel;
100 #define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
101 #else
102 #define CS_DBGOUT(mask,level,x)
103 #endif
104 //
105 // cs_debugmask areas
106 //
107 #define CS_INIT 0x00000001 // initialization and probe functions
108 #define CS_ERROR 0x00000002 // tmp debugging bit placeholder
109 #define CS_INTERRUPT 0x00000004 // interrupt handler (separate from all other)
110 #define CS_FUNCTION 0x00000008 // enter/leave functions
111 #define CS_WAVE_WRITE 0x00000010 // write information for wave
112 #define CS_WAVE_READ 0x00000020 // read information for wave
113 #define CS_MIDI_WRITE 0x00000040 // write information for midi
114 #define CS_MIDI_READ 0x00000080 // read information for midi
115 #define CS_MPU401_WRITE 0x00000100 // write information for mpu401
116 #define CS_MPU401_READ 0x00000200 // read information for mpu401
117 #define CS_OPEN 0x00000400 // all open functions in the driver
118 #define CS_RELEASE 0x00000800 // all release functions in the driver
119 #define CS_PARMS 0x00001000 // functional and operational parameters
120 #define CS_IOCTL 0x00002000 // ioctl (non-mixer)
121 #define CS_TMP 0x10000000 // tmp debug mask bit
122
123 #if CSDEBUG
124 static unsigned long cs_debuglevel = 1; // levels range from 1-9
125 static unsigned long cs_debugmask = CS_INIT | CS_ERROR; // use CS_DBGOUT with various mask values
126 #if MODULE
127 MODULE_PARM(cs_debuglevel, "i");
128 MODULE_PARM(cs_debugmask, "i");
129 #endif
130 #endif
131
132 // MIDI buffer sizes
133 #define MIDIINBUF 500
134 #define MIDIOUTBUF 500
135
136 #define FMODE_MIDI_SHIFT 3
137 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
138 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
139
140 #define RSRCISIOREGION(dev,num) ((dev)->resource[(num)].start != 0 && \
141 ((dev)->resource[(num)].flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
142 #define RSRCISMEMORYREGION(dev,num) ((dev)->resource[(num)].start != 0 && \
143 ((dev)->resource[(num)].flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY)
144 #define RSRCADDRESS(dev,num) ((dev)->resource[(num)].start)
145
146 #define CS4281_MAJOR_VERSION 1
147 #define CS4281_MINOR_VERSION 1
148 #ifdef __ia64__
149 #define CS4281_ARCH 64 //architecture key
150 #else
151 #define CS4281_ARCH 32 //architecture key
152 #endif
153
154 #define CS_TYPE_ADC 0
155 #define CS_TYPE_DAC 1
156
157 struct cs4281_state {
158 // magic
159 unsigned int magic;
160
161 // we keep the cards in a linked list
162 struct cs4281_state *next;
163
164 // pcidev is needed to turn off the DDMA controller at driver shutdown
165 struct pci_dev *pcidev;
166
167 // soundcore stuff
168 int dev_audio;
169 int dev_mixer;
170 int dev_midi;
171
172 // hardware resources
173 unsigned int pBA0phys, pBA1phys;
174 char *pBA0, *pBA1;
175 unsigned int irq;
176
177 // mixer registers
178 struct {
179 unsigned short vol[10];
180 unsigned int recsrc;
181 unsigned int modcnt;
182 unsigned short micpreamp;
183 } mix;
184
185 // wave stuff
186 struct properties {
187 unsigned fmt;
188 unsigned fmt_original; // original requested format
189 unsigned channels;
190 unsigned rate;
191 unsigned char clkdiv;
192 } prop_dac, prop_adc;
193 unsigned conversion:1; // conversion from 16 to 8 bit in progress
194 void *tmpbuff; // tmp buffer for sample conversions
195 unsigned ena;
196 spinlock_t lock;
197 struct semaphore open_sem;
198 struct semaphore open_sem_adc;
199 struct semaphore open_sem_dac;
200 mode_t open_mode;
201 wait_queue_head_t open_wait;
202 wait_queue_head_t open_wait_adc;
203 wait_queue_head_t open_wait_dac;
204
205 dma_addr_t dmaaddr_tmpbuff;
206 unsigned buforder_tmpbuff; // Log base 2 of 'rawbuf' size in bytes..
207 struct dmabuf {
208 void *rawbuf; // Physical address of
209 dma_addr_t dmaaddr;
210 unsigned buforder; // Log base 2 of 'rawbuf' size in bytes..
211 unsigned numfrag; // # of 'fragments' in the buffer.
212 unsigned fragshift; // Log base 2 of fragment size.
213 unsigned hwptr, swptr;
214 unsigned total_bytes; // # bytes process since open.
215 unsigned blocks; // last returned blocks value GETOPTR
216 unsigned wakeup; // interrupt occurred on block
217 int count;
218 unsigned error; // over/underrun
219 wait_queue_head_t wait;
220 // redundant, but makes calculations easier
221 unsigned fragsize; // 2**fragshift..
222 unsigned dmasize; // 2**buforder.
223 unsigned fragsamples;
224 // OSS stuff
225 unsigned mapped:1; // Buffer mapped in cs4281_mmap()?
226 unsigned ready:1; // prog_dmabuf_dac()/adc() successful?
227 unsigned endcleared:1;
228 unsigned type:1; // adc or dac buffer (CS_TYPE_XXX)
229 unsigned ossfragshift;
230 int ossmaxfrags;
231 unsigned subdivision;
232 } dma_dac, dma_adc;
233
234 // midi stuff
235 struct {
236 unsigned ird, iwr, icnt;
237 unsigned ord, owr, ocnt;
238 wait_queue_head_t iwait;
239 wait_queue_head_t owait;
240 struct timer_list timer;
241 unsigned char ibuf[MIDIINBUF];
242 unsigned char obuf[MIDIOUTBUF];
243 } midi;
244
245 };
246
247 #if CSDEBUG
248
249 // DEBUG ROUTINES
250
251 #define SOUND_MIXER_CS_GETDBGLEVEL _SIOWR('M',120, int)
252 #define SOUND_MIXER_CS_SETDBGLEVEL _SIOWR('M',121, int)
253 #define SOUND_MIXER_CS_GETDBGMASK _SIOWR('M',122, int)
254 #define SOUND_MIXER_CS_SETDBGMASK _SIOWR('M',123, int)
255
256 #define SNDCTL_DSP_CS_GETDBGLEVEL _SIOWR('P', 50, int)
257 #define SNDCTL_DSP_CS_SETDBGLEVEL _SIOWR('P', 51, int)
258 #define SNDCTL_DSP_CS_GETDBGMASK _SIOWR('P', 52, int)
259 #define SNDCTL_DSP_CS_SETDBGMASK _SIOWR('P', 53, int)
260
261 static void printioctl(unsigned int x)
262 {
263 unsigned int i;
264 unsigned char vidx;
265 // Index of mixtable1[] member is Device ID
266 // and must be <= SOUND_MIXER_NRDEVICES.
267 // Value of array member is index into s->mix.vol[]
268 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
269 [SOUND_MIXER_PCM] = 1, // voice
270 [SOUND_MIXER_LINE1] = 2, // AUX
271 [SOUND_MIXER_CD] = 3, // CD
272 [SOUND_MIXER_LINE] = 4, // Line
273 [SOUND_MIXER_SYNTH] = 5, // FM
274 [SOUND_MIXER_MIC] = 6, // Mic
275 [SOUND_MIXER_SPEAKER] = 7, // Speaker
276 [SOUND_MIXER_RECLEV] = 8, // Recording level
277 [SOUND_MIXER_VOLUME] = 9 // Master Volume
278 };
279
280 switch (x) {
281 case SOUND_MIXER_CS_GETDBGMASK:
282 CS_DBGOUT(CS_IOCTL, 4,
283 printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
284 break;
285 case SOUND_MIXER_CS_GETDBGLEVEL:
286 CS_DBGOUT(CS_IOCTL, 4,
287 printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
288 break;
289 case SOUND_MIXER_CS_SETDBGMASK:
290 CS_DBGOUT(CS_IOCTL, 4,
291 printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
292 break;
293 case SOUND_MIXER_CS_SETDBGLEVEL:
294 CS_DBGOUT(CS_IOCTL, 4,
295 printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
296 break;
297 case OSS_GETVERSION:
298 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
299 break;
300 case SNDCTL_DSP_SYNC:
301 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
302 break;
303 case SNDCTL_DSP_SETDUPLEX:
304 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
305 break;
306 case SNDCTL_DSP_GETCAPS:
307 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
308 break;
309 case SNDCTL_DSP_RESET:
310 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
311 break;
312 case SNDCTL_DSP_SPEED:
313 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
314 break;
315 case SNDCTL_DSP_STEREO:
316 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
317 break;
318 case SNDCTL_DSP_CHANNELS:
319 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
320 break;
321 case SNDCTL_DSP_GETFMTS:
322 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
323 break;
324 case SNDCTL_DSP_SETFMT:
325 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
326 break;
327 case SNDCTL_DSP_POST:
328 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
329 break;
330 case SNDCTL_DSP_GETTRIGGER:
331 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
332 break;
333 case SNDCTL_DSP_SETTRIGGER:
334 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
335 break;
336 case SNDCTL_DSP_GETOSPACE:
337 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
338 break;
339 case SNDCTL_DSP_GETISPACE:
340 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
341 break;
342 case SNDCTL_DSP_NONBLOCK:
343 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
344 break;
345 case SNDCTL_DSP_GETODELAY:
346 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
347 break;
348 case SNDCTL_DSP_GETIPTR:
349 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
350 break;
351 case SNDCTL_DSP_GETOPTR:
352 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
353 break;
354 case SNDCTL_DSP_GETBLKSIZE:
355 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
356 break;
357 case SNDCTL_DSP_SETFRAGMENT:
358 CS_DBGOUT(CS_IOCTL, 4,
359 printk("SNDCTL_DSP_SETFRAGMENT:\n"));
360 break;
361 case SNDCTL_DSP_SUBDIVIDE:
362 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
363 break;
364 case SOUND_PCM_READ_RATE:
365 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
366 break;
367 case SOUND_PCM_READ_CHANNELS:
368 CS_DBGOUT(CS_IOCTL, 4,
369 printk("SOUND_PCM_READ_CHANNELS:\n"));
370 break;
371 case SOUND_PCM_READ_BITS:
372 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
373 break;
374 case SOUND_PCM_WRITE_FILTER:
375 CS_DBGOUT(CS_IOCTL, 4,
376 printk("SOUND_PCM_WRITE_FILTER:\n"));
377 break;
378 case SNDCTL_DSP_SETSYNCRO:
379 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
380 break;
381 case SOUND_PCM_READ_FILTER:
382 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
383 break;
384 case SNDCTL_DSP_CS_GETDBGMASK:
385 CS_DBGOUT(CS_IOCTL, 4,
386 printk("SNDCTL_DSP_CS_GETDBGMASK:\n"));
387 break;
388 case SNDCTL_DSP_CS_GETDBGLEVEL:
389 CS_DBGOUT(CS_IOCTL, 4,
390 printk("SNDCTL_DSP_CS_GETDBGLEVEL:\n"));
391 break;
392 case SNDCTL_DSP_CS_SETDBGMASK:
393 CS_DBGOUT(CS_IOCTL, 4,
394 printk("SNDCTL_DSP_CS_SETDBGMASK:\n"));
395 break;
396 case SNDCTL_DSP_CS_SETDBGLEVEL:
397 CS_DBGOUT(CS_IOCTL, 4,
398 printk("SNDCTL_DSP_CS_SETDBGLEVEL:\n"));
399 break;
400
401 case SOUND_MIXER_PRIVATE1:
402 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
403 break;
404 case SOUND_MIXER_PRIVATE2:
405 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
406 break;
407 case SOUND_MIXER_PRIVATE3:
408 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
409 break;
410 case SOUND_MIXER_PRIVATE4:
411 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
412 break;
413 case SOUND_MIXER_PRIVATE5:
414 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
415 break;
416 case SOUND_MIXER_INFO:
417 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
418 break;
419 case SOUND_OLD_MIXER_INFO:
420 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
421 break;
422
423 default:
424 switch (_IOC_NR(x)) {
425 case SOUND_MIXER_VOLUME:
426 CS_DBGOUT(CS_IOCTL, 4,
427 printk("SOUND_MIXER_VOLUME:\n"));
428 break;
429 case SOUND_MIXER_SPEAKER:
430 CS_DBGOUT(CS_IOCTL, 4,
431 printk("SOUND_MIXER_SPEAKER:\n"));
432 break;
433 case SOUND_MIXER_RECLEV:
434 CS_DBGOUT(CS_IOCTL, 4,
435 printk("SOUND_MIXER_RECLEV:\n"));
436 break;
437 case SOUND_MIXER_MIC:
438 CS_DBGOUT(CS_IOCTL, 4,
439 printk("SOUND_MIXER_MIC:\n"));
440 break;
441 case SOUND_MIXER_SYNTH:
442 CS_DBGOUT(CS_IOCTL, 4,
443 printk("SOUND_MIXER_SYNTH:\n"));
444 break;
445 case SOUND_MIXER_RECSRC:
446 CS_DBGOUT(CS_IOCTL, 4,
447 printk("SOUND_MIXER_RECSRC:\n"));
448 break;
449 case SOUND_MIXER_DEVMASK:
450 CS_DBGOUT(CS_IOCTL, 4,
451 printk("SOUND_MIXER_DEVMASK:\n"));
452 break;
453 case SOUND_MIXER_RECMASK:
454 CS_DBGOUT(CS_IOCTL, 4,
455 printk("SOUND_MIXER_RECMASK:\n"));
456 break;
457 case SOUND_MIXER_STEREODEVS:
458 CS_DBGOUT(CS_IOCTL, 4,
459 printk("SOUND_MIXER_STEREODEVS:\n"));
460 break;
461 case SOUND_MIXER_CAPS:
462 CS_DBGOUT(CS_IOCTL, 4,
463 printk("SOUND_MIXER_CAPS:\n"));
464 break;
465 default:
466 i = _IOC_NR(x);
467 if (i >= SOUND_MIXER_NRDEVICES
468 || !(vidx = mixtable1[i])) {
469 CS_DBGOUT(CS_IOCTL, 4,
470 printk
471 ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
472 x, i));
473 } else {
474 CS_DBGOUT(CS_IOCTL, 4,
475 printk
476 ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
477 x, i));
478 }
479 break;
480 }
481 }
482 }
483 #endif
484 static int prog_dmabuf_adc(struct cs4281_state *s);
485 static void prog_codec(struct cs4281_state *s, unsigned type);
486
487 static struct cs4281_state *devs = NULL;
488 // ---------------------------------------------------------------------
489 //
490 // Hardware Interfaces For the CS4281
491 //
492
493
494 //******************************************************************************
495 // "delayus()-- Delay for the specified # of microseconds.
496 //******************************************************************************
497 static void delayus(u32 delay)
498 {
499 u32 j;
500 if (delay > 9999) {
501 j = (delay * HZ) / 1000000; /* calculate delay in jiffies */
502 if (j < 1)
503 j = 1; /* minimum one jiffy. */
504 current->state = TASK_UNINTERRUPTIBLE;
505 schedule_timeout(j);
506 } else
507 udelay(delay);
508 return;
509 }
510
511
512 //******************************************************************************
513 // "cs4281_read_ac97" -- Reads a word from the specified location in the
514 // CS4281's address space(based on the BA0 register).
515 //
516 // 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
517 // 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 register,
518 // 0h for reads.
519 // 3. Write ACCTL = Control Register = 460h for initiating the write
520 // 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
521 // 5. if DCV not cleared, break and return error
522 // 6. Read ACSTS = Status Register = 464h, check VSTS bit
523 //****************************************************************************
524 static int cs4281_read_ac97(struct cs4281_state *card, u32 offset,
525 u32 * value)
526 {
527 u32 count, status;
528
529 // Make sure that there is not data sitting
530 // around from a previous uncompleted access.
531 // ACSDA = Status Data Register = 47Ch
532 status = readl(card->pBA0 + BA0_ACSDA);
533
534 // Setup the AC97 control registers on the CS4281 to send the
535 // appropriate command to the AC97 to perform the read.
536 // ACCAD = Command Address Register = 46Ch
537 // ACCDA = Command Data Register = 470h
538 // ACCTL = Control Register = 460h
539 // bit DCV - will clear when process completed
540 // bit CRW - Read command
541 // bit VFRM - valid frame enabled
542 // bit ESYN - ASYNC generation enabled
543
544 // Get the actual AC97 register from the offset
545 writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD);
546 writel(0, card->pBA0 + BA0_ACCDA);
547 writel(ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN,
548 card->pBA0 + BA0_ACCTL);
549
550 // Wait for the read to occur.
551 for (count = 0; count < 10; count++) {
552 // First, we want to wait for a short time.
553 udelay(25);
554
555 // Now, check to see if the read has completed.
556 // ACCTL = 460h, DCV should be reset by now and 460h = 17h
557 if (!(readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV))
558 break;
559 }
560
561 // Make sure the read completed.
562 if (readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV)
563 return 1;
564
565 // Wait for the valid status bit to go active.
566 for (count = 0; count < 10; count++) {
567 // Read the AC97 status register.
568 // ACSTS = Status Register = 464h
569 status = readl(card->pBA0 + BA0_ACSTS);
570
571 // See if we have valid status.
572 // VSTS - Valid Status
573 if (status & ACSTS_VSTS)
574 break;
575 // Wait for a short while.
576 udelay(25);
577 }
578
579 // Make sure we got valid status.
580 if (!(status & ACSTS_VSTS))
581 return 1;
582
583 // Read the data returned from the AC97 register.
584 // ACSDA = Status Data Register = 474h
585 *value = readl(card->pBA0 + BA0_ACSDA);
586
587 // Success.
588 return (0);
589 }
590
591
592 //****************************************************************************
593 //
594 // "cs4281_write_ac97()"-- writes a word to the specified location in the
595 // CS461x's address space (based on the part's base address zero register).
596 //
597 // 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
598 // 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 reg.
599 // 3. Write ACCTL = Control Register = 460h for initiating the write
600 // 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
601 // 5. if DCV not cleared, break and return error
602 //
603 //****************************************************************************
604 static int cs4281_write_ac97(struct cs4281_state *card, u32 offset,
605 u32 value)
606 {
607 u32 count, status;
608
609 CS_DBGOUT(CS_FUNCTION, 2,
610 printk(KERN_INFO "cs4281: cs_4281_write_ac97()+ \n"));
611
612 // Setup the AC97 control registers on the CS4281 to send the
613 // appropriate command to the AC97 to perform the read.
614 // ACCAD = Command Address Register = 46Ch
615 // ACCDA = Command Data Register = 470h
616 // ACCTL = Control Register = 460h
617 // set DCV - will clear when process completed
618 // reset CRW - Write command
619 // set VFRM - valid frame enabled
620 // set ESYN - ASYNC generation enabled
621 // set RSTN - ARST# inactive, AC97 codec not reset
622
623 // Get the actual AC97 register from the offset
624
625 writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD);
626 writel(value, card->pBA0 + BA0_ACCDA);
627 writel(ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN,
628 card->pBA0 + BA0_ACCTL);
629
630 // Wait for the write to occur.
631 for (count = 0; count < 10; count++) {
632 // First, we want to wait for a short time.
633 udelay(25);
634 // Now, check to see if the write has completed.
635 // ACCTL = 460h, DCV should be reset by now and 460h = 07h
636 status = readl(card->pBA0 + BA0_ACCTL);
637 if (!(status & ACCTL_DCV))
638 break;
639 }
640
641 // Make sure the write completed.
642 if (status & ACCTL_DCV) {
643 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
644 "cs4281: cs_4281_write_ac97()- unable to write. ACCTL_DCV active\n"));
645 return 1;
646 }
647 CS_DBGOUT(CS_FUNCTION, 2,
648 printk(KERN_INFO "cs4281: cs_4281_write_ac97()- 0\n"));
649 // Success.
650 return 0;
651 }
652
653
654 //******************************************************************************
655 // "Init4281()" -- Bring up the part.
656 //******************************************************************************
657 static int __devinit cs4281_hw_init(struct cs4281_state *card)
658 {
659 u32 ac97_slotid;
660 u32 temp1, temp2;
661
662 CS_DBGOUT(CS_FUNCTION, 2,
663 printk(KERN_INFO "cs4281: cs4281_hw_init()+ \n"));
664 //***************************************7
665 // Set up the Sound System Configuration
666 //***************************************
667
668 // Set the 'Configuration Write Protect' register
669 // to 4281h. Allows vendor-defined configuration
670 // space between 0e4h and 0ffh to be written.
671
672 writel(0x4281, card->pBA0 + BA0_CWPR); // (3e0h)
673
674 // (0), Blast the clock control register to zero so that the
675 // PLL starts out in a known state, and blast the master serial
676 // port control register to zero so that the serial ports also
677 // start out in a known state.
678
679 writel(0, card->pBA0 + BA0_CLKCR1); // (400h)
680 writel(0, card->pBA0 + BA0_SERMC); // (420h)
681
682
683 // (1), Make ESYN go to zero to turn off
684 // the Sync pulse on the AC97 link.
685
686 writel(0, card->pBA0 + BA0_ACCTL);
687 udelay(50);
688
689
690 // (2) Drive the ARST# pin low for a minimum of 1uS (as defined in
691 // the AC97 spec) and then drive it high. This is done for non
692 // AC97 modes since there might be logic external to the CS461x
693 // that uses the ARST# line for a reset.
694
695 writel(0, card->pBA0 + BA0_SPMC); // (3ech)
696 udelay(100);
697 writel(SPMC_RSTN, card->pBA0 + BA0_SPMC);
698 delayus(50000); // Wait 50 ms for ABITCLK to become stable.
699
700 // (3) Turn on the Sound System Clocks.
701 writel(CLKCR1_PLLP, card->pBA0 + BA0_CLKCR1); // (400h)
702 delayus(50000); // Wait for the PLL to stabilize.
703 // Turn on clocking of the core (CLKCR1(400h) = 0x00000030)
704 writel(CLKCR1_PLLP | CLKCR1_SWCE, card->pBA0 + BA0_CLKCR1);
705
706 // (4) Power on everything for now..
707 writel(0x7E, card->pBA0 + BA0_SSPM); // (740h)
708
709 // (5) Wait for clock stabilization.
710 for (temp1 = 0; temp1 < 1000; temp1++) {
711 udelay(1000);
712 if (readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY)
713 break;
714 }
715 if (!(readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY)) {
716 CS_DBGOUT(CS_ERROR, 1,
717 printk(KERN_ERR "cs4281: DLLRDY failed!\n"));
718 return -EIO;
719 }
720 // (6) Enable ASYNC generation.
721 writel(ACCTL_ESYN, card->pBA0 + BA0_ACCTL); // (460h)
722
723 // Now wait 'for a short while' to allow the AC97
724 // part to start generating bit clock. (so we don't
725 // Try to start the PLL without an input clock.)
726 delayus(50000);
727
728 // Set the serial port timing configuration, so that the
729 // clock control circuit gets its clock from the right place.
730 writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2.
731
732 // (7) Wait for the codec ready signal from the AC97 codec.
733
734 for (temp1 = 0; temp1 < 1000; temp1++) {
735 // Delay a mil to let things settle out and
736 // to prevent retrying the read too quickly.
737 udelay(1000);
738 if (readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY) // If ready, (464h)
739 break; // exit the 'for' loop.
740 }
741 if (!(readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY)) // If never came ready,
742 {
743 CS_DBGOUT(CS_FUNCTION, 2,
744 printk(KERN_ERR
745 "cs4281: ACSTS never came ready!\n"));
746 return -EIO; // exit initialization.
747 }
748 // (8) Assert the 'valid frame' signal so we can
749 // begin sending commands to the AC97 codec.
750 writel(ACCTL_VFRM | ACCTL_ESYN, card->pBA0 + BA0_ACCTL); // (460h)
751
752 // (9), Wait until CODEC calibration is finished.
753 // Print an error message if it doesn't.
754 for (temp1 = 0; temp1 < 1000; temp1++) {
755 delayus(10000);
756 // Read the AC97 Powerdown Control/Status Register.
757 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp2);
758 if ((temp2 & 0x0000000F) == 0x0000000F)
759 break;
760 }
761 if ((temp2 & 0x0000000F) != 0x0000000F) {
762 CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_ERR
763 "cs4281: Codec failed to calibrate. Status = %.8x.\n",
764 temp2));
765 return -EIO;
766 }
767 // (10), Set the serial port timing configuration, so that the
768 // clock control circuit gets its clock from the right place.
769 writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2.
770
771
772 // (11) Wait until we've sampled input slots 3 & 4 as valid, meaning
773 // that the codec is pumping ADC data across the AC link.
774 for (temp1 = 0; temp1 < 1000; temp1++) {
775 // Delay a mil to let things settle out and
776 // to prevent retrying the read too quickly.
777 delayus(1000); //(test)
778
779 // Read the input slot valid register; See
780 // if input slots 3 and 4 are valid yet.
781 if (
782 (readl(card->pBA0 + BA0_ACISV) &
783 (ACISV_ISV3 | ACISV_ISV4)) ==
784 (ACISV_ISV3 | ACISV_ISV4)) break; // Exit the 'for' if slots are valid.
785 }
786 // If we never got valid data, exit initialization.
787 if ((readl(card->pBA0 + BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4))
788 != (ACISV_ISV3 | ACISV_ISV4)) {
789 CS_DBGOUT(CS_FUNCTION, 2,
790 printk(KERN_ERR
791 "cs4281: Never got valid data!\n"));
792 return -EIO; // If no valid data, exit initialization.
793 }
794 // (12), Start digital data transfer of audio data to the codec.
795 writel(ACOSV_SLV3 | ACOSV_SLV4, card->pBA0 + BA0_ACOSV); // (468h)
796
797
798 //**************************************
799 // Unmute the Master and Alternate
800 // (headphone) volumes. Set to max.
801 //**************************************
802 cs4281_write_ac97(card, BA0_AC97_HEADPHONE_VOLUME, 0);
803 cs4281_write_ac97(card, BA0_AC97_MASTER_VOLUME, 0);
804
805 //******************************************
806 // Power on the DAC(AddDACUser()from main())
807 //******************************************
808 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
809 cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfdff);
810
811 // Wait until we sample a DAC ready state.
812 for (temp2 = 0; temp2 < 32; temp2++) {
813 // Let's wait a mil to let things settle.
814 delayus(1000);
815 // Read the current state of the power control reg.
816 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
817 // If the DAC ready state bit is set, stop waiting.
818 if (temp1 & 0x2)
819 break;
820 }
821
822 //******************************************
823 // Power on the ADC(AddADCUser()from main())
824 //******************************************
825 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
826 cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfeff);
827
828 // Wait until we sample ADC ready state.
829 for (temp2 = 0; temp2 < 32; temp2++) {
830 // Let's wait a mil to let things settle.
831 delayus(1000);
832 // Read the current state of the power control reg.
833 cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
834 // If the ADC ready state bit is set, stop waiting.
835 if (temp1 & 0x1)
836 break;
837 }
838 // Set up 4281 Register contents that
839 // don't change for boot duration.
840
841 // For playback, we map AC97 slot 3 and 4(Left
842 // & Right PCM playback) to DMA Channel 0.
843 // Set the fifo to be 15 bytes at offset zero.
844
845 ac97_slotid = 0x01000f00; // FCR0.RS[4:0]=1(=>slot4, right PCM playback).
846 // FCR0.LS[4:0]=0(=>slot3, left PCM playback).
847 // FCR0.SZ[6-0]=15; FCR0.OF[6-0]=0.
848 writel(ac97_slotid, card->pBA0 + BA0_FCR0); // (180h)
849 writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR0); // Turn on FIFO Enable.
850
851 // For capture, we map AC97 slot 10 and 11(Left
852 // and Right PCM Record) to DMA Channel 1.
853 // Set the fifo to be 15 bytes at offset sixteen.
854 ac97_slotid = 0x0B0A0f10; // FCR1.RS[4:0]=11(=>slot11, right PCM record).
855 // FCR1.LS[4:0]=10(=>slot10, left PCM record).
856 // FCR1.SZ[6-0]=15; FCR1.OF[6-0]=16.
857 writel(ac97_slotid | FCRn_PSH, card->pBA0 + BA0_FCR1); // (184h)
858 writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR1); // Turn on FIFO Enable.
859
860 // Map the Playback SRC to the same AC97 slots(3 & 4--
861 // --Playback left & right)as DMA channel 0.
862 // Map the record SRC to the same AC97 slots(10 & 11--
863 // -- Record left & right) as DMA channel 1.
864
865 ac97_slotid = 0x0b0a0100; // SCRSA.PRSS[4:0]=1(=>slot4, right PCM playback).
866 // SCRSA.PLSS[4:0]=0(=>slot3, left PCM playback).
867 // SCRSA.CRSS[4:0]=11(=>slot11, right PCM record)
868 // SCRSA.CLSS[4:0]=10(=>slot10, left PCM record).
869 writel(ac97_slotid, card->pBA0 + BA0_SRCSA); // (75ch)
870
871 // Set 'Half Terminal Count Interrupt Enable' and 'Terminal
872 // Count Interrupt Enable' in DMA Control Registers 0 & 1.
873 // Set 'MSK' flag to 1 to keep the DMA engines paused.
874 temp1 = (DCRn_HTCIE | DCRn_TCIE | DCRn_MSK); // (00030001h)
875 writel(temp1, card->pBA0 + BA0_DCR0); // (154h
876 writel(temp1, card->pBA0 + BA0_DCR1); // (15ch)
877
878 // Set 'Auto-Initialize Control' to 'enabled'; For playback,
879 // set 'Transfer Type Control'(TR[1:0]) to 'read transfer',
880 // for record, set Transfer Type Control to 'write transfer'.
881 // All other bits set to zero; Some will be changed @ transfer start.
882 temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); // (20000018h)
883 writel(temp1, card->pBA0 + BA0_DMR0); // (150h)
884 temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); // (20000014h)
885 writel(temp1, card->pBA0 + BA0_DMR1); // (158h)
886
887 // Enable DMA interrupts generally, and
888 // DMA0 & DMA1 interrupts specifically.
889 temp1 = readl(card->pBA0 + BA0_HIMR) & 0xfffbfcff;
890 writel(temp1, card->pBA0 + BA0_HIMR);
891
892 CS_DBGOUT(CS_FUNCTION, 2,
893 printk(KERN_INFO "cs4281: cs4281_hw_init()- 0\n"));
894 return 0;
895 }
896
897
898 //******************************************************************************
899 // "cs4281_play_rate()" --
900 //******************************************************************************
901 static void cs4281_play_rate(struct cs4281_state *card, u32 playrate)
902 {
903 u32 DACSRvalue = 1;
904
905 // Based on the sample rate, program the DACSR register.
906 if (playrate == 8000)
907 DACSRvalue = 5;
908 if (playrate == 11025)
909 DACSRvalue = 4;
910 else if (playrate == 22050)
911 DACSRvalue = 2;
912 else if (playrate == 44100)
913 DACSRvalue = 1;
914 else if ((playrate <= 48000) && (playrate >= 6023))
915 DACSRvalue = 24576000 / (playrate * 16);
916 else if (playrate < 6023)
917 // Not allowed by open.
918 return;
919 else if (playrate > 48000)
920 // Not allowed by open.
921 return;
922 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 2, printk(KERN_INFO
923 "cs4281: cs4281_play_rate(): DACSRvalue=0x%.8x playrate=%d\n",
924 DACSRvalue,
925 playrate));
926 // Write the 'sample rate select code'
927 // to the 'DAC Sample Rate' register.
928 writel(DACSRvalue, card->pBA0 + BA0_DACSR); // (744h)
929 }
930
931 //******************************************************************************
932 // "cs4281_record_rate()" -- Initialize the record sample rate converter.
933 //******************************************************************************
934 static void cs4281_record_rate(struct cs4281_state *card, u32 outrate)
935 {
936 u32 ADCSRvalue = 1;
937
938 //
939 // Based on the sample rate, program the ADCSR register
940 //
941 if (outrate == 8000)
942 ADCSRvalue = 5;
943 if (outrate == 11025)
944 ADCSRvalue = 4;
945 else if (outrate == 22050)
946 ADCSRvalue = 2;
947 else if (outrate == 44100)
948 ADCSRvalue = 1;
949 else if ((outrate <= 48000) && (outrate >= 6023))
950 ADCSRvalue = 24576000 / (outrate * 16);
951 else if (outrate < 6023) {
952 // Not allowed by open.
953 return;
954 } else if (outrate > 48000) {
955 // Not allowed by open.
956 return;
957 }
958 CS_DBGOUT(CS_WAVE_READ | CS_PARMS, 2, printk(KERN_INFO
959 "cs4281: cs4281_record_rate(): ADCSRvalue=0x%.8x outrate=%d\n",
960 ADCSRvalue, outrate));
961 // Write the 'sample rate select code
962 // to the 'ADC Sample Rate' register.
963 writel(ADCSRvalue, card->pBA0 + BA0_ADCSR); // (748h)
964 }
965
966
967
968 static void stop_dac(struct cs4281_state *s)
969 {
970 unsigned long flags;
971 unsigned temp1;
972
973 CS_DBGOUT(CS_WAVE_WRITE, 3,
974 printk(KERN_INFO "cs4281: stop_dac():\n"));
975 spin_lock_irqsave(&s->lock, flags);
976 s->ena &= ~FMODE_WRITE;
977 temp1 = readl(s->pBA0 + BA0_DCR0) | DCRn_MSK;
978 writel(temp1, s->pBA0 + BA0_DCR0);
979
980 spin_unlock_irqrestore(&s->lock, flags);
981 }
982
983
984 static void start_dac(struct cs4281_state *s)
985 {
986 unsigned long flags;
987 unsigned temp1;
988
989 CS_DBGOUT(CS_FUNCTION, 3,
990 printk(KERN_INFO "cs4281: start_dac()+\n"));
991 spin_lock_irqsave(&s->lock, flags);
992 if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
993 s->dma_dac.count > 0)
994 && s->dma_dac.ready) {
995 s->ena |= FMODE_WRITE;
996 temp1 = readl(s->pBA0 + BA0_DCR0) & ~DCRn_MSK; // Clear DMA0 channel mask.
997 writel(temp1, s->pBA0 + BA0_DCR0); // Start DMA'ing.
998 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Enable interrupts.
999
1000 writel(7, s->pBA0 + BA0_PPRVC);
1001 writel(7, s->pBA0 + BA0_PPLVC);
1002 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
1003 "cs4281: start_dac(): writel 0x%x start dma\n",
1004 temp1));
1005
1006 }
1007 spin_unlock_irqrestore(&s->lock, flags);
1008 CS_DBGOUT(CS_FUNCTION, 3,
1009 printk(KERN_INFO "cs4281: start_dac()-\n"));
1010 }
1011
1012
1013 static void stop_adc(struct cs4281_state *s)
1014 {
1015 unsigned long flags;
1016 unsigned temp1;
1017
1018 CS_DBGOUT(CS_FUNCTION, 3,
1019 printk(KERN_INFO "cs4281: stop_adc()+\n"));
1020
1021 spin_lock_irqsave(&s->lock, flags);
1022 s->ena &= ~FMODE_READ;
1023
1024 if (s->conversion == 1) {
1025 s->conversion = 0;
1026 s->prop_adc.fmt = s->prop_adc.fmt_original;
1027 }
1028 temp1 = readl(s->pBA0 + BA0_DCR1) | DCRn_MSK;
1029 writel(temp1, s->pBA0 + BA0_DCR1);
1030 spin_unlock_irqrestore(&s->lock, flags);
1031 CS_DBGOUT(CS_FUNCTION, 3,
1032 printk(KERN_INFO "cs4281: stop_adc()-\n"));
1033 }
1034
1035
1036 static void start_adc(struct cs4281_state *s)
1037 {
1038 unsigned long flags;
1039 unsigned temp1;
1040
1041 CS_DBGOUT(CS_FUNCTION, 2,
1042 printk(KERN_INFO "cs4281: start_adc()+\n"));
1043
1044 spin_lock_irqsave(&s->lock, flags);
1045 if (!(s->ena & FMODE_READ) &&
1046 (s->dma_adc.mapped || s->dma_adc.count <=
1047 (signed) (s->dma_adc.dmasize - 2 * s->dma_adc.fragsize))
1048 && s->dma_adc.ready) {
1049 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
1050 //
1051 // now only use 16 bit capture, due to truncation issue
1052 // in the chip, noticable distortion occurs.
1053 // allocate buffer and then convert from 16 bit to
1054 // 8 bit for the user buffer.
1055 //
1056 s->prop_adc.fmt_original = s->prop_adc.fmt;
1057 if (s->prop_adc.fmt & AFMT_S8) {
1058 s->prop_adc.fmt &= ~AFMT_S8;
1059 s->prop_adc.fmt |= AFMT_S16_LE;
1060 }
1061 if (s->prop_adc.fmt & AFMT_U8) {
1062 s->prop_adc.fmt &= ~AFMT_U8;
1063 s->prop_adc.fmt |= AFMT_U16_LE;
1064 }
1065 //
1066 // prog_dmabuf_adc performs a stop_adc() but that is
1067 // ok since we really haven't started the DMA yet.
1068 //
1069 prog_codec(s, CS_TYPE_ADC);
1070
1071 if (prog_dmabuf_adc(s) != 0) {
1072 CS_DBGOUT(CS_ERROR, 3,
1073 printk(KERN_INFO
1074 "cs4281: start_adc(): error in prog_dmabuf_adc\n"));
1075 }
1076 s->conversion = 1;
1077 }
1078 s->ena |= FMODE_READ;
1079 temp1 = readl(s->pBA0 + BA0_DCR1) & ~DCRn_MSK; // Clear DMA1 channel mask bit.
1080 writel(temp1, s->pBA0 + BA0_DCR1); // Start recording
1081 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Enable interrupts.
1082 CS_DBGOUT(CS_PARMS, 6,
1083 printk(KERN_INFO
1084 "cs4281: start_adc(): writel 0x%x \n",
1085 temp1));
1086 }
1087 spin_unlock_irqrestore(&s->lock, flags);
1088 CS_DBGOUT(CS_FUNCTION, 2,
1089 printk(KERN_INFO "cs4281: start_adc()-\n"));
1090
1091 }
1092
1093
1094 // ---------------------------------------------------------------------
1095 // use 64k (+1) rather than 32k as some of the higher frequencies need a larger buffer.
1096 // comments reflect 32k.
1097 #define DMABUF_DEFAULTORDER (15-PAGE_SHIFT+1) // == 3(for PC), = log base 2( buff sz = 32k).
1098 #define DMABUF_MINORDER 1 // ==> min buffer size = 8K.
1099
1100
1101 extern void dealloc_dmabuf(struct cs4281_state *s, struct dmabuf *db)
1102 {
1103 struct page *map, *mapend;
1104
1105 if (db->rawbuf) {
1106 // Undo prog_dmabuf()'s marking the pages as reserved
1107 mapend =
1108 virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) -
1109 1);
1110 for (map = virt_to_page(db->rawbuf); map <= mapend; map++)
1111 mem_map_unreserve(map);
1112 pci_free_consistent(s->pcidev, PAGE_SIZE << db->buforder,
1113 db->rawbuf, db->dmaaddr);
1114 }
1115 if (s->tmpbuff && (db->type == CS_TYPE_ADC)) {
1116 // Undo prog_dmabuf()'s marking the pages as reserved
1117 mapend =
1118 virt_to_page(s->tmpbuff +
1119 (PAGE_SIZE << s->buforder_tmpbuff) - 1);
1120 for (map = virt_to_page(s->tmpbuff); map <= mapend; map++)
1121 mem_map_unreserve(map);
1122 pci_free_consistent(s->pcidev,
1123 PAGE_SIZE << s->buforder_tmpbuff,
1124 s->tmpbuff, s->dmaaddr_tmpbuff);
1125 }
1126 s->tmpbuff = NULL;
1127 db->rawbuf = NULL;
1128 db->mapped = db->ready = 0;
1129 }
1130
1131 static int prog_dmabuf(struct cs4281_state *s, struct dmabuf *db)
1132 {
1133 int order;
1134 unsigned bytespersec, temp1;
1135 unsigned bufs, sample_shift = 0;
1136 struct page *map, *mapend;
1137
1138 CS_DBGOUT(CS_FUNCTION, 2,
1139 printk(KERN_INFO "cs4281: prog_dmabuf()+\n"));
1140 db->hwptr = db->swptr = db->total_bytes = db->count = db->error =
1141 db->endcleared = db->blocks = db->wakeup = 0;
1142
1143 if (!db->rawbuf) {
1144 db->ready = db->mapped = 0;
1145 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER;
1146 order--)
1147 if (
1148 (db->rawbuf =
1149 (void *) pci_alloc_consistent(s->pcidev,
1150 PAGE_SIZE <<
1151 order,
1152 &db->
1153 dmaaddr)))
1154 break;
1155 if (!db->rawbuf) {
1156 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
1157 "cs4281: prog_dmabuf(): unable to allocate rawbuf\n"));
1158 return -ENOMEM;
1159 }
1160 db->buforder = order;
1161 // Now mark the pages as reserved; otherwise the
1162 // remap_page_range() in cs4281_mmap doesn't work.
1163 // 1. get index to last page in mem_map array for rawbuf.
1164 mapend =
1165 virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) -
1166 1);
1167
1168 // 2. mark each physical page in range as 'reserved'.
1169 for (map = virt_to_page(db->rawbuf); map <= mapend; map++)
1170 mem_map_reserve(map);
1171 }
1172 if (!s->tmpbuff && (db->type == CS_TYPE_ADC)) {
1173 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER;
1174 order--)
1175 if (
1176 (s->tmpbuff =
1177 (void *) pci_alloc_consistent(s->pcidev,
1178 PAGE_SIZE <<
1179 order,
1180 &s->
1181 dmaaddr_tmpbuff)))
1182 break;
1183 if (!s->tmpbuff) {
1184 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
1185 "cs4281: prog_dmabuf(): unable to allocate tmpbuff\n"));
1186 return -ENOMEM;
1187 }
1188 s->buforder_tmpbuff = order;
1189 // Now mark the pages as reserved; otherwise the
1190 // remap_page_range() in cs4281_mmap doesn't work.
1191 // 1. get index to last page in mem_map array for rawbuf.
1192 mapend =
1193 virt_to_page(s->tmpbuff +
1194 (PAGE_SIZE << s->buforder_tmpbuff) - 1);
1195
1196 // 2. mark each physical page in range as 'reserved'.
1197 for (map = virt_to_page(s->tmpbuff); map <= mapend; map++)
1198 mem_map_reserve(map);
1199 }
1200 if (db->type == CS_TYPE_DAC) {
1201 if (s->prop_dac.fmt & (AFMT_S16_LE | AFMT_U16_LE))
1202 sample_shift++;
1203 if (s->prop_dac.channels > 1)
1204 sample_shift++;
1205 bytespersec = s->prop_dac.rate << sample_shift;
1206 } else // CS_TYPE_ADC
1207 {
1208 if (s->prop_adc.fmt & (AFMT_S16_LE | AFMT_U16_LE))
1209 sample_shift++;
1210 if (s->prop_adc.channels > 1)
1211 sample_shift++;
1212 bytespersec = s->prop_adc.rate << sample_shift;
1213 }
1214 bufs = PAGE_SIZE << db->buforder;
1215
1216
1217 #define INTERRUPT_RATE_MS 100 // Interrupt rate in milliseconds.
1218 db->numfrag = 2;
1219 temp1 = bytespersec / (1000 / INTERRUPT_RATE_MS); // Nominal frag size(bytes/interrupt)
1220 db->fragshift = 8; // Min 256 bytes.
1221 while (1 << db->fragshift < temp1) // Calc power of 2 frag size.
1222 db->fragshift += 1;
1223 db->fragsize = 1 << db->fragshift;
1224 db->dmasize = db->fragsize * 2;
1225 db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment.
1226
1227 // If the calculated size is larger than the allocated
1228 // buffer, divide the allocated buffer into 2 fragments.
1229 if (db->dmasize > bufs) {
1230
1231 db->numfrag = 2; // Two fragments.
1232 db->fragsize = bufs >> 1; // Each 1/2 the alloc'ed buffer.
1233 db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment.
1234 db->dmasize = bufs; // Use all the alloc'ed buffer.
1235
1236 db->fragshift = 0; // Calculate 'fragshift'.
1237 temp1 = db->fragsize; // update_ptr() uses it
1238 while ((temp1 >>= 1) > 1) // to calc 'total-bytes'
1239 db->fragshift += 1; // returned in DSP_GETI/OPTR.
1240 }
1241 CS_DBGOUT(CS_FUNCTION, 2,
1242 printk(KERN_INFO "cs4281: prog_dmabuf()-\n"));
1243 CS_DBGOUT(CS_PARMS, 8,
1244 printk(KERN_INFO
1245 "cs4281: prog_dmabuf(): numfrag=%d fragsize=%d fragsamples=%d fragshift=%d bufs=%d fmt=0x%x ch=%d\n",
1246 db->numfrag, db->fragsize, db->fragsamples,
1247 db->fragshift, bufs,
1248 (db->type ==
1249 CS_TYPE_DAC) ? s->prop_dac.fmt : s->prop_adc.fmt,
1250 (db->type ==
1251 CS_TYPE_DAC) ? s->prop_dac.channels : s->
1252 prop_adc.channels));
1253 return 0;
1254 }
1255
1256
1257 static int prog_dmabuf_adc(struct cs4281_state *s)
1258 {
1259 unsigned long va;
1260 unsigned count;
1261 int c;
1262 stop_adc(s);
1263 s->dma_adc.type = CS_TYPE_ADC;
1264 if ((c = prog_dmabuf(s, &s->dma_adc)))
1265 return c;
1266
1267 if (s->dma_adc.rawbuf) {
1268 memset(s->dma_adc.rawbuf,
1269 (s->prop_adc.
1270 fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1271 s->dma_adc.dmasize);
1272 }
1273 if (s->tmpbuff) {
1274 memset(s->tmpbuff,
1275 (s->prop_adc.
1276 fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1277 PAGE_SIZE << s->buforder_tmpbuff);
1278 }
1279
1280 va = virt_to_bus(s->dma_adc.rawbuf);
1281
1282 count = s->dma_adc.dmasize;
1283
1284 if (s->prop_adc.
1285 fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
1286 count /= 2; // 16-bit.
1287
1288 if (s->prop_adc.channels > 1)
1289 count /= 2; // Assume stereo.
1290
1291 CS_DBGOUT(CS_WAVE_READ, 3, printk(KERN_INFO
1292 "cs4281: prog_dmabuf_adc(): count=%d va=0x%.8x\n",
1293 count, (unsigned) va));
1294
1295 writel(va, s->pBA0 + BA0_DBA1); // Set buffer start address.
1296 writel(count - 1, s->pBA0 + BA0_DBC1); // Set count.
1297 s->dma_adc.ready = 1;
1298 return 0;
1299 }
1300
1301
1302 static int prog_dmabuf_dac(struct cs4281_state *s)
1303 {
1304 unsigned long va;
1305 unsigned count;
1306 int c;
1307 stop_dac(s);
1308 s->dma_dac.type = CS_TYPE_DAC;
1309 if ((c = prog_dmabuf(s, &s->dma_dac)))
1310 return c;
1311 memset(s->dma_dac.rawbuf,
1312 (s->prop_dac.fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1313 s->dma_dac.dmasize);
1314
1315 va = virt_to_bus(s->dma_dac.rawbuf);
1316
1317 count = s->dma_dac.dmasize;
1318 if (s->prop_dac.
1319 fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
1320 count /= 2; // 16-bit.
1321
1322 if (s->prop_dac.channels > 1)
1323 count /= 2; // Assume stereo.
1324
1325 writel(va, s->pBA0 + BA0_DBA0); // Set buffer start address.
1326 writel(count - 1, s->pBA0 + BA0_DBC0); // Set count.
1327
1328 CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO
1329 "cs4281: prog_dmabuf_dac(): count=%d va=0x%.8x\n",
1330 count, (unsigned) va));
1331
1332 s->dma_dac.ready = 1;
1333 return 0;
1334 }
1335
1336
1337 static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
1338 unsigned len, unsigned char c)
1339 {
1340 if (bptr + len > bsize) {
1341 unsigned x = bsize - bptr;
1342 memset(((char *) buf) + bptr, c, x);
1343 bptr = 0;
1344 len -= x;
1345 }
1346 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1347 "cs4281: clear_advance(): memset %d at 0x%.8x for %d size \n",
1348 (unsigned) c,
1349 (unsigned) ((char *) buf) +
1350 bptr, len));
1351 memset(((char *) buf) + bptr, c, len);
1352 }
1353
1354
1355
1356 // call with spinlock held!
1357 static void cs4281_update_ptr(struct cs4281_state *s)
1358 {
1359 int diff;
1360 unsigned hwptr, va;
1361
1362 // update ADC pointer
1363 if (s->ena & FMODE_READ) {
1364 hwptr = readl(s->pBA0 + BA0_DCA1); // Read capture DMA address.
1365 va = virt_to_bus(s->dma_adc.rawbuf);
1366 hwptr -= (unsigned) va;
1367 diff =
1368 (s->dma_adc.dmasize + hwptr -
1369 s->dma_adc.hwptr) % s->dma_adc.dmasize;
1370 s->dma_adc.hwptr = hwptr;
1371 s->dma_adc.total_bytes += diff;
1372 s->dma_adc.count += diff;
1373 if (s->dma_adc.count > s->dma_adc.dmasize)
1374 s->dma_adc.count = s->dma_adc.dmasize;
1375 if (s->dma_adc.mapped) {
1376 if (s->dma_adc.count >=
1377 (signed) s->dma_adc.fragsize) wake_up(&s->
1378 dma_adc.
1379 wait);
1380 } else {
1381 if (s->dma_adc.count > 0)
1382 wake_up(&s->dma_adc.wait);
1383 }
1384 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1385 "cs4281: cs4281_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1386 (unsigned) s,
1387 s->dma_adc.hwptr,
1388 s->dma_adc.total_bytes,
1389 s->dma_adc.count));
1390 }
1391 // update DAC pointer
1392 //
1393 // check for end of buffer, means that we are going to wait for another interrupt
1394 // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
1395 //
1396 if (s->ena & FMODE_WRITE) {
1397 hwptr = readl(s->pBA0 + BA0_DCA0); // Read play DMA address.
1398 va = virt_to_bus(s->dma_dac.rawbuf);
1399 hwptr -= (unsigned) va;
1400 diff =
1401 (s->dma_dac.dmasize + hwptr -
1402 s->dma_dac.hwptr) % s->dma_dac.dmasize;
1403 s->dma_dac.hwptr = hwptr;
1404 s->dma_dac.total_bytes += diff;
1405 if (s->dma_dac.mapped) {
1406 s->dma_dac.count += diff;
1407 if (s->dma_dac.count >= s->dma_dac.fragsize) {
1408 s->dma_dac.wakeup = 1;
1409 wake_up(&s->dma_dac.wait);
1410 if (s->dma_dac.count > s->dma_dac.dmasize)
1411 s->dma_dac.count &=
1412 s->dma_dac.dmasize - 1;
1413 }
1414 } else {
1415
1416 s->dma_dac.count -= diff;
1417 if (s->dma_dac.count <= 0) {
1418 //
1419 // fill with silence, and do not shut down the DAC.
1420 // Continue to play silence until the _release.
1421 //
1422 CS_DBGOUT(CS_WAVE_WRITE, 6,
1423 printk(KERN_INFO
1424 "cs4281: cs4281_update_ptr(): memset %d at 0x%.8x for %d size \n",
1425 (unsigned) (s->prop_dac.
1426 fmt & (AFMT_U8
1427 |
1428 AFMT_U16_LE))
1429 ? 0x80 : 0,
1430 (unsigned) s->dma_dac.
1431 rawbuf,
1432 s->dma_dac.dmasize));
1433 memset(s->dma_dac.rawbuf,
1434 (s->prop_dac.
1435 fmt & (AFMT_U8 | AFMT_U16_LE)) ?
1436 0x80 : 0, s->dma_dac.dmasize);
1437 } else if (s->dma_dac.count <=
1438 (signed) s->dma_dac.fragsize
1439 && !s->dma_dac.endcleared) {
1440 clear_advance(s->dma_dac.rawbuf,
1441 s->dma_dac.dmasize,
1442 s->dma_dac.swptr,
1443 s->dma_dac.fragsize,
1444 (s->prop_dac.
1445 fmt & (AFMT_U8 |
1446 AFMT_U16_LE)) ? 0x80
1447 : 0);
1448 s->dma_dac.endcleared = 1;
1449 }
1450 if (s->dma_dac.count < (signed) s->dma_dac.dmasize)
1451 wake_up(&s->dma_dac.wait);
1452 }
1453 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1454 "cs4281: cs4281_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1455 (unsigned) s,
1456 s->dma_dac.hwptr,
1457 s->dma_dac.total_bytes,
1458 s->dma_dac.count));
1459 }
1460 }
1461
1462
1463 // ---------------------------------------------------------------------
1464
1465 static void prog_codec(struct cs4281_state *s, unsigned type)
1466 {
1467 unsigned long flags;
1468 unsigned temp1, format;
1469
1470 CS_DBGOUT(CS_FUNCTION, 2,
1471 printk(KERN_INFO "cs4281: prog_codec()+ \n"));
1472
1473 spin_lock_irqsave(&s->lock, flags);
1474 if (type == CS_TYPE_ADC) {
1475 temp1 = readl(s->pBA0 + BA0_DCR1);
1476 writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR1); // Stop capture DMA, if active.
1477
1478 // program sampling rates
1479 // Note, for CS4281, capture & play rates can be set independently.
1480 cs4281_record_rate(s, s->prop_adc.rate);
1481
1482 // program ADC parameters
1483 format = DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE;
1484 if (s->prop_adc.
1485 fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) { // 16-bit
1486 if (s->prop_adc.fmt & (AFMT_S16_BE | AFMT_U16_BE)) // Big-endian?
1487 format |= DMRn_BEND;
1488 if (s->prop_adc.fmt & (AFMT_U16_LE | AFMT_U16_BE))
1489 format |= DMRn_USIGN; // Unsigned.
1490 } else
1491 format |= DMRn_SIZE8 | DMRn_USIGN; // 8-bit, unsigned
1492 if (s->prop_adc.channels < 2)
1493 format |= DMRn_MONO;
1494
1495 writel(format, s->pBA0 + BA0_DMR1);
1496
1497 CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO
1498 "cs4281: prog_codec(): adc %s %s %s rate=%d DMR0 format=0x%.8x\n",
1499 (format & DMRn_SIZE8) ? "8" :
1500 "16",
1501 (format & DMRn_USIGN) ?
1502 "Unsigned" : "Signed",
1503 (format & DMRn_MONO) ? "Mono"
1504 : "Stereo", s->prop_adc.rate,
1505 format));
1506
1507 s->ena &= ~FMODE_READ; // not capturing data yet
1508 }
1509
1510
1511 if (type == CS_TYPE_DAC) {
1512 temp1 = readl(s->pBA0 + BA0_DCR0);
1513 writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR0); // Stop play DMA, if active.
1514
1515 // program sampling rates
1516 // Note, for CS4281, capture & play rates can be set independently.
1517 cs4281_play_rate(s, s->prop_dac.rate);
1518
1519 // program DAC parameters
1520 format = DMRn_DMA | DMRn_AUTO | DMRn_TR_READ;
1521 if (s->prop_dac.
1522 fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) { // 16-bit
1523 if (s->prop_dac.fmt & (AFMT_S16_BE | AFMT_U16_BE))
1524 format |= DMRn_BEND; // Big Endian.
1525 if (s->prop_dac.fmt & (AFMT_U16_LE | AFMT_U16_BE))
1526 format |= DMRn_USIGN; // Unsigned.
1527 } else
1528 format |= DMRn_SIZE8 | DMRn_USIGN; // 8-bit, unsigned
1529
1530 if (s->prop_dac.channels < 2)
1531 format |= DMRn_MONO;
1532
1533 writel(format, s->pBA0 + BA0_DMR0);
1534
1535
1536 CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO
1537 "cs4281: prog_codec(): dac %s %s %s rate=%d DMR0 format=0x%.8x\n",
1538 (format & DMRn_SIZE8) ? "8" :
1539 "16",
1540 (format & DMRn_USIGN) ?
1541 "Unsigned" : "Signed",
1542 (format & DMRn_MONO) ? "Mono"
1543 : "Stereo", s->prop_dac.rate,
1544 format));
1545
1546 s->ena &= ~FMODE_WRITE; // not capturing data yet
1547
1548 }
1549 spin_unlock_irqrestore(&s->lock, flags);
1550 CS_DBGOUT(CS_FUNCTION, 2,
1551 printk(KERN_INFO "cs4281: prog_codec()- \n"));
1552 }
1553
1554
1555 // ---------------------------------------------------------------------
1556
1557 static const char invalid_magic[] =
1558 KERN_CRIT "cs4281: invalid magic value\n";
1559
1560 #define VALIDATE_STATE(s) \
1561 ({ \
1562 if (!(s) || (s)->magic != CS4281_MAGIC) { \
1563 printk(invalid_magic); \
1564 return -ENXIO; \
1565 } \
1566 })
1567
1568 // ---------------------------------------------------------------------
1569
1570
1571 static int mixer_ioctl(struct cs4281_state *s, unsigned int cmd,
1572 unsigned long arg)
1573 {
1574 // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
1575 // Value of array member is recording source Device ID Mask.
1576 static const unsigned int mixer_src[8] = {
1577 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
1578 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
1579 };
1580
1581 // Index of mixtable1[] member is Device ID
1582 // and must be <= SOUND_MIXER_NRDEVICES.
1583 // Value of array member is index into s->mix.vol[]
1584 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
1585 [SOUND_MIXER_PCM] = 1, // voice
1586 [SOUND_MIXER_LINE1] = 2, // AUX
1587 [SOUND_MIXER_CD] = 3, // CD
1588 [SOUND_MIXER_LINE] = 4, // Line
1589 [SOUND_MIXER_SYNTH] = 5, // FM
1590 [SOUND_MIXER_MIC] = 6, // Mic
1591 [SOUND_MIXER_SPEAKER] = 7, // Speaker
1592 [SOUND_MIXER_RECLEV] = 8, // Recording level
1593 [SOUND_MIXER_VOLUME] = 9 // Master Volume
1594 };
1595
1596
1597 static const unsigned mixreg[] = {
1598 BA0_AC97_PCM_OUT_VOLUME,
1599 BA0_AC97_AUX_VOLUME,
1600 BA0_AC97_CD_VOLUME,
1601 BA0_AC97_LINE_IN_VOLUME
1602 };
1603 unsigned char l, r, rl, rr, vidx;
1604 unsigned char attentbl[11] =
1605 { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
1606 unsigned temp1;
1607 int i, val;
1608
1609 VALIDATE_STATE(s);
1610 CS_DBGOUT(CS_FUNCTION, 4,
1611 printk(KERN_INFO
1612 "cs4281: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n",
1613 (unsigned) s, cmd));
1614 #if CSDEBUG
1615 printioctl(cmd);
1616 #endif
1617 #if CSDEBUG_INTERFACE
1618
1619 if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
1620 (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
1621 (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
1622 (cmd == SOUND_MIXER_CS_SETDBGLEVEL)) {
1623 switch (cmd) {
1624
1625 case SOUND_MIXER_CS_GETDBGMASK:
1626 return put_user(cs_debugmask,
1627 (unsigned long *) arg);
1628
1629 case SOUND_MIXER_CS_GETDBGLEVEL:
1630 return put_user(cs_debuglevel,
1631 (unsigned long *) arg);
1632
1633 case SOUND_MIXER_CS_SETDBGMASK:
1634 if (get_user(val, (unsigned long *) arg))
1635 return -EFAULT;
1636 cs_debugmask = val;
1637 return 0;
1638
1639 case SOUND_MIXER_CS_SETDBGLEVEL:
1640 if (get_user(val, (unsigned long *) arg))
1641 return -EFAULT;
1642 cs_debuglevel = val;
1643 return 0;
1644 default:
1645 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
1646 "cs4281: mixer_ioctl(): ERROR unknown debug cmd\n"));
1647 return 0;
1648 }
1649 }
1650 #endif
1651
1652 if (cmd == SOUND_MIXER_PRIVATE1) {
1653 // enable/disable/query mixer preamp
1654 if (get_user(val, (int *) arg))
1655 return -EFAULT;
1656 if (val != -1) {
1657 cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
1658 temp1 = val ? (temp1 | 0x40) : (temp1 & 0xffbf);
1659 cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1);
1660 }
1661 cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
1662 val = (temp1 & 0x40) ? 1 : 0;
1663 return put_user(val, (int *) arg);
1664 }
1665 if (cmd == SOUND_MIXER_PRIVATE2) {
1666 // enable/disable/query spatializer
1667 if (get_user(val, (int *) arg))
1668 return -EFAULT;
1669 if (val != -1) {
1670 temp1 = (val & 0x3f) >> 2;
1671 cs4281_write_ac97(s, BA0_AC97_3D_CONTROL, temp1);
1672 cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE,
1673 &temp1);
1674 cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE,
1675 temp1 | 0x2000);
1676 }
1677 cs4281_read_ac97(s, BA0_AC97_3D_CONTROL, &temp1);
1678 return put_user((temp1 << 2) | 3, (int *) arg);
1679 }
1680 if (cmd == SOUND_MIXER_INFO) {
1681 mixer_info info;
1682 strncpy(info.id, "CS4281", sizeof(info.id));
1683 strncpy(info.name, "Crystal CS4281", sizeof(info.name));
1684 info.modify_counter = s->mix.modcnt;
1685 if (copy_to_user((void *) arg, &info, sizeof(info)))
1686 return -EFAULT;
1687 return 0;
1688 }
1689 if (cmd == SOUND_OLD_MIXER_INFO) {
1690 _old_mixer_info info;
1691 strncpy(info.id, "CS4281", sizeof(info.id));
1692 strncpy(info.name, "Crystal CS4281", sizeof(info.name));
1693 if (copy_to_user((void *) arg, &info, sizeof(info)))
1694 return -EFAULT;
1695 return 0;
1696 }
1697 if (cmd == OSS_GETVERSION)
1698 return put_user(SOUND_VERSION, (int *) arg);
1699
1700 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1701 return -EINVAL;
1702
1703 // If ioctl has only the SIOC_READ bit(bit 31)
1704 // on, process the only-read commands.
1705 if (_SIOC_DIR(cmd) == _SIOC_READ) {
1706 switch (_IOC_NR(cmd)) {
1707 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
1708 cs4281_read_ac97(s, BA0_AC97_RECORD_SELECT,
1709 &temp1);
1710 return put_user(mixer_src[temp1 & 7], (int *) arg);
1711
1712 case SOUND_MIXER_DEVMASK: // Arg contains a bit for each supported device
1713 return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH |
1714 SOUND_MASK_CD | SOUND_MASK_LINE |
1715 SOUND_MASK_LINE1 | SOUND_MASK_MIC |
1716 SOUND_MASK_VOLUME |
1717 SOUND_MASK_RECLEV |
1718 SOUND_MASK_SPEAKER, (int *) arg);
1719
1720 case SOUND_MIXER_RECMASK: // Arg contains a bit for each supported recording source
1721 return put_user(SOUND_MASK_LINE | SOUND_MASK_MIC |
1722 SOUND_MASK_CD | SOUND_MASK_VOLUME |
1723 SOUND_MASK_LINE1, (int *) arg);
1724
1725 case SOUND_MIXER_STEREODEVS: // Mixer channels supporting stereo
1726 return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH |
1727 SOUND_MASK_CD | SOUND_MASK_LINE |
1728 SOUND_MASK_LINE1 | SOUND_MASK_MIC |
1729 SOUND_MASK_VOLUME |
1730 SOUND_MASK_RECLEV, (int *) arg);
1731
1732 case SOUND_MIXER_CAPS:
1733 return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg);
1734
1735 default:
1736 i = _IOC_NR(cmd);
1737 if (i >= SOUND_MIXER_NRDEVICES
1738 || !(vidx = mixtable1[i]))
1739 return -EINVAL;
1740 return put_user(s->mix.vol[vidx - 1], (int *) arg);
1741 }
1742 }
1743 // If ioctl doesn't have both the SIOC_READ and
1744 // the SIOC_WRITE bit set, return invalid.
1745 if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
1746 return -EINVAL;
1747
1748 // Increment the count of volume writes.
1749 s->mix.modcnt++;
1750
1751 // Isolate the command; it must be a write.
1752 switch (_IOC_NR(cmd)) {
1753
1754 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
1755 if (get_user(val, (int *) arg))
1756 return -EFAULT;
1757 i = hweight32(val); // i = # bits on in val.
1758 if (i != 1) // One & only 1 bit must be on.
1759 return 0;
1760 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
1761 if (val == mixer_src[i]) {
1762 temp1 = (i << 8) | i;
1763 cs4281_write_ac97(s,
1764 BA0_AC97_RECORD_SELECT,
1765 temp1);
1766 return 0;
1767 }
1768 }
1769 return 0;
1770
1771 case SOUND_MIXER_VOLUME:
1772 if (get_user(val, (int *) arg))
1773 return -EFAULT;
1774 l = val & 0xff;
1775 if (l > 100)
1776 l = 100; // Max soundcard.h vol is 100.
1777 if (l < 6) {
1778 rl = 63;
1779 l = 0;
1780 } else
1781 rl = attentbl[(10 * l) / 100]; // Convert 0-100 vol to 63-0 atten.
1782
1783 r = (val >> 8) & 0xff;
1784 if (r > 100)
1785 r = 100; // Max right volume is 100, too
1786 if (r < 6) {
1787 rr = 63;
1788 r = 0;
1789 } else
1790 rr = attentbl[(10 * r) / 100]; // Convert volume to attenuation.
1791
1792 if ((rl > 60) && (rr > 60)) // If both l & r are 'low',
1793 temp1 = 0x8000; // turn on the mute bit.
1794 else
1795 temp1 = 0;
1796
1797 temp1 |= (rl << 8) | rr;
1798
1799 cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME, temp1);
1800 cs4281_write_ac97(s, BA0_AC97_HEADPHONE_VOLUME, temp1);
1801
1802 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1803 s->mix.vol[8] = ((unsigned int) r << 8) | l;
1804 #else
1805 s->mix.vol[8] = val;
1806 #endif
1807 return put_user(s->mix.vol[8], (int *) arg);
1808
1809 case SOUND_MIXER_SPEAKER:
1810 if (get_user(val, (int *) arg))
1811 return -EFAULT;
1812 l = val & 0xff;
1813 if (l > 100)
1814 l = 100;
1815 if (l < 3) {
1816 rl = 0;
1817 l = 0;
1818 } else {
1819 rl = (l * 2 - 5) / 13; // Convert 0-100 range to 0-15.
1820 l = (rl * 13 + 5) / 2;
1821 }
1822
1823 if (rl < 3) {
1824 temp1 = 0x8000;
1825 rl = 0;
1826 } else
1827 temp1 = 0;
1828 rl = 15 - rl; // Convert volume to attenuation.
1829 temp1 |= rl << 1;
1830 cs4281_write_ac97(s, BA0_AC97_PC_BEEP_VOLUME, temp1);
1831
1832 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1833 s->mix.vol[6] = l << 8;
1834 #else
1835 s->mix.vol[6] = val;
1836 #endif
1837 return put_user(s->mix.vol[6], (int *) arg);
1838
1839 case SOUND_MIXER_RECLEV:
1840 if (get_user(val, (int *) arg))
1841 return -EFAULT;
1842 l = val & 0xff;
1843 if (l > 100)
1844 l = 100;
1845 r = (val >> 8) & 0xff;
1846 if (r > 100)
1847 r = 100;
1848 rl = (l * 2 - 5) / 13; // Convert 0-100 scale to 0-15.
1849 rr = (r * 2 - 5) / 13;
1850 if (rl < 3 && rr < 3)
1851 temp1 = 0x8000;
1852 else
1853 temp1 = 0;
1854
1855 temp1 = temp1 | (rl << 8) | rr;
1856 cs4281_write_ac97(s, BA0_AC97_RECORD_GAIN, temp1);
1857
1858 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1859 s->mix.vol[7] = ((unsigned int) r << 8) | l;
1860 #else
1861 s->mix.vol[7] = val;
1862 #endif
1863 return put_user(s->mix.vol[7], (int *) arg);
1864
1865 case SOUND_MIXER_MIC:
1866 if (get_user(val, (int *) arg))
1867 return -EFAULT;
1868 l = val & 0xff;
1869 if (l > 100)
1870 l = 100;
1871 if (l < 1) {
1872 l = 0;
1873 rl = 0;
1874 } else {
1875 rl = ((unsigned) l * 5 - 4) / 16; // Convert 0-100 range to 0-31.
1876 l = (rl * 16 + 4) / 5;
1877 }
1878 cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
1879 temp1 &= 0x40; // Isolate 20db gain bit.
1880 if (rl < 3) {
1881 temp1 |= 0x8000;
1882 rl = 0;
1883 }
1884 rl = 31 - rl; // Convert volume to attenuation.
1885 temp1 |= rl;
1886 cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1);
1887
1888 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1889 s->mix.vol[5] = val << 8;
1890 #else
1891 s->mix.vol[5] = val;
1892 #endif
1893 return put_user(s->mix.vol[5], (int *) arg);
1894
1895
1896 case SOUND_MIXER_SYNTH:
1897 if (get_user(val, (int *) arg))
1898 return -EFAULT;
1899 l = val & 0xff;
1900 if (l > 100)
1901 l = 100;
1902 if (get_user(val, (int *) arg))
1903 return -EFAULT;
1904 r = (val >> 8) & 0xff;
1905 if (r > 100)
1906 r = 100;
1907 rl = (l * 2 - 11) / 3; // Convert 0-100 range to 0-63.
1908 rr = (r * 2 - 11) / 3;
1909 if (rl < 3) // If l is low, turn on
1910 temp1 = 0x0080; // the mute bit.
1911 else
1912 temp1 = 0;
1913
1914 rl = 63 - rl; // Convert vol to attenuation.
1915 writel(temp1 | rl, s->pBA0 + BA0_FMLVC);
1916 if (rr < 3) // If rr is low, turn on
1917 temp1 = 0x0080; // the mute bit.
1918 else
1919 temp1 = 0;
1920 rr = 63 - rr; // Convert vol to attenuation.
1921 writel(temp1 | rr, s->pBA0 + BA0_FMRVC);
1922
1923 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1924 s->mix.vol[4] = (r << 8) | l;
1925 #else
1926 s->mix.vol[4] = val;
1927 #endif
1928 return put_user(s->mix.vol[4], (int *) arg);
1929
1930
1931 default:
1932 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1933 "cs4281: mixer_ioctl(): default\n"));
1934
1935 i = _IOC_NR(cmd);
1936 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
1937 return -EINVAL;
1938 if (get_user(val, (int *) arg))
1939 return -EFAULT;
1940 l = val & 0xff;
1941 if (l > 100)
1942 l = 100;
1943 if (l < 1) {
1944 l = 0;
1945 rl = 31;
1946 } else
1947 rl = (attentbl[(l * 10) / 100]) >> 1;
1948
1949 r = (val >> 8) & 0xff;
1950 if (r > 100)
1951 r = 100;
1952 if (r < 1) {
1953 r = 0;
1954 rr = 31;
1955 } else
1956 rr = (attentbl[(r * 10) / 100]) >> 1;
1957 if ((rl > 30) && (rr > 30))
1958 temp1 = 0x8000;
1959 else
1960 temp1 = 0;
1961 temp1 = temp1 | (rl << 8) | rr;
1962 cs4281_write_ac97(s, mixreg[vidx - 1], temp1);
1963
1964 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1965 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
1966 #else
1967 s->mix.vol[vidx - 1] = val;
1968 #endif
1969 return put_user(s->mix.vol[vidx - 1], (int *) arg);
1970 }
1971 }
1972
1973
1974 // ---------------------------------------------------------------------
1975
1976 static loff_t cs4281_llseek(struct file *file, loff_t offset, int origin)
1977 {
1978 return -ESPIPE;
1979 }
1980
1981
1982 // ---------------------------------------------------------------------
1983
1984 static int cs4281_open_mixdev(struct inode *inode, struct file *file)
1985 {
1986 int minor = MINOR(inode->i_rdev);
1987 struct cs4281_state *s = devs;
1988
1989 while (s && s->dev_mixer != minor)
1990 s = s->next;
1991 if (!s)
1992 return -ENODEV;
1993 VALIDATE_STATE(s);
1994 file->private_data = s;
1995 MOD_INC_USE_COUNT;
1996 return 0;
1997 }
1998
1999
2000 static int cs4281_release_mixdev(struct inode *inode, struct file *file)
2001 {
2002 struct cs4281_state *s =
2003 (struct cs4281_state *) file->private_data;
2004
2005 VALIDATE_STATE(s);
2006 MOD_DEC_USE_COUNT;
2007 return 0;
2008 }
2009
2010
2011 static int cs4281_ioctl_mixdev(struct inode *inode, struct file *file,
2012 unsigned int cmd, unsigned long arg)
2013 {
2014 return mixer_ioctl((struct cs4281_state *) file->private_data, cmd,
2015 arg);
2016 }
2017
2018
2019 // ******************************************************************************************
2020 // Mixer file operations struct.
2021 // ******************************************************************************************
2022 static /*const */ struct file_operations cs4281_mixer_fops = {
2023 llseek:cs4281_llseek,
2024 ioctl:cs4281_ioctl_mixdev,
2025 open:cs4281_open_mixdev,
2026 release:cs4281_release_mixdev,
2027 };
2028
2029 // ---------------------------------------------------------------------
2030
2031
2032 static int drain_adc(struct cs4281_state *s, int nonblock)
2033 {
2034 DECLARE_WAITQUEUE(wait, current);
2035 unsigned long flags;
2036 int count;
2037 unsigned tmo;
2038
2039 if (s->dma_adc.mapped)
2040 return 0;
2041 add_wait_queue(&s->dma_adc.wait, &wait);
2042 for (;;) {
2043 set_current_state(TASK_INTERRUPTIBLE);
2044 spin_lock_irqsave(&s->lock, flags);
2045 count = s->dma_adc.count;
2046 CS_DBGOUT(CS_FUNCTION, 2,
2047 printk(KERN_INFO "cs4281: drain_adc() %d\n",
2048 count));
2049 spin_unlock_irqrestore(&s->lock, flags);
2050 if (count <= 0) {
2051 CS_DBGOUT(CS_FUNCTION, 2,
2052 printk(KERN_INFO
2053 "cs4281: drain_adc() count<0\n"));
2054 break;
2055 }
2056 if (signal_pending(current))
2057 break;
2058 if (nonblock) {
2059 remove_wait_queue(&s->dma_adc.wait, &wait);
2060 current->state = TASK_RUNNING;
2061 return -EBUSY;
2062 }
2063 tmo =
2064 3 * HZ * (count +
2065 s->dma_adc.fragsize) / 2 / s->prop_adc.rate;
2066 if (s->prop_adc.fmt & (AFMT_S16_LE | AFMT_U16_LE))
2067 tmo >>= 1;
2068 if (s->prop_adc.channels > 1)
2069 tmo >>= 1;
2070 if (!schedule_timeout(tmo + 1))
2071 printk(KERN_DEBUG "cs4281: dma timed out??\n");
2072 }
2073 remove_wait_queue(&s->dma_adc.wait, &wait);
2074 current->state = TASK_RUNNING;
2075 if (signal_pending(current))
2076 return -ERESTARTSYS;
2077 return 0;
2078 }
2079
2080 static int drain_dac(struct cs4281_state *s, int nonblock)
2081 {
2082 DECLARE_WAITQUEUE(wait, current);
2083 unsigned long flags;
2084 int count;
2085 unsigned tmo;
2086
2087 if (s->dma_dac.mapped)
2088 return 0;
2089 add_wait_queue(&s->dma_dac.wait, &wait);
2090 for (;;) {
2091 set_current_state(TASK_INTERRUPTIBLE);
2092 spin_lock_irqsave(&s->lock, flags);
2093 count = s->dma_dac.count;
2094 spin_unlock_irqrestore(&s->lock, flags);
2095 if (count <= 0)
2096 break;
2097 if (signal_pending(current))
2098 break;
2099 if (nonblock) {
2100 remove_wait_queue(&s->dma_dac.wait, &wait);
2101 current->state = TASK_RUNNING;
2102 return -EBUSY;
2103 }
2104 tmo =
2105 3 * HZ * (count +
2106 s->dma_dac.fragsize) / 2 / s->prop_dac.rate;
2107 if (s->prop_dac.fmt & (AFMT_S16_LE | AFMT_U16_LE))
2108 tmo >>= 1;
2109 if (s->prop_dac.channels > 1)
2110 tmo >>= 1;
2111 if (!schedule_timeout(tmo + 1))
2112 printk(KERN_DEBUG "cs4281: dma timed out??\n");
2113 }
2114 remove_wait_queue(&s->dma_dac.wait, &wait);
2115 current->state = TASK_RUNNING;
2116 if (signal_pending(current))
2117 return -ERESTARTSYS;
2118 return 0;
2119 }
2120
2121 //****************************************************************************
2122 //
2123 // CopySamples copies 16-bit stereo samples from the source to the
2124 // destination, possibly converting down to either 8-bit or mono or both.
2125 // count specifies the number of output bytes to write.
2126 //
2127 // Arguments:
2128 //
2129 // dst - Pointer to a destination buffer.
2130 // src - Pointer to a source buffer
2131 // count - The number of bytes to copy into the destination buffer.
2132 // iChannels - Stereo - 2
2133 // Mono - 1
2134 // fmt - AFMT_xxx (soundcard.h formats)
2135 //
2136 // NOTES: only call this routine for conversion to 8bit from 16bit
2137 //
2138 //****************************************************************************
2139 static void CopySamples(char *dst, char *src, int count, int iChannels,
2140 unsigned fmt)
2141 {
2142
2143 unsigned short *psSrc;
2144 long lAudioSample;
2145
2146 CS_DBGOUT(CS_FUNCTION, 2,
2147 printk(KERN_INFO "cs4281: CopySamples()+ "));
2148 CS_DBGOUT(CS_WAVE_READ, 8,
2149 printk(KERN_INFO
2150 " dst=0x%x src=0x%x count=%d iChannels=%d fmt=0x%x\n",
2151 (unsigned) dst, (unsigned) src, (unsigned) count,
2152 (unsigned) iChannels, (unsigned) fmt));
2153
2154 // Gershwin does format conversion in hardware so normally
2155 // we don't do any host based coversion. The data formatter
2156 // truncates 16 bit data to 8 bit and that causes some hiss.
2157 // We have already forced the HW to do 16 bit sampling and
2158 // 2 channel so that we can use software to round instead
2159 // of truncate
2160
2161 //
2162 // See if the data should be output as 8-bit unsigned stereo.
2163 //
2164 if ((iChannels == 2) && (fmt & AFMT_U8)) {
2165 //
2166 // Convert each 16-bit unsigned stereo sample to 8-bit unsigned
2167 // stereo using rounding.
2168 //
2169 psSrc = (unsigned short *) src;
2170 count = count / 2;
2171 while (count--) {
2172 lAudioSample = (long) psSrc[count] + (long) 0x80;
2173 if (lAudioSample > 0xffff) {
2174 lAudioSample = 0xffff;
2175 }
2176 dst[count] = (char) (lAudioSample >> 8);
2177 }
2178 }
2179 //
2180 // check for 8-bit signed stereo.
2181 //
2182 else if ((iChannels == 2) && (fmt & AFMT_S8)) {
2183 //
2184 // Convert each 16-bit stereo sample to 8-bit stereo using rounding.
2185 //
2186 psSrc = (short *) src;
2187 while (count--) {
2188 lAudioSample =
2189 (((long) psSrc[0] + (long) psSrc[1]) / 2);
2190 psSrc += 2;
2191 *dst++ = (char) ((short) lAudioSample >> 8);
2192 }
2193 }
2194 //
2195 // See if the data should be output at 8-bit unsigned mono.
2196 //
2197 else if ((iChannels == 1) && (fmt & AFMT_U8)) {
2198 //
2199 // Convert each 16-bit unsigned mono sample to 8-bit unsigned
2200 // mono using rounding.
2201 //
2202
2203 psSrc = (short *) src;
2204 while (count--) {
2205 lAudioSample = (long) *psSrc++ + (long) 0x80;
2206 if (lAudioSample > 0x7fff) {
2207 lAudioSample = 0x7fff;
2208 }
2209 //
2210 // Convert Signed to Unsigned.
2211 //
2212
2213 *dst++ =
2214 (unsigned
2215 char) (((short) lAudioSample +
2216 (short) 0x8000) >> 8);
2217 }
2218 }
2219 //
2220 // Otherwise, the data should be output as 8-bit signed mono.
2221 //
2222 else if ((iChannels == 1) && (fmt & AFMT_S8)) {
2223 //
2224 // Convert each 16-bit signed mono sample to 8-bit signed mono
2225 // using rounding.
2226 //
2227 psSrc = (short *) src;
2228 while (count--) {
2229 lAudioSample =
2230 (((long) psSrc[0] + (long) psSrc[1]) / 2);
2231 if (lAudioSample > 0x7fff) {
2232 lAudioSample = 0x7fff;
2233 }
2234 psSrc += 2;
2235 *dst++ = (char) ((short) lAudioSample >> 8);
2236 }
2237 }
2238 }
2239
2240 //
2241 // cs_copy_to_user()
2242 // replacement for the standard copy_to_user, to allow for a conversion from
2243 // 16 bit to 8 bit if the record conversion is active. the cs4281 has some
2244 // issues with 8 bit capture, so the driver always captures data in 16 bit
2245 // and then if the user requested 8 bit, converts from 16 to 8 bit.
2246 //
2247 static unsigned cs_copy_to_user(struct cs4281_state *s, void *dest,
2248 unsigned *hwsrc, unsigned cnt,
2249 unsigned *copied)
2250 {
2251 void *src = hwsrc; //default to the standard destination buffer addr
2252
2253 CS_DBGOUT(CS_FUNCTION, 6, printk(KERN_INFO
2254 "cs_copy_to_user()+ fmt=0x%x fmt_o=0x%x cnt=%d dest=0x%.8x\n",
2255 s->prop_adc.fmt,
2256 s->prop_adc.fmt_original,
2257 (unsigned) cnt, (unsigned) dest));
2258
2259 if (cnt > s->dma_adc.dmasize) {
2260 cnt = s->dma_adc.dmasize;
2261 }
2262 if (!cnt) {
2263 *copied = 0;
2264 return 0;
2265 }
2266 if (s->conversion) {
2267 if (!s->tmpbuff) {
2268 *copied = cnt / 2;
2269 return 0;
2270 }
2271 CopySamples(s->tmpbuff, (void *) hwsrc, cnt,
2272 (unsigned) s->prop_adc.channels,
2273 s->prop_adc.fmt_original);
2274 src = s->tmpbuff;
2275 cnt = cnt / 2;
2276 }
2277
2278 if (copy_to_user(dest, src, cnt)) {
2279 *copied = 0;
2280 return -EFAULT;
2281 }
2282 *copied = cnt;
2283 CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_INFO
2284 "cs4281: cs_copy_to_user()- copied bytes is %d \n",
2285 cnt));
2286 return 0;
2287 }
2288
2289 // ---------------------------------------------------------------------
2290
2291 static ssize_t cs4281_read(struct file *file, char *buffer, size_t count,
2292 loff_t * ppos)
2293 {
2294 struct cs4281_state *s =
2295 (struct cs4281_state *) file->private_data;
2296 ssize_t ret;
2297 unsigned long flags;
2298 unsigned swptr;
2299 int cnt;
2300 unsigned copied = 0;
2301
2302 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
2303 printk(KERN_INFO "cs4281: cs4281_read()+ %d \n", count));
2304
2305 VALIDATE_STATE(s);
2306 if (ppos != &file->f_pos)
2307 return -ESPIPE;
2308 if (s->dma_adc.mapped)
2309 return -ENXIO;
2310 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
2311 return ret;
2312 if (!access_ok(VERIFY_WRITE, buffer, count))
2313 return -EFAULT;
2314 ret = 0;
2315 //
2316 // "count" is the amount of bytes to read (from app), is decremented each loop
2317 // by the amount of bytes that have been returned to the user buffer.
2318 // "cnt" is the running total of each read from the buffer (changes each loop)
2319 // "buffer" points to the app's buffer
2320 // "ret" keeps a running total of the amount of bytes that have been copied
2321 // to the user buffer.
2322 // "copied" is the total bytes copied into the user buffer for each loop.
2323 //
2324 while (count > 0) {
2325 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
2326 "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n",
2327 count, s->dma_adc.count,
2328 s->dma_adc.swptr,
2329 s->dma_adc.hwptr));
2330 spin_lock_irqsave(&s->lock, flags);
2331
2332 // get the current copy point of the sw buffer
2333 swptr = s->dma_adc.swptr;
2334
2335 // cnt is the amount of unread bytes from the end of the
2336 // hw buffer to the current sw pointer
2337 cnt = s->dma_adc.dmasize - swptr;
2338
2339 // dma_adc.count is the current total bytes that have not been read.
2340 // if the amount of unread bytes from the current sw pointer to the
2341 // end of the buffer is greater than the current total bytes that
2342 // have not been read, then set the "cnt" (unread bytes) to the
2343 // amount of unread bytes.
2344
2345 if (s->dma_adc.count < cnt)
2346 cnt = s->dma_adc.count;
2347 spin_unlock_irqrestore(&s->lock, flags);
2348 //
2349 // if we are converting from 8/16 then we need to copy
2350 // twice the number of 16 bit bytes then 8 bit bytes.
2351 //
2352 if (s->conversion) {
2353 if (cnt > (count * 2))
2354 cnt = (count * 2);
2355 } else {
2356 if (cnt > count)
2357 cnt = count;
2358 }
2359 //
2360 // "cnt" NOW is the smaller of the amount that will be read,
2361 // and the amount that is requested in this read (or partial).
2362 // if there are no bytes in the buffer to read, then start the
2363 // ADC and wait for the interrupt handler to wake us up.
2364 //
2365 if (cnt <= 0) {
2366
2367 // start up the dma engine and then continue back to the top of
2368 // the loop when wake up occurs.
2369 start_adc(s);
2370 if (file->f_flags & O_NONBLOCK)
2371 return ret ? ret : -EAGAIN;
2372 interruptible_sleep_on(&s->dma_adc.wait);
2373 if (signal_pending(current))
2374 return ret ? ret : -ERESTARTSYS;
2375 continue;
2376 }
2377 // there are bytes in the buffer to read.
2378 // copy from the hw buffer over to the user buffer.
2379 // user buffer is designated by "buffer"
2380 // virtual address to copy from is rawbuf+swptr
2381 // the "cnt" is the number of bytes to read.
2382
2383 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
2384 "_read() copy_to cnt=%d count=%d ",
2385 cnt, count));
2386 CS_DBGOUT(CS_WAVE_READ, 8,
2387 printk(KERN_INFO
2388 " .dmasize=%d .count=%d buffer=0x%.8x ret=%d\n",
2389 s->dma_adc.dmasize, s->dma_adc.count,
2390 (unsigned) buffer, ret));
2391
2392 if (cs_copy_to_user
2393 (s, buffer, s->dma_adc.rawbuf + swptr, cnt, &copied))
2394 return ret ? ret : -EFAULT;
2395 swptr = (swptr + cnt) % s->dma_adc.dmasize;
2396 spin_lock_irqsave(&s->lock, flags);
2397 s->dma_adc.swptr = swptr;
2398 s->dma_adc.count -= cnt;
2399 spin_unlock_irqrestore(&s->lock, flags);
2400 count -= copied;
2401 buffer += copied;
2402 ret += copied;
2403 start_adc(s);
2404 }
2405 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
2406 printk(KERN_INFO "cs4281: cs4281_read()- %d\n", ret));
2407 return ret;
2408 }
2409
2410
2411 static ssize_t cs4281_write(struct file *file, const char *buffer,
2412 size_t count, loff_t * ppos)
2413 {
2414 struct cs4281_state *s =
2415 (struct cs4281_state *) file->private_data;
2416 ssize_t ret;
2417 unsigned long flags;
2418 unsigned swptr;
2419 int cnt;
2420
2421 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
2422 printk(KERN_INFO "cs4281: cs4281_write()+ count=%d\n",
2423 count));
2424 VALIDATE_STATE(s);
2425
2426 if (ppos != &file->f_pos)
2427 return -ESPIPE;
2428 if (s->dma_dac.mapped)
2429 return -ENXIO;
2430 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
2431 return ret;
2432 if (!access_ok(VERIFY_READ, buffer, count))
2433 return -EFAULT;
2434 ret = 0;
2435 while (count > 0) {
2436 spin_lock_irqsave(&s->lock, flags);
2437 if (s->dma_dac.count < 0) {
2438 s->dma_dac.count = 0;
2439 s->dma_dac.swptr = s->dma_dac.hwptr;
2440 }
2441 swptr = s->dma_dac.swptr;
2442 cnt = s->dma_dac.dmasize - swptr;
2443 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
2444 cnt = s->dma_dac.dmasize - s->dma_dac.count;
2445 spin_unlock_irqrestore(&s->lock, flags);
2446 if (cnt > count)
2447 cnt = count;
2448 if (cnt <= 0) {
2449
2450 start_dac(s);
2451 if (file->f_flags & O_NONBLOCK)
2452 return ret ? ret : -EAGAIN;
2453 interruptible_sleep_on(&s->dma_dac.wait);
2454 if (signal_pending(current))
2455 return ret ? ret : -ERESTARTSYS;
2456 continue;
2457 }
2458 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt))
2459 return ret ? ret : -EFAULT;
2460 swptr = (swptr + cnt) % s->dma_dac.dmasize;
2461 spin_lock_irqsave(&s->lock, flags);
2462 s->dma_dac.swptr = swptr;
2463 s->dma_dac.count += cnt;
2464 s->dma_dac.endcleared = 0;
2465 spin_unlock_irqrestore(&s->lock, flags);
2466 count -= cnt;
2467 buffer += cnt;
2468 ret += cnt;
2469 start_dac(s);
2470 }
2471 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
2472 printk(KERN_INFO "cs4281: cs4281_write()- %d\n", ret));
2473 return ret;
2474 }
2475
2476
2477 static unsigned int cs4281_poll(struct file *file,
2478 struct poll_table_struct *wait)
2479 {
2480 struct cs4281_state *s =
2481 (struct cs4281_state *) file->private_data;
2482 unsigned long flags;
2483 unsigned int mask = 0;
2484
2485 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
2486 printk(KERN_INFO "cs4281: cs4281_poll()+\n"));
2487 VALIDATE_STATE(s);
2488 if (file->f_mode & FMODE_WRITE) {
2489 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
2490 printk(KERN_INFO
2491 "cs4281: cs4281_poll() wait on FMODE_WRITE\n"));
2492 poll_wait(file, &s->dma_dac.wait, wait);
2493 }
2494 if (file->f_mode & FMODE_READ) {
2495 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
2496 printk(KERN_INFO
2497 "cs4281: cs4281_poll() wait on FMODE_READ\n"));
2498 poll_wait(file, &s->dma_adc.wait, wait);
2499 }
2500 spin_lock_irqsave(&s->lock, flags);
2501 cs4281_update_ptr(s);
2502 if (file->f_mode & FMODE_WRITE) {
2503 if (s->dma_dac.mapped) {
2504 if (s->dma_dac.count >=
2505 (signed) s->dma_dac.fragsize) {
2506 if (s->dma_dac.wakeup)
2507 mask |= POLLOUT | POLLWRNORM;
2508 else
2509 mask = 0;
2510 s->dma_dac.wakeup = 0;
2511 }
2512 } else {
2513 if ((signed) s->dma_dac.dmasize > s->dma_dac.count)
2514 mask |= POLLOUT | POLLWRNORM;
2515 }
2516 } else if (file->f_mode & FMODE_READ) {
2517 if (s->dma_adc.mapped) {
2518 if (s->dma_adc.count >=
2519 (signed) s->dma_adc.fragsize) mask |=
2520 POLLIN | POLLRDNORM;
2521 } else {
2522 if (s->dma_adc.count > 0)
2523 mask |= POLLIN | POLLRDNORM;
2524 }
2525 }
2526 spin_unlock_irqrestore(&s->lock, flags);
2527 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
2528 printk(KERN_INFO "cs4281: cs4281_poll()- 0x%.8x\n",
2529 mask));
2530 return mask;
2531 }
2532
2533
2534 static int cs4281_mmap(struct file *file, struct vm_area_struct *vma)
2535 {
2536 struct cs4281_state *s =
2537 (struct cs4281_state *) file->private_data;
2538 struct dmabuf *db;
2539 int ret;
2540 unsigned long size;
2541
2542 CS_DBGOUT(CS_FUNCTION | CS_PARMS | CS_OPEN, 4,
2543 printk(KERN_INFO "cs4281: cs4281_mmap()+\n"));
2544
2545 VALIDATE_STATE(s);
2546 if (vma->vm_flags & VM_WRITE) {
2547 if ((ret = prog_dmabuf_dac(s)) != 0)
2548 return ret;
2549 db = &s->dma_dac;
2550 } else if (vma->vm_flags & VM_READ) {
2551 if ((ret = prog_dmabuf_adc(s)) != 0)
2552 return ret;
2553 db = &s->dma_adc;
2554 } else
2555 return -EINVAL;
2556 //
2557 // only support PLAYBACK for now
2558 //
2559 db = &s->dma_dac;
2560
2561 if (vma->vm_pgoff != 0)
2562 return -EINVAL;
2563 size = vma->vm_end - vma->vm_start;
2564 if (size > (PAGE_SIZE << db->buforder))
2565 return -EINVAL;
2566 if (remap_page_range
2567 (vma->vm_start, virt_to_phys(db->rawbuf), size,
2568 vma->vm_page_prot)) return -EAGAIN;
2569 db->mapped = 1;
2570
2571 CS_DBGOUT(CS_FUNCTION | CS_PARMS | CS_OPEN, 4,
2572 printk(KERN_INFO "cs4281: cs4281_mmap()- 0 size=%d\n",
2573 (unsigned) size));
2574
2575 return 0;
2576 }
2577
2578
2579 static int cs4281_ioctl(struct inode *inode, struct file *file,
2580 unsigned int cmd, unsigned long arg)
2581 {
2582 struct cs4281_state *s =
2583 (struct cs4281_state *) file->private_data;
2584 unsigned long flags;
2585 audio_buf_info abinfo;
2586 count_info cinfo;
2587 int val, mapped, ret;
2588
2589 CS_DBGOUT(CS_FUNCTION, 4,
2590 printk(KERN_INFO
2591 "cs4281: cs4281_ioctl(): file=0x%.8x cmd=0x%.8x\n",
2592 (unsigned) file, cmd));
2593 #if CSDEBUG
2594 printioctl(cmd);
2595 #endif
2596 VALIDATE_STATE(s);
2597 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
2598 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
2599 switch (cmd) {
2600 case OSS_GETVERSION:
2601 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2602 "cs4281: cs4281_ioctl(): SOUND_VERSION=0x%.8x\n",
2603 SOUND_VERSION));
2604 return put_user(SOUND_VERSION, (int *) arg);
2605
2606 case SNDCTL_DSP_SYNC:
2607 CS_DBGOUT(CS_IOCTL, 4,
2608 printk(KERN_INFO
2609 "cs4281: cs4281_ioctl(): DSP_SYNC\n"));
2610 if (file->f_mode & FMODE_WRITE)
2611 return drain_dac(s,
2612 0 /*file->f_flags & O_NONBLOCK */
2613 );
2614 return 0;
2615
2616 case SNDCTL_DSP_SETDUPLEX:
2617 return 0;
2618
2619 case SNDCTL_DSP_GETCAPS:
2620 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
2621 DSP_CAP_TRIGGER | DSP_CAP_MMAP,
2622 (int *) arg);
2623
2624 case SNDCTL_DSP_RESET:
2625 CS_DBGOUT(CS_IOCTL, 4,
2626 printk(KERN_INFO
2627 "cs4281: cs4281_ioctl(): DSP_RESET\n"));
2628 if (file->f_mode & FMODE_WRITE) {
2629 stop_dac(s);
2630 synchronize_irq();
2631 s->dma_dac.swptr = s->dma_dac.hwptr =
2632 s->dma_dac.count = s->dma_dac.total_bytes =
2633 s->dma_dac.blocks = s->dma_dac.wakeup = 0;
2634 prog_codec(s, CS_TYPE_DAC);
2635 }
2636 if (file->f_mode & FMODE_READ) {
2637 stop_adc(s);
2638 synchronize_irq();
2639 s->dma_adc.swptr = s->dma_adc.hwptr =
2640 s->dma_adc.count = s->dma_adc.total_bytes =
2641 s->dma_adc.blocks = s->dma_dac.wakeup = 0;
2642 prog_codec(s, CS_TYPE_ADC);
2643 }
2644 return 0;
2645
2646 case SNDCTL_DSP_SPEED:
2647 if (get_user(val, (int *) arg))
2648 return -EFAULT;
2649 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4,
2650 printk(KERN_INFO
2651 "cs4281: cs4281_ioctl(): DSP_SPEED val=%d\n",
2652 val));
2653 //
2654 // support independent capture and playback channels
2655 // assume that the file mode bit determines the
2656 // direction of the data flow.
2657 //
2658 if (file->f_mode & FMODE_READ) {
2659 if (val >= 0) {
2660 stop_adc(s);
2661 s->dma_adc.ready = 0;
2662 // program sampling rates
2663 if (val > 48000)
2664 val = 48000;
2665 if (val < 6300)
2666 val = 6300;
2667 s->prop_adc.rate = val;
2668 prog_codec(s, CS_TYPE_ADC);
2669 }
2670 }
2671 if (file->f_mode & FMODE_WRITE) {
2672 if (val >= 0) {
2673 stop_dac(s);
2674 s->dma_dac.ready = 0;
2675 // program sampling rates
2676 if (val > 48000)
2677 val = 48000;
2678 if (val < 6300)
2679 val = 6300;
2680 s->prop_dac.rate = val;
2681 prog_codec(s, CS_TYPE_DAC);
2682 }
2683 }
2684
2685 if (file->f_mode & FMODE_WRITE)
2686 val = s->prop_dac.rate;
2687 else if (file->f_mode & FMODE_READ)
2688 val = s->prop_adc.rate;
2689
2690 return put_user(val, (int *) arg);
2691
2692 case SNDCTL_DSP_STEREO:
2693 if (get_user(val, (int *) arg))
2694 return -EFAULT;
2695 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4,
2696 printk(KERN_INFO
2697 "cs4281: cs4281_ioctl(): DSP_STEREO val=%d\n",
2698 val));
2699 if (file->f_mode & FMODE_READ) {
2700 stop_adc(s);
2701 s->dma_adc.ready = 0;
2702 s->prop_adc.channels = val ? 2 : 1;
2703 prog_codec(s, CS_TYPE_ADC);
2704 }
2705 if (file->f_mode & FMODE_WRITE) {
2706 stop_dac(s);
2707 s->dma_dac.ready = 0;
2708 s->prop_dac.channels = val ? 2 : 1;
2709 prog_codec(s, CS_TYPE_DAC);
2710 }
2711 return 0;
2712
2713 case SNDCTL_DSP_CHANNELS:
2714 if (get_user(val, (int *) arg))
2715 return -EFAULT;
2716 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4,
2717 printk(KERN_INFO
2718 "cs4281: cs4281_ioctl(): DSP_CHANNELS val=%d\n",
2719 val));
2720 if (val != 0) {
2721 if (file->f_mode & FMODE_READ) {
2722 stop_adc(s);
2723 s->dma_adc.ready = 0;
2724 if (val >= 2)
2725 s->prop_adc.channels = 2;
2726 else
2727 s->prop_adc.channels = 1;
2728 prog_codec(s, CS_TYPE_ADC);
2729 }
2730 if (file->f_mode & FMODE_WRITE) {
2731 stop_dac(s);
2732 s->dma_dac.ready = 0;
2733 if (val >= 2)
2734 s->prop_dac.channels = 2;
2735 else
2736 s->prop_dac.channels = 1;
2737 prog_codec(s, CS_TYPE_DAC);
2738 }
2739 }
2740
2741 if (file->f_mode & FMODE_WRITE)
2742 val = s->prop_dac.channels;
2743 else if (file->f_mode & FMODE_READ)
2744 val = s->prop_adc.channels;
2745
2746 return put_user(val, (int *) arg);
2747
2748 case SNDCTL_DSP_GETFMTS: // Returns a mask
2749 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4,
2750 printk(KERN_INFO
2751 "cs4281: cs4281_ioctl(): DSP_GETFMT val=0x%.8x\n",
2752 AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2753 AFMT_U8));
2754 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2755 AFMT_U8, (int *) arg);
2756
2757 case SNDCTL_DSP_SETFMT:
2758 if (get_user(val, (int *) arg))
2759 return -EFAULT;
2760 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4,
2761 printk(KERN_INFO
2762 "cs4281: cs4281_ioctl(): DSP_SETFMT val=0x%.8x\n",
2763 val));
2764 if (val != AFMT_QUERY) {
2765 if (file->f_mode & FMODE_READ) {
2766 stop_adc(s);
2767 s->dma_adc.ready = 0;
2768 if (val != AFMT_S16_LE
2769 && val != AFMT_U16_LE && val != AFMT_S8
2770 && val != AFMT_U8)
2771 val = AFMT_U8;
2772 s->prop_adc.fmt = val;
2773 s->prop_adc.fmt_original = s->prop_adc.fmt;
2774 prog_codec(s, CS_TYPE_ADC);
2775 }
2776 if (file->f_mode & FMODE_WRITE) {
2777 stop_dac(s);
2778 s->dma_dac.ready = 0;
2779 if (val != AFMT_S16_LE
2780 && val != AFMT_U16_LE && val != AFMT_S8
2781 && val != AFMT_U8)
2782 val = AFMT_U8;
2783 s->prop_dac.fmt = val;
2784 s->prop_dac.fmt_original = s->prop_dac.fmt;
2785 prog_codec(s, CS_TYPE_DAC);
2786 }
2787 } else {
2788 if (file->f_mode & FMODE_WRITE)
2789 val = s->prop_dac.fmt_original;
2790 else if (file->f_mode & FMODE_READ)
2791 val = s->prop_adc.fmt_original;
2792 }
2793 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4,
2794 printk(KERN_INFO
2795 "cs4281: cs4281_ioctl(): DSP_SETFMT return val=0x%.8x\n",
2796 val));
2797 return put_user(val, (int *) arg);
2798
2799 case SNDCTL_DSP_POST:
2800 CS_DBGOUT(CS_IOCTL, 4,
2801 printk(KERN_INFO
2802 "cs4281: cs4281_ioctl(): DSP_POST\n"));
2803 return 0;
2804
2805 case SNDCTL_DSP_GETTRIGGER:
2806 val = 0;
2807 if (file->f_mode & s->ena & FMODE_READ)
2808 val |= PCM_ENABLE_INPUT;
2809 if (file->f_mode & s->ena & FMODE_WRITE)
2810 val |= PCM_ENABLE_OUTPUT;
2811 return put_user(val, (int *) arg);
2812
2813 case SNDCTL_DSP_SETTRIGGER:
2814 if (get_user(val, (int *) arg))
2815 return -EFAULT;
2816 if (file->f_mode & FMODE_READ) {
2817 if (val & PCM_ENABLE_INPUT) {
2818 if (!s->dma_adc.ready
2819 && (ret = prog_dmabuf_adc(s)))
2820 return ret;
2821 start_adc(s);
2822 } else
2823 stop_adc(s);
2824 }
2825 if (file->f_mode & FMODE_WRITE) {
2826 if (val & PCM_ENABLE_OUTPUT) {
2827 if (!s->dma_dac.ready
2828 && (ret = prog_dmabuf_dac(s)))
2829 return ret;
2830 start_dac(s);
2831 } else
2832 stop_dac(s);
2833 }
2834 return 0;
2835
2836 case SNDCTL_DSP_GETOSPACE:
2837 if (!(file->f_mode & FMODE_WRITE))
2838 return -EINVAL;
2839 if (!(s->ena & FMODE_WRITE)
2840 && (val = prog_dmabuf_dac(s)) != 0)
2841 return val;
2842 spin_lock_irqsave(&s->lock, flags);
2843 cs4281_update_ptr(s);
2844 abinfo.fragsize = s->dma_dac.fragsize;
2845 if (s->dma_dac.mapped)
2846 abinfo.bytes = s->dma_dac.dmasize;
2847 else
2848 abinfo.bytes =
2849 s->dma_dac.dmasize - s->dma_dac.count;
2850 abinfo.fragstotal = s->dma_dac.numfrag;
2851 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2852 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
2853 "cs4281: cs4281_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
2854 abinfo.
2855 fragsize,
2856 abinfo.bytes,
2857 abinfo.
2858 fragstotal,
2859 abinfo.
2860 fragments));
2861 spin_unlock_irqrestore(&s->lock, flags);
2862 return copy_to_user((void *) arg, &abinfo,
2863 sizeof(abinfo)) ? -EFAULT : 0;
2864
2865 case SNDCTL_DSP_GETISPACE:
2866 if (!(file->f_mode & FMODE_READ))
2867 return -EINVAL;
2868 if (!(s->ena & FMODE_READ)
2869 && (val = prog_dmabuf_adc(s)) != 0) return val;
2870 spin_lock_irqsave(&s->lock, flags);
2871 cs4281_update_ptr(s);
2872 if (s->conversion) {
2873 abinfo.fragsize = s->dma_adc.fragsize / 2;
2874 abinfo.bytes = s->dma_adc.count / 2;
2875 abinfo.fragstotal = s->dma_adc.numfrag;
2876 abinfo.fragments =
2877 abinfo.bytes >> (s->dma_adc.fragshift - 1);
2878 } else {
2879 abinfo.fragsize = s->dma_adc.fragsize;
2880 abinfo.bytes = s->dma_adc.count;
2881 abinfo.fragstotal = s->dma_adc.numfrag;
2882 abinfo.fragments =
2883 abinfo.bytes >> s->dma_adc.fragshift;
2884 }
2885 spin_unlock_irqrestore(&s->lock, flags);
2886 return copy_to_user((void *) arg, &abinfo,
2887 sizeof(abinfo)) ? -EFAULT : 0;
2888
2889 case SNDCTL_DSP_NONBLOCK:
2890 file->f_flags |= O_NONBLOCK;
2891 return 0;
2892
2893 case SNDCTL_DSP_GETODELAY:
2894 if (!(file->f_mode & FMODE_WRITE))
2895 return -EINVAL;
2896 spin_lock_irqsave(&s->lock, flags);
2897 cs4281_update_ptr(s);
2898 val = s->dma_dac.count;
2899 spin_unlock_irqrestore(&s->lock, flags);
2900 return put_user(val, (int *) arg);
2901
2902 case SNDCTL_DSP_GETIPTR:
2903 if (!(file->f_mode & FMODE_READ))
2904 return -EINVAL;
2905 spin_lock_irqsave(&s->lock, flags);
2906 cs4281_update_ptr(s);
2907 cinfo.bytes = s->dma_adc.total_bytes;
2908 if (s->dma_adc.mapped) {
2909 cinfo.blocks =
2910 (cinfo.bytes >> s->dma_adc.fragshift) -
2911 s->dma_adc.blocks;
2912 s->dma_adc.blocks =
2913 cinfo.bytes >> s->dma_adc.fragshift;
2914 } else {
2915 if (s->conversion) {
2916 cinfo.blocks =
2917 s->dma_adc.count /
2918 2 >> (s->dma_adc.fragshift - 1);
2919 } else
2920 cinfo.blocks =
2921 s->dma_adc.count >> s->dma_adc.
2922 fragshift;
2923 }
2924 if (s->conversion)
2925 cinfo.ptr = s->dma_adc.hwptr / 2;
2926 else
2927 cinfo.ptr = s->dma_adc.hwptr;
2928 if (s->dma_adc.mapped)
2929 s->dma_adc.count &= s->dma_adc.fragsize - 1;
2930 spin_unlock_irqrestore(&s->lock, flags);
2931 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
2932
2933 case SNDCTL_DSP_GETOPTR:
2934 if (!(file->f_mode & FMODE_WRITE))
2935 return -EINVAL;
2936 spin_lock_irqsave(&s->lock, flags);
2937 cs4281_update_ptr(s);
2938 cinfo.bytes = s->dma_dac.total_bytes;
2939 if (s->dma_dac.mapped) {
2940 cinfo.blocks =
2941 (cinfo.bytes >> s->dma_dac.fragshift) -
2942 s->dma_dac.blocks;
2943 s->dma_dac.blocks =
2944 cinfo.bytes >> s->dma_dac.fragshift;
2945 } else {
2946 cinfo.blocks =
2947 s->dma_dac.count >> s->dma_dac.fragshift;
2948 }
2949 cinfo.ptr = s->dma_dac.hwptr;
2950 if (s->dma_dac.mapped)
2951 s->dma_dac.count &= s->dma_dac.fragsize - 1;
2952 spin_unlock_irqrestore(&s->lock, flags);
2953 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
2954
2955 case SNDCTL_DSP_GETBLKSIZE:
2956 if (file->f_mode & FMODE_WRITE) {
2957 if ((val = prog_dmabuf_dac(s)))
2958 return val;
2959 return put_user(s->dma_dac.fragsize, (int *) arg);
2960 }
2961 if ((val = prog_dmabuf_adc(s)))
2962 return val;
2963 if (s->conversion)
2964 return put_user(s->dma_adc.fragsize / 2,
2965 (int *) arg);
2966 else
2967 return put_user(s->dma_adc.fragsize, (int *) arg);
2968
2969 case SNDCTL_DSP_SETFRAGMENT:
2970 if (get_user(val, (int *) arg))
2971 return -EFAULT;
2972 return 0; // Say OK, but do nothing.
2973
2974 case SNDCTL_DSP_SUBDIVIDE:
2975 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
2976 || (file->f_mode & FMODE_WRITE
2977 && s->dma_dac.subdivision)) return -EINVAL;
2978 if (get_user(val, (int *) arg))
2979 return -EFAULT;
2980 if (val != 1 && val != 2 && val != 4)
2981 return -EINVAL;
2982 if (file->f_mode & FMODE_READ)
2983 s->dma_adc.subdivision = val;
2984 else if (file->f_mode & FMODE_WRITE)
2985 s->dma_dac.subdivision = val;
2986 return 0;
2987
2988 case SOUND_PCM_READ_RATE:
2989 if (file->f_mode & FMODE_READ)
2990 return put_user(s->prop_adc.rate, (int *) arg);
2991 else if (file->f_mode & FMODE_WRITE)
2992 return put_user(s->prop_dac.rate, (int *) arg);
2993
2994 case SOUND_PCM_READ_CHANNELS:
2995 if (file->f_mode & FMODE_READ)
2996 return put_user(s->prop_adc.channels, (int *) arg);
2997 else if (file->f_mode & FMODE_WRITE)
2998 return put_user(s->prop_dac.channels, (int *) arg);
2999
3000 case SOUND_PCM_READ_BITS:
3001 if (file->f_mode & FMODE_READ)
3002 return
3003 put_user(
3004 (s->prop_adc.
3005 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
3006 (int *) arg);
3007 else if (file->f_mode & FMODE_WRITE)
3008 return
3009 put_user(
3010 (s->prop_dac.
3011 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
3012 (int *) arg);
3013
3014 case SOUND_PCM_WRITE_FILTER:
3015 case SNDCTL_DSP_SETSYNCRO:
3016 case SOUND_PCM_READ_FILTER:
3017 return -EINVAL;
3018
3019 #if CSDEBUG_INTERFACE
3020
3021 case SNDCTL_DSP_CS_GETDBGMASK:
3022 return put_user(cs_debugmask, (unsigned long *) arg);
3023
3024 case SNDCTL_DSP_CS_GETDBGLEVEL:
3025 return put_user(cs_debuglevel, (unsigned long *) arg);
3026
3027 case SNDCTL_DSP_CS_SETDBGMASK:
3028 if (get_user(val, (unsigned long *) arg))
3029 return -EFAULT;
3030 cs_debugmask = val;
3031 return 0;
3032
3033 case SNDCTL_DSP_CS_SETDBGLEVEL:
3034 if (get_user(val, (unsigned long *) arg))
3035 return -EFAULT;
3036 cs_debuglevel = val;
3037 return 0;
3038 #endif
3039
3040 }
3041 return mixer_ioctl(s, cmd, arg);
3042 }
3043
3044
3045 static int cs4281_release(struct inode *inode, struct file *file)
3046 {
3047 struct cs4281_state *s =
3048 (struct cs4281_state *) file->private_data;
3049
3050 CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2,
3051 printk(KERN_INFO
3052 "cs4281: cs4281_release(): inode=0x%.8x file=0x%.8x f_mode=%d\n",
3053 (unsigned) inode, (unsigned) file, file->f_mode));
3054
3055 VALIDATE_STATE(s);
3056
3057 if (file->f_mode & FMODE_WRITE) {
3058 drain_dac(s, file->f_flags & O_NONBLOCK);
3059 down(&s->open_sem_dac);
3060 stop_dac(s);
3061 dealloc_dmabuf(s, &s->dma_dac);
3062 s->open_mode &= ~FMODE_WRITE;
3063 up(&s->open_sem_dac);
3064 wake_up(&s->open_wait_dac);
3065 MOD_DEC_USE_COUNT;
3066 }
3067 if (file->f_mode & FMODE_READ) {
3068 drain_adc(s, file->f_flags & O_NONBLOCK);
3069 down(&s->open_sem_adc);
3070 stop_adc(s);
3071 dealloc_dmabuf(s, &s->dma_adc);
3072 s->open_mode &= ~FMODE_READ;
3073 up(&s->open_sem_adc);
3074 wake_up(&s->open_wait_adc);
3075 MOD_DEC_USE_COUNT;
3076 }
3077 return 0;
3078 }
3079
3080 static int cs4281_open(struct inode *inode, struct file *file)
3081 {
3082 int minor = MINOR(inode->i_rdev);
3083 struct cs4281_state *s = devs;
3084
3085 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
3086 printk(KERN_INFO
3087 "cs4281: cs4281_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
3088 (unsigned) inode, (unsigned) file, file->f_mode));
3089 while (s && ((s->dev_audio ^ minor) & ~0xf))
3090 s = s->next;
3091 if (!s) {
3092 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
3093 "cs4281: cs4281_open(): Error - unable to find audio state struct\n"));
3094 return -ENODEV;
3095 }
3096 VALIDATE_STATE(s);
3097 file->private_data = s;
3098
3099 // wait for device to become free
3100 if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
3101 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
3102 printk(KERN_INFO
3103 "cs4281: cs4281_open(): Error - must open READ and/or WRITE\n"));
3104 return -ENODEV;
3105 }
3106 if (file->f_mode & FMODE_WRITE) {
3107 down(&s->open_sem_dac);
3108 while (s->open_mode & FMODE_WRITE) {
3109 if (file->f_flags & O_NONBLOCK) {
3110 up(&s->open_sem_dac);
3111 return -EBUSY;
3112 }
3113 up(&s->open_sem_dac);
3114 interruptible_sleep_on(&s->open_wait_dac);
3115
3116 if (signal_pending(current))
3117 return -ERESTARTSYS;
3118 down(&s->open_sem_dac);
3119 }
3120 }
3121 if (file->f_mode & FMODE_READ) {
3122 down(&s->open_sem_adc);
3123 while (s->open_mode & FMODE_READ) {
3124 if (file->f_flags & O_NONBLOCK) {
3125 up(&s->open_sem_adc);
3126 return -EBUSY;
3127 }
3128 up(&s->open_sem_adc);
3129 interruptible_sleep_on(&s->open_wait_adc);
3130
3131 if (signal_pending(current))
3132 return -ERESTARTSYS;
3133 down(&s->open_sem_adc);
3134 }
3135 }
3136 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
3137 if (file->f_mode & FMODE_READ) {
3138 s->prop_adc.fmt = AFMT_U8;
3139 s->prop_adc.fmt_original = s->prop_adc.fmt;
3140 s->prop_adc.channels = 1;
3141 s->prop_adc.rate = 8000;
3142 s->prop_adc.clkdiv = 96 | 0x80;
3143 s->conversion = 0;
3144 s->ena &= ~FMODE_READ;
3145 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
3146 s->dma_adc.subdivision = 0;
3147 up(&s->open_sem_adc);
3148 MOD_INC_USE_COUNT;
3149
3150 if (prog_dmabuf_adc(s)) {
3151 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
3152 "cs4281: adc Program dmabufs failed.\n"));
3153 cs4281_release(inode, file);
3154 return -ENOMEM;
3155 }
3156 prog_codec(s, CS_TYPE_ADC);
3157 }
3158 if (file->f_mode & FMODE_WRITE) {
3159 s->prop_dac.fmt = AFMT_U8;
3160 s->prop_dac.fmt_original = s->prop_dac.fmt;
3161 s->prop_dac.channels = 1;
3162 s->prop_dac.rate = 8000;
3163 s->prop_dac.clkdiv = 96 | 0x80;
3164 s->conversion = 0;
3165 s->ena &= ~FMODE_WRITE;
3166 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
3167 s->dma_dac.subdivision = 0;
3168 up(&s->open_sem_dac);
3169 MOD_INC_USE_COUNT;
3170
3171 if (prog_dmabuf_dac(s)) {
3172 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
3173 "cs4281: dac Program dmabufs failed.\n"));
3174 cs4281_release(inode, file);
3175 return -ENOMEM;
3176 }
3177 prog_codec(s, CS_TYPE_DAC);
3178 }
3179 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
3180 printk(KERN_INFO "cs4281: cs4281_open()- 0\n"));
3181 return 0;
3182 }
3183
3184
3185 // ******************************************************************************************
3186 // Wave (audio) file operations struct.
3187 // ******************************************************************************************
3188 static /*const */ struct file_operations cs4281_audio_fops = {
3189 llseek:cs4281_llseek,
3190 read:cs4281_read,
3191 write:cs4281_write,
3192 poll:cs4281_poll,
3193 ioctl:cs4281_ioctl,
3194 mmap:cs4281_mmap,
3195 open:cs4281_open,
3196 release:cs4281_release,
3197 };
3198
3199 // ---------------------------------------------------------------------
3200
3201 // hold spinlock for the following!
3202 static void cs4281_handle_midi(struct cs4281_state *s)
3203 {
3204 unsigned char ch;
3205 int wake;
3206 unsigned temp1;
3207
3208 wake = 0;
3209 while (!(readl(s->pBA0 + BA0_MIDSR) & 0x80)) {
3210 ch = readl(s->pBA0 + BA0_MIDRP);
3211 if (s->midi.icnt < MIDIINBUF) {
3212 s->midi.ibuf[s->midi.iwr] = ch;
3213 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
3214 s->midi.icnt++;
3215 }
3216 wake = 1;
3217 }
3218 if (wake)
3219 wake_up(&s->midi.iwait);
3220 wake = 0;
3221 while (!(readl(s->pBA0 + BA0_MIDSR) & 0x40) && s->midi.ocnt > 0) {
3222 temp1 = (s->midi.obuf[s->midi.ord]) & 0x000000ff;
3223 writel(temp1, s->pBA0 + BA0_MIDWP);
3224 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
3225 s->midi.ocnt--;
3226 if (s->midi.ocnt < MIDIOUTBUF - 16)
3227 wake = 1;
3228 }
3229 if (wake)
3230 wake_up(&s->midi.owait);
3231 }
3232
3233
3234
3235 static void cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3236 {
3237 struct cs4281_state *s = (struct cs4281_state *) dev_id;
3238 unsigned int temp1;
3239
3240 // fastpath out, to ease interrupt sharing
3241 temp1 = readl(s->pBA0 + BA0_HISR); // Get Int Status reg.
3242
3243 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
3244 "cs4281: cs4281_interrupt() BA0_HISR=0x%.8x\n",
3245 temp1));
3246
3247 if (!(temp1 & (HISR_DMA0 | HISR_DMA1 | HISR_MIDI))) { // If not DMA or MIDI int,
3248 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // reenable interrupts
3249 CS_DBGOUT(CS_INTERRUPT, 4, printk(KERN_INFO
3250 "cs4281: cs4281_interrupt(): returning not cs4281 interrupt.\n"));
3251 return; // and return.
3252 }
3253
3254 if (temp1 & HISR_DMA0) // If play interrupt,
3255 readl(s->pBA0 + BA0_HDSR0); // clear the source.
3256
3257 if (temp1 & HISR_DMA1) // Same for play.
3258 readl(s->pBA0 + BA0_HDSR1);
3259 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Local EOI
3260
3261 spin_lock(&s->lock);
3262 cs4281_update_ptr(s);
3263 cs4281_handle_midi(s);
3264 spin_unlock(&s->lock);
3265 }
3266
3267 // **************************************************************************
3268
3269 static void cs4281_midi_timer(unsigned long data)
3270 {
3271 struct cs4281_state *s = (struct cs4281_state *) data;
3272 unsigned long flags;
3273
3274 spin_lock_irqsave(&s->lock, flags);
3275 cs4281_handle_midi(s);
3276 spin_unlock_irqrestore(&s->lock, flags);
3277 s->midi.timer.expires = jiffies + 1;
3278 add_timer(&s->midi.timer);
3279 }
3280
3281
3282 // ---------------------------------------------------------------------
3283
3284 static ssize_t cs4281_midi_read(struct file *file, char *buffer,
3285 size_t count, loff_t * ppos)
3286 {
3287 struct cs4281_state *s =
3288 (struct cs4281_state *) file->private_data;
3289 ssize_t ret;
3290 unsigned long flags;
3291 unsigned ptr;
3292 int cnt;
3293
3294 VALIDATE_STATE(s);
3295 if (ppos != &file->f_pos)
3296 return -ESPIPE;
3297 if (!access_ok(VERIFY_WRITE, buffer, count))
3298 return -EFAULT;
3299 ret = 0;
3300 while (count > 0) {
3301 spin_lock_irqsave(&s->lock, flags);
3302 ptr = s->midi.ird;
3303 cnt = MIDIINBUF - ptr;
3304 if (s->midi.icnt < cnt)
3305 cnt = s->midi.icnt;
3306 spin_unlock_irqrestore(&s->lock, flags);
3307 if (cnt > count)
3308 cnt = count;
3309 if (cnt <= 0) {
3310 if (file->f_flags & O_NONBLOCK)
3311 return ret ? ret : -EAGAIN;
3312 interruptible_sleep_on(&s->midi.iwait);
3313 if (signal_pending(current))
3314 return ret ? ret : -ERESTARTSYS;
3315 continue;
3316 }
3317 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt))
3318 return ret ? ret : -EFAULT;
3319 ptr = (ptr + cnt) % MIDIINBUF;
3320 spin_lock_irqsave(&s->lock, flags);
3321 s->midi.ird = ptr;
3322 s->midi.icnt -= cnt;
3323 spin_unlock_irqrestore(&s->lock, flags);
3324 count -= cnt;
3325 buffer += cnt;
3326 ret += cnt;
3327 }
3328 return ret;
3329 }
3330
3331
3332 static ssize_t cs4281_midi_write(struct file *file, const char *buffer,
3333 size_t count, loff_t * ppos)
3334 {
3335 struct cs4281_state *s =
3336 (struct cs4281_state *) file->private_data;
3337 ssize_t ret;
3338 unsigned long flags;
3339 unsigned ptr;
3340 int cnt;
3341
3342 VALIDATE_STATE(s);
3343 if (ppos != &file->f_pos)
3344 return -ESPIPE;
3345 if (!access_ok(VERIFY_READ, buffer, count))
3346 return -EFAULT;
3347 ret = 0;
3348 while (count > 0) {
3349 spin_lock_irqsave(&s->lock, flags);
3350 ptr = s->midi.owr;
3351 cnt = MIDIOUTBUF - ptr;
3352 if (s->midi.ocnt + cnt > MIDIOUTBUF)
3353 cnt = MIDIOUTBUF - s->midi.ocnt;
3354 if (cnt <= 0)
3355 cs4281_handle_midi(s);
3356 spin_unlock_irqrestore(&s->lock, flags);
3357 if (cnt > count)
3358 cnt = count;
3359 if (cnt <= 0) {
3360 if (file->f_flags & O_NONBLOCK)
3361 return ret ? ret : -EAGAIN;
3362 interruptible_sleep_on(&s->midi.owait);
3363 if (signal_pending(current))
3364 return ret ? ret : -ERESTARTSYS;
3365 continue;
3366 }
3367 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt))
3368 return ret ? ret : -EFAULT;
3369 ptr = (ptr + cnt) % MIDIOUTBUF;
3370 spin_lock_irqsave(&s->lock, flags);
3371 s->midi.owr = ptr;
3372 s->midi.ocnt += cnt;
3373 spin_unlock_irqrestore(&s->lock, flags);
3374 count -= cnt;
3375 buffer += cnt;
3376 ret += cnt;
3377 spin_lock_irqsave(&s->lock, flags);
3378 cs4281_handle_midi(s);
3379 spin_unlock_irqrestore(&s->lock, flags);
3380 }
3381 return ret;
3382 }
3383
3384
3385 static unsigned int cs4281_midi_poll(struct file *file,
3386 struct poll_table_struct *wait)
3387 {
3388 struct cs4281_state *s =
3389 (struct cs4281_state *) file->private_data;
3390 unsigned long flags;
3391 unsigned int mask = 0;
3392
3393 VALIDATE_STATE(s);
3394 if (file->f_flags & FMODE_WRITE)
3395 poll_wait(file, &s->midi.owait, wait);
3396 if (file->f_flags & FMODE_READ)
3397 poll_wait(file, &s->midi.iwait, wait);
3398 spin_lock_irqsave(&s->lock, flags);
3399 if (file->f_flags & FMODE_READ) {
3400 if (s->midi.icnt > 0)
3401 mask |= POLLIN | POLLRDNORM;
3402 }
3403 if (file->f_flags & FMODE_WRITE) {
3404 if (s->midi.ocnt < MIDIOUTBUF)
3405 mask |= POLLOUT | POLLWRNORM;
3406 }
3407 spin_unlock_irqrestore(&s->lock, flags);
3408 return mask;
3409 }
3410
3411
3412 static int cs4281_midi_open(struct inode *inode, struct file *file)
3413 {
3414 int minor = MINOR(inode->i_rdev);
3415 struct cs4281_state *s = devs;
3416 unsigned long flags, temp1;
3417 while (s && s->dev_midi != minor)
3418 s = s->next;
3419 if (!s)
3420 return -ENODEV;
3421 VALIDATE_STATE(s);
3422 file->private_data = s;
3423 // wait for device to become free
3424 down(&s->open_sem);
3425 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
3426 if (file->f_flags & O_NONBLOCK) {
3427 up(&s->open_sem);
3428 return -EBUSY;
3429 }
3430 up(&s->open_sem);
3431 interruptible_sleep_on(&s->open_wait);
3432 if (signal_pending(current))
3433 return -ERESTARTSYS;
3434 down(&s->open_sem);
3435 }
3436 spin_lock_irqsave(&s->lock, flags);
3437 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
3438 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
3439 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
3440 writel(1, s->pBA0 + BA0_MIDCR); // Reset the interface.
3441 writel(0, s->pBA0 + BA0_MIDCR); // Return to normal mode.
3442 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
3443 writel(0x0000000f, s->pBA0 + BA0_MIDCR); // Enable transmit, record, ints.
3444 temp1 = readl(s->pBA0 + BA0_HIMR);
3445 writel(temp1 & 0xffbfffff, s->pBA0 + BA0_HIMR); // Enable midi int. recognition.
3446 writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Enable interrupts
3447 init_timer(&s->midi.timer);
3448 s->midi.timer.expires = jiffies + 1;
3449 s->midi.timer.data = (unsigned long) s;
3450 s->midi.timer.function = cs4281_midi_timer;
3451 add_timer(&s->midi.timer);
3452 }
3453 if (file->f_mode & FMODE_READ) {
3454 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
3455 }
3456 if (file->f_mode & FMODE_WRITE) {
3457 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
3458 }
3459 spin_unlock_irqrestore(&s->lock, flags);
3460 s->open_mode |=
3461 (file->
3462 f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ |
3463 FMODE_MIDI_WRITE);
3464 up(&s->open_sem);
3465 MOD_INC_USE_COUNT;
3466 return 0;
3467 }
3468
3469
3470 static int cs4281_midi_release(struct inode *inode, struct file *file)
3471 {
3472 struct cs4281_state *s =
3473 (struct cs4281_state *) file->private_data;
3474 DECLARE_WAITQUEUE(wait, current);
3475 unsigned long flags;
3476 unsigned count, tmo;
3477
3478 VALIDATE_STATE(s);
3479
3480 if (file->f_mode & FMODE_WRITE) {
3481 add_wait_queue(&s->midi.owait, &wait);
3482 for (;;) {
3483 set_current_state(TASK_INTERRUPTIBLE);
3484 spin_lock_irqsave(&s->lock, flags);
3485 count = s->midi.ocnt;
3486 spin_unlock_irqrestore(&s->lock, flags);
3487 if (count <= 0)
3488 break;
3489 if (signal_pending(current))
3490 break;
3491 if (file->f_flags & O_NONBLOCK) {
3492 remove_wait_queue(&s->midi.owait, &wait);
3493 current->state = TASK_RUNNING;
3494 return -EBUSY;
3495 }
3496 tmo = (count * HZ) / 3100;
3497 if (!schedule_timeout(tmo ? : 1) && tmo)
3498 printk(KERN_DEBUG
3499 "cs4281: midi timed out??\n");
3500 }
3501 remove_wait_queue(&s->midi.owait, &wait);
3502 current->state = TASK_RUNNING;
3503 }
3504 down(&s->open_sem);
3505 s->open_mode &=
3506 (~(file->f_mode << FMODE_MIDI_SHIFT)) & (FMODE_MIDI_READ |
3507 FMODE_MIDI_WRITE);
3508 spin_lock_irqsave(&s->lock, flags);
3509 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
3510 writel(0, s->pBA0 + BA0_MIDCR); // Disable Midi interrupts.
3511 del_timer(&s->midi.timer);
3512 }
3513 spin_unlock_irqrestore(&s->lock, flags);
3514 up(&s->open_sem);
3515 wake_up(&s->open_wait);
3516 MOD_DEC_USE_COUNT;
3517 return 0;
3518 }
3519
3520 // ******************************************************************************************
3521 // Midi file operations struct.
3522 // ******************************************************************************************
3523 static /*const */ struct file_operations cs4281_midi_fops = {
3524 llseek:cs4281_llseek,
3525 read:cs4281_midi_read,
3526 write:cs4281_midi_write,
3527 poll:cs4281_midi_poll,
3528 open:cs4281_midi_open,
3529 release:cs4281_midi_release,
3530 };
3531
3532
3533 // ---------------------------------------------------------------------
3534
3535 // maximum number of devices
3536 #define NR_DEVICE 8 // Only eight devices supported currently.
3537
3538 // ---------------------------------------------------------------------
3539
3540 static struct initvol {
3541 int mixch;
3542 int vol;
3543 } initvol[] __initdata = {
3544
3545 {
3546 SOUND_MIXER_WRITE_VOLUME, 0x4040}, {
3547 SOUND_MIXER_WRITE_PCM, 0x4040}, {
3548 SOUND_MIXER_WRITE_SYNTH, 0x4040}, {
3549 SOUND_MIXER_WRITE_CD, 0x4040}, {
3550 SOUND_MIXER_WRITE_LINE, 0x4040}, {
3551 SOUND_MIXER_WRITE_LINE1, 0x4040}, {
3552 SOUND_MIXER_WRITE_RECLEV, 0x0000}, {
3553 SOUND_MIXER_WRITE_SPEAKER, 0x4040}, {
3554 SOUND_MIXER_WRITE_MIC, 0x0000}
3555 };
3556
3557
3558 static int __devinit cs4281_probe(struct pci_dev *pcidev,
3559 const struct pci_device_id *pciid)
3560 {
3561 struct cs4281_state *s;
3562 dma_addr_t dma_mask;
3563 mm_segment_t fs;
3564 int i, val, index = 0;
3565 unsigned int temp1, temp2;
3566
3567 CS_DBGOUT(CS_FUNCTION | CS_INIT, 2,
3568 printk(KERN_INFO "cs4281: probe()+\n"));
3569
3570 if (!RSRCISMEMORYREGION(pcidev, 0) ||
3571 !RSRCISMEMORYREGION(pcidev, 1)) {
3572 CS_DBGOUT(CS_ERROR, 1,
3573 printk(KERN_ERR
3574 "cs4281: probe()- Memory region not assigned\n"));
3575 return -1;
3576 }
3577 if (pcidev->irq == 0) {
3578 CS_DBGOUT(CS_ERROR, 1,
3579 printk(KERN_ERR
3580 "cs4281: probe() IRQ not assigned\n"));
3581 return -1;
3582 }
3583 if (!pci_dma_supported(pcidev, 0xffffffff)) {
3584 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
3585 "cs4281: probe() architecture does not support 32bit PCI busmaster DMA\n"));
3586 return -1;
3587 }
3588 dma_mask = 0xffffffff; /* this enables playback and recording */
3589 if (!(s = kmalloc(sizeof(struct cs4281_state), GFP_KERNEL))) {
3590 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
3591 "cs4281: probe() no memory for state struct.\n"));
3592 return -1;
3593 }
3594 memset(s, 0, sizeof(struct cs4281_state));
3595 init_waitqueue_head(&s->dma_adc.wait);
3596 init_waitqueue_head(&s->dma_dac.wait);
3597 init_waitqueue_head(&s->open_wait);
3598 init_waitqueue_head(&s->open_wait_adc);
3599 init_waitqueue_head(&s->open_wait_dac);
3600 init_waitqueue_head(&s->midi.iwait);
3601 init_waitqueue_head(&s->midi.owait);
3602 init_MUTEX(&s->open_sem);
3603 init_MUTEX(&s->open_sem_adc);
3604 init_MUTEX(&s->open_sem_dac);
3605 spin_lock_init(&s->lock);
3606 s->pBA0phys = RSRCADDRESS(pcidev, 0);
3607 s->pBA1phys = RSRCADDRESS(pcidev, 1);
3608 s->pBA0 = ioremap_nocache(s->pBA0phys, 4096); // Convert phys
3609 s->pBA1 = ioremap_nocache(s->pBA1phys, 65536); // to linear.
3610 temp1 = readl(s->pBA0 + BA0_PCICFG00);
3611 temp2 = readl(s->pBA0 + BA0_PCICFG04);
3612
3613 CS_DBGOUT(CS_INIT, 2,
3614 printk(KERN_INFO
3615 "cs4281: probe() BA0=0x%.8x BA1=0x%.8x pBA0=0x%.8x pBA1=0x%.8x \n",
3616 (unsigned) temp1, (unsigned) temp2,
3617 (unsigned) s->pBA0, (unsigned) s->pBA1));
3618
3619 CS_DBGOUT(CS_INIT, 2,
3620 printk(KERN_INFO
3621 "cs4281: probe() pBA0phys=0x%.8x pBA1phys=0x%.8x\n",
3622 (unsigned) s->pBA0phys, (unsigned) s->pBA1phys));
3623
3624 temp1 = cs4281_hw_init(s);
3625 if (temp1) {
3626 CS_DBGOUT(CS_ERROR | CS_INIT, 1,
3627 printk(KERN_ERR
3628 "cs4281: cs4281_hw_init() failed. Skipping part.\n"));
3629 return -1;
3630 }
3631 s->magic = CS4281_MAGIC;
3632 s->pcidev = pcidev;
3633 s->irq = pcidev->irq;
3634 if (pci_enable_device(pcidev)) {
3635 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
3636 printk(KERN_ERR
3637 "cs4281: pci_enable_device() failed\n"));
3638 goto err_irq;
3639 }
3640 if (request_irq
3641 (s->irq, cs4281_interrupt, SA_SHIRQ, "Crystal CS4281", s)) {
3642 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
3643 printk(KERN_ERR "cs4281: irq %u in use\n",
3644 s->irq));
3645 goto err_irq;
3646 }
3647 if ((s->dev_audio = register_sound_dsp(&cs4281_audio_fops, -1)) <
3648 0) {
3649 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
3650 printk(KERN_ERR
3651 "cs4281: probe() register_sound_dsp() failed.\n"));
3652 goto err_dev1;
3653 }
3654 if ((s->dev_mixer = register_sound_mixer(&cs4281_mixer_fops, -1)) <
3655 0) {
3656 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
3657 printk(KERN_ERR
3658 "cs4281: probe() register_sound_mixer() failed.\n"));
3659 goto err_dev2;
3660 }
3661 if ((s->dev_midi = register_sound_midi(&cs4281_midi_fops, -1)) < 0) {
3662 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
3663 printk(KERN_ERR
3664 "cs4281: probe() register_sound_midi() failed.\n"));
3665 goto err_dev3;
3666 }
3667
3668 pci_set_master(pcidev); // enable bus mastering
3669
3670 fs = get_fs();
3671 set_fs(KERNEL_DS);
3672 val = SOUND_MASK_LINE;
3673 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
3674 for (i = 0; i < sizeof(initvol) / sizeof(initvol[0]); i++) {
3675 val = initvol[i].vol;
3676 mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
3677 }
3678 val = 1; // enable mic preamp
3679 mixer_ioctl(s, SOUND_MIXER_PRIVATE1, (unsigned long) &val);
3680 set_fs(fs);
3681
3682 // queue it for later freeing
3683 s->next = devs;
3684 pcidev->driver_data = s;
3685 pcidev->dma_mask = dma_mask;
3686 devs = s;
3687 index++;
3688 return 0;
3689
3690 err_dev3:
3691 unregister_sound_mixer(s->dev_mixer);
3692 err_dev2:
3693 unregister_sound_dsp(s->dev_audio);
3694 err_dev1:
3695 free_irq(s->irq, s);
3696 err_irq:
3697 kfree(s);
3698
3699 if (!devs) {
3700 CS_DBGOUT(CS_INIT | CS_ERROR, 1,
3701 printk(KERN_INFO
3702 "cs4281: probe()- no device allocated\n"));
3703 return -ENODEV;
3704 }
3705 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
3706 printk(KERN_INFO
3707 "cs4281: probe()- device allocated successfully\n"));
3708 return 0;
3709 } // probe_cs4281
3710
3711
3712 // ---------------------------------------------------------------------
3713
3714 static void __devinit cs4281_remove(struct pci_dev *dev)
3715 {
3716 struct cs4281_state *s = (struct cs4281_state *) dev->driver_data;
3717 // stop DMA controller
3718 synchronize_irq();
3719 free_irq(s->irq, s);
3720 unregister_sound_dsp(s->dev_audio);
3721 unregister_sound_mixer(s->dev_mixer);
3722 unregister_sound_midi(s->dev_midi);
3723 kfree(s);
3724 dev->driver_data = NULL;
3725 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
3726 printk(KERN_INFO
3727 "cs4281: cs4281_remove(): remove successful\n"));
3728 }
3729
3730 static struct pci_device_id id_table[] __devinitdata = {
3731
3732 {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CRYSTAL_CS4281,
3733 PCI_ANY_ID, PCI_ANY_ID, 0, 0},
3734 {0,}
3735 };
3736
3737 MODULE_DEVICE_TABLE(pci, id_table);
3738
3739 static struct pci_driver cs4281_driver = {
3740 name:"cs4281",
3741 id_table:id_table,
3742 probe:cs4281_probe,
3743 remove:cs4281_remove
3744 };
3745
3746 static int __init init_cs4281(void)
3747 {
3748
3749 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
3750 printk(KERN_INFO "cs4281: init_cs4281()+ \n"));
3751 if (!pci_present()) { /* No PCI bus in this machine! */
3752 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
3753 printk(KERN_INFO
3754 "cs4281: init_cs4281()- no pci bus found\n"));
3755 return -ENODEV;
3756 }
3757 printk(KERN_INFO "cs4281: version v%d.%02d.%d time " __TIME__ " "
3758 __DATE__ "\n", CS4281_MAJOR_VERSION, CS4281_MINOR_VERSION,
3759 CS4281_ARCH);
3760 if (!pci_register_driver(&cs4281_driver)) {
3761 pci_unregister_driver(&cs4281_driver);
3762 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
3763 printk(KERN_INFO
3764 "cs4281: init_cs4281()- unable to register pci device \n"));
3765 return -ENODEV;
3766 }
3767 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
3768 printk(KERN_INFO "cs4281: init_cs4281()- 0\n"));
3769 return 0;
3770 }
3771
3772
3773 // ---------------------------------------------------------------------
3774
3775
3776 MODULE_AUTHOR("gw boynton, wesb@crystal.cirrus.com");
3777 MODULE_DESCRIPTION("Cirrus Logic CS4281 Driver");
3778
3779 static void __exit cleanup_cs4281(void)
3780 {
3781 pci_unregister_driver(&cs4281_driver);
3782 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
3783 printk(KERN_INFO "cs4281: cleanup_cs4281() finished\n"));
3784 }
3785
3786 // ---------------------------------------------------------------------
3787
3788 module_init(init_cs4281);
3789 module_exit(cleanup_cs4281);
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