2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
23 #include <linux/irq.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/config.h>
29 #include <linux/smp_lock.h>
30 #include <linux/mc146818rtc.h>
36 static spinlock_t ioapic_lock
= SPIN_LOCK_UNLOCKED
;
39 * # of IO-APICs and # of IRQ routing registers
42 int nr_ioapic_registers
[MAX_IO_APICS
];
44 /* I/O APIC entries */
45 struct mpc_config_ioapic mp_ioapics
[MAX_IO_APICS
];
47 /* # of MP IRQ source entries */
48 struct mpc_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
50 /* MP IRQ source entries */
54 # define TARGET_CPUS cpu_online_map
56 # define TARGET_CPUS 0x01
59 * Rough estimation of how many shared IRQs there are, can
62 #define MAX_PLUS_SHARED_IRQS NR_IRQS
63 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
66 * This is performance-critical, we want to do it O(1)
68 * the indexing order of this array favors 1:1 mappings
69 * between pins and IRQs.
72 static struct irq_pin_list
{
74 } irq_2_pin
[PIN_MAP_SIZE
];
77 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
78 * shared ISA-space IRQs, so we have to support them. We are super
79 * fast in the common case, and fast for shared ISA-space IRQs.
81 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
83 static int first_free_entry
= NR_IRQS
;
84 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
87 entry
= irq_2_pin
+ entry
->next
;
89 if (entry
->pin
!= -1) {
90 entry
->next
= first_free_entry
;
91 entry
= irq_2_pin
+ entry
->next
;
92 if (++first_free_entry
>= PIN_MAP_SIZE
)
93 panic("io_apic.c: whoops");
99 #define __DO_ACTION(R, ACTION, FINAL) \
103 struct irq_pin_list *entry = irq_2_pin + irq; \
110 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
112 io_apic_modify(entry->apic, reg); \
115 entry = irq_2_pin + entry->next; \
120 #define DO_ACTION(name,R,ACTION, FINAL) \
122 static void name##_IO_APIC_irq (unsigned int irq) \
123 __DO_ACTION(R, ACTION, FINAL)
125 DO_ACTION( __mask
, 0, |= 0x00010000, io_apic_sync(entry
->apic
))/* mask = 1 */
126 DO_ACTION( __unmask
, 0, &= 0xfffeffff, ) /* mask = 0 */
128 static void mask_IO_APIC_irq (unsigned int irq
)
132 spin_lock_irqsave(&ioapic_lock
, flags
);
133 __mask_IO_APIC_irq(irq
);
134 spin_unlock_irqrestore(&ioapic_lock
, flags
);
137 static void unmask_IO_APIC_irq (unsigned int irq
)
141 spin_lock_irqsave(&ioapic_lock
, flags
);
142 __unmask_IO_APIC_irq(irq
);
143 spin_unlock_irqrestore(&ioapic_lock
, flags
);
146 void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
148 struct IO_APIC_route_entry entry
;
151 * Disable it in the IO-APIC irq-routing table:
153 memset(&entry
, 0, sizeof(entry
));
155 io_apic_write(apic
, 0x10 + 2 * pin
, *(((int *)&entry
) + 0));
156 io_apic_write(apic
, 0x11 + 2 * pin
, *(((int *)&entry
) + 1));
159 static void clear_IO_APIC (void)
163 for (apic
= 0; apic
< nr_ioapics
; apic
++)
164 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
165 clear_IO_APIC_pin(apic
, pin
);
169 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
170 * specific CPU-side IRQs.
174 int pirq_entries
[MAX_PIRQS
];
176 int skip_ioapic_setup
;
178 static int __init
ioapic_setup(char *str
)
180 skip_ioapic_setup
= 1;
184 __setup("noapic", ioapic_setup
);
186 static int __init
ioapic_pirq_setup(char *str
)
189 int ints
[MAX_PIRQS
+1];
191 get_options(str
, ARRAY_SIZE(ints
), ints
);
193 for (i
= 0; i
< MAX_PIRQS
; i
++)
194 pirq_entries
[i
] = -1;
197 printk(KERN_INFO
"PIRQ redirection, working around broken MP-BIOS.\n");
199 if (ints
[0] < MAX_PIRQS
)
202 for (i
= 0; i
< max
; i
++) {
203 printk(KERN_DEBUG
"... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
205 * PIRQs are mapped upside down, usually.
207 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
212 __setup("pirq=", ioapic_pirq_setup
);
215 * Find the IRQ entry number of a certain pin.
217 static int __init
find_irq_entry(int apic
, int pin
, int type
)
221 for (i
= 0; i
< mp_irq_entries
; i
++)
222 if (mp_irqs
[i
].mpc_irqtype
== type
&&
223 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
224 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
225 mp_irqs
[i
].mpc_dstirq
== pin
)
232 * Find the pin to which IRQ[irq] (ISA) is connected
234 static int __init
find_isa_irq_pin(int irq
, int type
)
238 for (i
= 0; i
< mp_irq_entries
; i
++) {
239 int lbus
= mp_irqs
[i
].mpc_srcbus
;
241 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_ISA
||
242 mp_bus_id_to_type
[lbus
] == MP_BUS_EISA
||
243 mp_bus_id_to_type
[lbus
] == MP_BUS_MCA
) &&
244 (mp_irqs
[i
].mpc_irqtype
== type
) &&
245 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
247 return mp_irqs
[i
].mpc_dstirq
;
253 * Find a specific PCI IRQ entry.
254 * Not an __init, possibly needed by modules
256 static int __init
pin_2_irq(int idx
, int apic
, int pin
);
257 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pci_pin
)
259 int apic
, i
, best_guess
= -1;
261 for (i
= 0; i
< mp_irq_entries
; i
++) {
262 int lbus
= mp_irqs
[i
].mpc_srcbus
;
264 for (apic
= 0; apic
< nr_ioapics
; apic
++)
265 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
266 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
269 if ((mp_bus_id_to_type
[lbus
] == MP_BUS_PCI
) &&
270 !mp_irqs
[i
].mpc_irqtype
&&
271 (bus
== mp_bus_id_to_pci_bus
[mp_irqs
[i
].mpc_srcbus
]) &&
272 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
273 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
275 if (!(apic
|| IO_APIC_IRQ(irq
)))
278 if (pci_pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
281 * Use the first all-but-pin matching entry as a
282 * best-guess fuzzy result for broken mptables.
292 * EISA Edge/Level control register, ELCR
294 static int __init
EISA_ELCR(unsigned int irq
)
297 unsigned int port
= 0x4d0 + (irq
>> 3);
298 return (inb(port
) >> (irq
& 7)) & 1;
300 printk(KERN_INFO
"Broken MPtable reports ISA irq %d\n", irq
);
304 /* EISA interrupts are always polarity zero and can be edge or level
305 * trigger depending on the ELCR value. If an interrupt is listed as
306 * EISA conforming in the MP table, that means its trigger type must
307 * be read in from the ELCR */
309 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
310 #define default_EISA_polarity(idx) (0)
312 /* ISA interrupts are always polarity zero edge triggered,
313 * when listed as conforming in the MP table. */
315 #define default_ISA_trigger(idx) (0)
316 #define default_ISA_polarity(idx) (0)
318 /* PCI interrupts are always polarity one level triggered,
319 * when listed as conforming in the MP table. */
321 #define default_PCI_trigger(idx) (1)
322 #define default_PCI_polarity(idx) (1)
324 /* MCA interrupts are always polarity zero level triggered,
325 * when listed as conforming in the MP table. */
327 #define default_MCA_trigger(idx) (1)
328 #define default_MCA_polarity(idx) (0)
330 static int __init
MPBIOS_polarity(int idx
)
332 int bus
= mp_irqs
[idx
].mpc_srcbus
;
336 * Determine IRQ line polarity (high active or low active):
338 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
340 case 0: /* conforms, ie. bus-type dependent polarity */
342 switch (mp_bus_id_to_type
[bus
])
344 case MP_BUS_ISA
: /* ISA pin */
346 polarity
= default_ISA_polarity(idx
);
349 case MP_BUS_EISA
: /* EISA pin */
351 polarity
= default_EISA_polarity(idx
);
354 case MP_BUS_PCI
: /* PCI pin */
356 polarity
= default_PCI_polarity(idx
);
359 case MP_BUS_MCA
: /* MCA pin */
361 polarity
= default_MCA_polarity(idx
);
366 printk(KERN_WARNING
"broken BIOS!!\n");
373 case 1: /* high active */
378 case 2: /* reserved */
380 printk(KERN_WARNING
"broken BIOS!!\n");
384 case 3: /* low active */
389 default: /* invalid */
391 printk(KERN_WARNING
"broken BIOS!!\n");
399 static int __init
MPBIOS_trigger(int idx
)
401 int bus
= mp_irqs
[idx
].mpc_srcbus
;
405 * Determine IRQ trigger mode (edge or level sensitive):
407 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
409 case 0: /* conforms, ie. bus-type dependent */
411 switch (mp_bus_id_to_type
[bus
])
413 case MP_BUS_ISA
: /* ISA pin */
415 trigger
= default_ISA_trigger(idx
);
418 case MP_BUS_EISA
: /* EISA pin */
420 trigger
= default_EISA_trigger(idx
);
423 case MP_BUS_PCI
: /* PCI pin */
425 trigger
= default_PCI_trigger(idx
);
428 case MP_BUS_MCA
: /* MCA pin */
430 trigger
= default_MCA_trigger(idx
);
435 printk(KERN_WARNING
"broken BIOS!!\n");
447 case 2: /* reserved */
449 printk(KERN_WARNING
"broken BIOS!!\n");
458 default: /* invalid */
460 printk(KERN_WARNING
"broken BIOS!!\n");
468 static inline int irq_polarity(int idx
)
470 return MPBIOS_polarity(idx
);
473 static inline int irq_trigger(int idx
)
475 return MPBIOS_trigger(idx
);
478 static int __init
pin_2_irq(int idx
, int apic
, int pin
)
481 int bus
= mp_irqs
[idx
].mpc_srcbus
;
484 * Debugging check, we are in big trouble if this message pops up!
486 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
487 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
489 switch (mp_bus_id_to_type
[bus
])
491 case MP_BUS_ISA
: /* ISA pin */
495 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
498 case MP_BUS_PCI
: /* PCI pin */
501 * PCI IRQs are mapped in order
505 irq
+= nr_ioapic_registers
[i
++];
511 printk(KERN_ERR
"unknown bus type %d.\n",bus
);
518 * PCI IRQ command line redirection. Yes, limits are hardcoded.
520 if ((pin
>= 16) && (pin
<= 23)) {
521 if (pirq_entries
[pin
-16] != -1) {
522 if (!pirq_entries
[pin
-16]) {
523 printk(KERN_DEBUG
"disabling PIRQ%d\n", pin
-16);
525 irq
= pirq_entries
[pin
-16];
526 printk(KERN_DEBUG
"using PIRQ%d -> IRQ %d\n",
534 static inline int IO_APIC_irq_trigger(int irq
)
538 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
539 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
540 idx
= find_irq_entry(apic
,pin
,mp_INT
);
541 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
542 return irq_trigger(idx
);
546 * nonexistent IRQs are edge default
551 int irq_vector
[NR_IRQS
] = { FIRST_DEVICE_VECTOR
, 0 };
553 static int __init
assign_irq_vector(int irq
)
555 static int current_vector
= FIRST_DEVICE_VECTOR
, offset
= 0;
556 if (IO_APIC_VECTOR(irq
) > 0)
557 return IO_APIC_VECTOR(irq
);
560 if (current_vector
== SYSCALL_VECTOR
)
563 if (current_vector
> FIRST_SYSTEM_VECTOR
) {
565 current_vector
= FIRST_DEVICE_VECTOR
+ offset
;
568 if (current_vector
== FIRST_SYSTEM_VECTOR
)
569 panic("ran out of interrupt sources!");
571 IO_APIC_VECTOR(irq
) = current_vector
;
572 return current_vector
;
575 extern void (*interrupt
[NR_IRQS
])(void);
576 static struct hw_interrupt_type ioapic_level_irq_type
;
577 static struct hw_interrupt_type ioapic_edge_irq_type
;
579 void __init
setup_IO_APIC_irqs(void)
581 struct IO_APIC_route_entry entry
;
582 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
584 printk(KERN_DEBUG
"init IO_APIC IRQs\n");
586 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
587 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
590 * add it to the IO-APIC irq-routing table:
592 memset(&entry
,0,sizeof(entry
));
594 entry
.delivery_mode
= dest_LowestPrio
;
595 entry
.dest_mode
= 1; /* logical delivery */
596 entry
.mask
= 0; /* enable IRQ */
597 entry
.dest
.logical
.logical_dest
= TARGET_CPUS
;
599 idx
= find_irq_entry(apic
,pin
,mp_INT
);
602 printk(KERN_DEBUG
" IO-APIC (apicid-pin) %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
605 printk(", %d-%d", mp_ioapics
[apic
].mpc_apicid
, pin
);
609 entry
.trigger
= irq_trigger(idx
);
610 entry
.polarity
= irq_polarity(idx
);
612 if (irq_trigger(idx
)) {
615 entry
.dest
.logical
.logical_dest
= TARGET_CPUS
;
618 irq
= pin_2_irq(idx
, apic
, pin
);
619 add_pin_to_irq(irq
, apic
, pin
);
621 if (!apic
&& !IO_APIC_IRQ(irq
))
624 if (IO_APIC_IRQ(irq
)) {
625 vector
= assign_irq_vector(irq
);
626 entry
.vector
= vector
;
628 if (IO_APIC_irq_trigger(irq
))
629 irq_desc
[irq
].handler
= &ioapic_level_irq_type
;
631 irq_desc
[irq
].handler
= &ioapic_edge_irq_type
;
633 set_intr_gate(vector
, interrupt
[irq
]);
635 if (!apic
&& (irq
< 16))
636 disable_8259A_irq(irq
);
638 io_apic_write(apic
, 0x11+2*pin
, *(((int *)&entry
)+1));
639 io_apic_write(apic
, 0x10+2*pin
, *(((int *)&entry
)+0));
644 printk(" not connected.\n");
648 * Set up the 8259A-master output pin as broadcast to all
651 void __init
setup_ExtINT_IRQ0_pin(unsigned int pin
, int vector
)
653 struct IO_APIC_route_entry entry
;
655 memset(&entry
,0,sizeof(entry
));
657 disable_8259A_irq(0);
660 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
663 * We use logical delivery to get the timer IRQ
666 entry
.dest_mode
= 1; /* logical delivery */
667 entry
.mask
= 0; /* unmask IRQ now */
668 entry
.dest
.logical
.logical_dest
= TARGET_CPUS
;
669 entry
.delivery_mode
= dest_LowestPrio
;
672 entry
.vector
= vector
;
675 * The timer IRQ doesnt have to know that behind the
676 * scene we have a 8259A-master in AEOI mode ...
678 irq_desc
[0].handler
= &ioapic_edge_irq_type
;
681 * Add it to the IO-APIC irq-routing table:
683 io_apic_write(0, 0x11+2*pin
, *(((int *)&entry
)+1));
684 io_apic_write(0, 0x10+2*pin
, *(((int *)&entry
)+0));
689 void __init
UNEXPECTED_IO_APIC(void)
691 printk(KERN_WARNING
" WARNING: unexpected IO-APIC, please mail\n");
692 printk(KERN_WARNING
" to linux-smp@vger.kernel.org\n");
695 void __init
print_IO_APIC(void)
698 struct IO_APIC_reg_00 reg_00
;
699 struct IO_APIC_reg_01 reg_01
;
700 struct IO_APIC_reg_02 reg_02
;
702 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
703 for (i
= 0; i
< nr_ioapics
; i
++)
704 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
705 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
708 * We are a bit conservative about what we expect. We have to
709 * know about every hardware change ASAP.
711 printk(KERN_INFO
"testing the IO APIC.......................\n");
713 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
715 *(int *)®_00
= io_apic_read(apic
, 0);
716 *(int *)®_01
= io_apic_read(apic
, 1);
717 if (reg_01
.version
>= 0x10)
718 *(int *)®_02
= io_apic_read(apic
, 2);
721 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
722 printk(KERN_DEBUG
".... register #00: %08X\n", *(int *)®_00
);
723 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.ID
);
724 if (reg_00
.__reserved_1
|| reg_00
.__reserved_2
)
725 UNEXPECTED_IO_APIC();
727 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
728 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.entries
);
729 if ( (reg_01
.entries
!= 0x0f) && /* older (Neptune) boards */
730 (reg_01
.entries
!= 0x17) && /* typical ISA+PCI boards */
731 (reg_01
.entries
!= 0x1b) && /* Compaq Proliant boards */
732 (reg_01
.entries
!= 0x1f) && /* dual Xeon boards */
733 (reg_01
.entries
!= 0x22) && /* bigger Xeon boards */
734 (reg_01
.entries
!= 0x2E) &&
735 (reg_01
.entries
!= 0x3F)
737 UNEXPECTED_IO_APIC();
739 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.version
);
740 if ( (reg_01
.version
!= 0x01) && /* 82489DX IO-APICs */
741 (reg_01
.version
!= 0x10) && /* oldest IO-APICs */
742 (reg_01
.version
!= 0x11) && /* Pentium/Pro IO-APICs */
743 (reg_01
.version
!= 0x13) /* Xeon IO-APICs */
745 UNEXPECTED_IO_APIC();
746 if (reg_01
.__reserved_1
|| reg_01
.__reserved_2
)
747 UNEXPECTED_IO_APIC();
749 if (reg_01
.version
>= 0x10) {
750 printk(KERN_DEBUG
".... register #02: %08X\n", *(int *)®_02
);
751 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.arbitration
);
752 if (reg_02
.__reserved_1
|| reg_02
.__reserved_2
)
753 UNEXPECTED_IO_APIC();
756 printk(KERN_DEBUG
".... IRQ redirection table:\n");
758 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
759 " Stat Dest Deli Vect: \n");
761 for (i
= 0; i
<= reg_01
.entries
; i
++) {
762 struct IO_APIC_route_entry entry
;
764 *(((int *)&entry
)+0) = io_apic_read(apic
, 0x10+i
*2);
765 *(((int *)&entry
)+1) = io_apic_read(apic
, 0x11+i
*2);
767 printk(KERN_DEBUG
" %02x %03X %02X ",
769 entry
.dest
.logical
.logical_dest
,
770 entry
.dest
.physical
.physical_dest
773 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
778 entry
.delivery_status
,
785 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
786 for (i
= 0; i
< NR_IRQS
; i
++) {
787 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
790 printk(KERN_DEBUG
"IRQ%d ", i
);
792 printk("-> %d", entry
->pin
);
795 entry
= irq_2_pin
+ entry
->next
;
800 printk(KERN_INFO
".................................... done.\n");
805 static void print_APIC_bitfield (int base
)
810 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
811 for (i
= 0; i
< 8; i
++) {
812 v
= apic_read(base
+ i
*0x10);
813 for (j
= 0; j
< 32; j
++) {
823 void /*__init*/ print_local_APIC(void * dummy
)
825 unsigned int v
, ver
, maxlvt
;
827 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
828 smp_processor_id(), hard_smp_processor_id());
829 v
= apic_read(APIC_ID
);
830 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
831 v
= apic_read(APIC_LVR
);
832 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
833 ver
= GET_APIC_VERSION(v
);
834 maxlvt
= get_maxlvt();
836 v
= apic_read(APIC_TASKPRI
);
837 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
839 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
840 v
= apic_read(APIC_ARBPRI
);
841 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
842 v
& APIC_ARBPRI_MASK
);
843 v
= apic_read(APIC_PROCPRI
);
844 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
847 v
= apic_read(APIC_EOI
);
848 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
849 v
= apic_read(APIC_LDR
);
850 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
851 v
= apic_read(APIC_DFR
);
852 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
853 v
= apic_read(APIC_SPIV
);
854 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
856 printk(KERN_DEBUG
"... APIC ISR field:\n");
857 print_APIC_bitfield(APIC_ISR
);
858 printk(KERN_DEBUG
"... APIC TMR field:\n");
859 print_APIC_bitfield(APIC_TMR
);
860 printk(KERN_DEBUG
"... APIC IRR field:\n");
861 print_APIC_bitfield(APIC_IRR
);
863 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
864 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
865 apic_write(APIC_ESR
, 0);
866 v
= apic_read(APIC_ESR
);
867 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
870 v
= apic_read(APIC_ICR
);
871 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
872 v
= apic_read(APIC_ICR2
);
873 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
875 v
= apic_read(APIC_LVTT
);
876 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
878 if (maxlvt
> 3) { /* PC is LVT#4. */
879 v
= apic_read(APIC_LVTPC
);
880 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
882 v
= apic_read(APIC_LVT0
);
883 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
884 v
= apic_read(APIC_LVT1
);
885 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
887 if (maxlvt
> 2) { /* ERR is LVT#3. */
888 v
= apic_read(APIC_LVTERR
);
889 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
892 v
= apic_read(APIC_TMICT
);
893 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
894 v
= apic_read(APIC_TMCCT
);
895 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
896 v
= apic_read(APIC_TDCR
);
897 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
901 void print_all_local_APICs (void)
903 smp_call_function(print_local_APIC
, NULL
, 1, 1);
904 print_local_APIC(NULL
);
907 void /*__init*/ print_PIC(void)
909 extern spinlock_t i8259A_lock
;
910 unsigned int v
, flags
;
912 printk(KERN_DEBUG
"\nprinting PIC contents\n");
914 spin_lock_irqsave(&i8259A_lock
, flags
);
916 v
= inb(0xa1) << 8 | inb(0x21);
917 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
919 v
= inb(0xa0) << 8 | inb(0x20);
920 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
924 v
= inb(0xa0) << 8 | inb(0x20);
928 spin_unlock_irqrestore(&i8259A_lock
, flags
);
930 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
932 v
= inb(0x4d1) << 8 | inb(0x4d0);
933 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
936 static void __init
enable_IO_APIC(void)
938 struct IO_APIC_reg_01 reg_01
;
941 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
942 irq_2_pin
[i
].pin
= -1;
943 irq_2_pin
[i
].next
= 0;
946 for (i
= 0; i
< MAX_PIRQS
; i
++)
947 pirq_entries
[i
] = -1;
950 * The number of IO-APIC IRQ registers (== #pins):
952 for (i
= 0; i
< nr_ioapics
; i
++) {
953 *(int *)®_01
= io_apic_read(i
, 1);
954 nr_ioapic_registers
[i
] = reg_01
.entries
+1;
958 * Do not trust the IO-APIC being empty at bootup
964 * Not an __init, needed by the reboot code
966 void disable_IO_APIC(void)
969 * Clear the IO-APIC before rebooting:
973 disconnect_bsp_APIC();
977 * function to set the IO-APIC physical IDs based on the
978 * values stored in the MPC table.
980 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
983 static void __init
setup_ioapic_ids_from_mpc (void)
985 struct IO_APIC_reg_00 reg_00
;
986 unsigned long phys_id_present_map
= phys_cpu_present_map
;
989 unsigned char old_id
;
992 * Set the IOAPIC ID to the value stored in the MPC table.
994 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
996 /* Read the register 0 value */
997 *(int *)®_00
= io_apic_read(apic
, 0);
999 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1001 if (mp_ioapics
[apic
].mpc_apicid
>= 0xf) {
1002 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1003 apic
, mp_ioapics
[apic
].mpc_apicid
);
1004 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1006 mp_ioapics
[apic
].mpc_apicid
= reg_00
.ID
;
1010 * Sanity check, is the ID really free? Every APIC in a
1011 * system must have a unique ID or we get lots of nice
1012 * 'stuck on smp_invalidate_needed IPI wait' messages.
1014 if (phys_id_present_map
& (1 << mp_ioapics
[apic
].mpc_apicid
)) {
1015 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1016 apic
, mp_ioapics
[apic
].mpc_apicid
);
1017 for (i
= 0; i
< 0xf; i
++)
1018 if (!(phys_id_present_map
& (1 << i
)))
1021 panic("Max APIC ID exceeded!\n");
1022 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1024 phys_id_present_map
|= 1 << i
;
1025 mp_ioapics
[apic
].mpc_apicid
= i
;
1029 * We need to adjust the IRQ routing table
1030 * if the ID changed.
1032 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1033 for (i
= 0; i
< mp_irq_entries
; i
++)
1034 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1035 mp_irqs
[i
].mpc_dstapic
1036 = mp_ioapics
[apic
].mpc_apicid
;
1039 * Read the right value from the MPC table and
1040 * write it into the ID register.
1042 printk(KERN_INFO
"...changing IO-APIC physical APIC ID to %d ...",
1043 mp_ioapics
[apic
].mpc_apicid
);
1045 reg_00
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1046 io_apic_write(apic
, 0, *(int *)®_00
);
1051 *(int *)®_00
= io_apic_read(apic
, 0);
1052 if (reg_00
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1053 panic("could not set ID!\n");
1060 * There is a nasty bug in some older SMP boards, their mptable lies
1061 * about the timer IRQ. We do the following to work around the situation:
1063 * - timer IRQ defaults to IO-APIC IRQ
1064 * - if this function detects that timer IRQs are defunct, then we fall
1065 * back to ISA timer IRQs
1067 static int __init
timer_irq_works(void)
1069 unsigned int t1
= jiffies
;
1072 /* Let ten ticks pass... */
1073 mdelay((10 * 1000) / HZ
);
1076 * Expect a few ticks at least, to be sure some possible
1077 * glue logic does not lock up after one or two first
1078 * ticks in a non-ExtINT mode. Also the local APIC
1079 * might have cached one ExtINT interrupt. Finally, at
1080 * least one tick may be lost due to delays.
1082 if (jiffies
- t1
> 4)
1088 static int __init
nmi_irq_works(void)
1090 irq_cpustat_t tmp
[NR_CPUS
];
1093 memcpy(tmp
, irq_stat
, sizeof(tmp
));
1097 for (j
= 0; j
< smp_num_cpus
; j
++) {
1098 cpu
= cpu_logical_map(j
);
1099 if (nmi_count(cpu
) - tmp
[cpu
].__nmi_count
<= 3) {
1100 printk(KERN_WARNING
"CPU#%d NMI appears to be stuck.\n", cpu
);
1108 * In the SMP+IOAPIC case it might happen that there are an unspecified
1109 * number of pending IRQ events unhandled. These cases are very rare,
1110 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1111 * better to do it this way as thus we do not have to be aware of
1112 * 'pending' interrupts in the IRQ path, except at this point.
1115 * Edge triggered needs to resend any interrupt
1116 * that was delayed but this is now handled in the device
1119 #define enable_edge_ioapic_irq unmask_IO_APIC_irq
1121 static void disable_edge_ioapic_irq (unsigned int irq
) { /* nothing */ }
1124 * Starting up a edge-triggered IO-APIC interrupt is
1125 * nasty - we need to make sure that we get the edge.
1126 * If it is already asserted for some reason, we need
1127 * return 1 to indicate that is was pending.
1129 * This is not complete - we should be able to fake
1130 * an edge even if it isn't on the 8259A...
1133 static unsigned int startup_edge_ioapic_irq(unsigned int irq
)
1135 int was_pending
= 0;
1136 unsigned long flags
;
1138 spin_lock_irqsave(&ioapic_lock
, flags
);
1140 disable_8259A_irq(irq
);
1141 if (i8259A_irq_pending(irq
))
1144 __unmask_IO_APIC_irq(irq
);
1145 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1150 #define shutdown_edge_ioapic_irq disable_edge_ioapic_irq
1153 * Once we have recorded IRQ_PENDING already, we can mask the
1154 * interrupt for real. This prevents IRQ storms from unhandled
1157 static void ack_edge_ioapic_irq(unsigned int irq
)
1159 if ((irq_desc
[irq
].status
& (IRQ_PENDING
| IRQ_DISABLED
))
1160 == (IRQ_PENDING
| IRQ_DISABLED
))
1161 mask_IO_APIC_irq(irq
);
1165 static void end_edge_ioapic_irq (unsigned int i
) { /* nothing */ }
1169 * Level triggered interrupts can just be masked,
1170 * and shutting down and starting up the interrupt
1171 * is the same as enabling and disabling them -- except
1172 * with a startup need to return a "was pending" value.
1174 * Level triggered interrupts are special because we
1175 * do not touch any IO-APIC register while handling
1176 * them. We ack the APIC in the end-IRQ handler, not
1177 * in the start-IRQ-handler. Protection against reentrance
1178 * from the same interrupt is still provided, both by the
1179 * generic IRQ layer and by the fact that an unacked local
1180 * APIC does not accept IRQs.
1182 static unsigned int startup_level_ioapic_irq (unsigned int irq
)
1184 unmask_IO_APIC_irq(irq
);
1186 return 0; /* don't check for pending */
1189 #define shutdown_level_ioapic_irq mask_IO_APIC_irq
1190 #define enable_level_ioapic_irq unmask_IO_APIC_irq
1191 #define disable_level_ioapic_irq mask_IO_APIC_irq
1193 static void end_level_ioapic_irq (unsigned int i
)
1198 static void mask_and_ack_level_ioapic_irq (unsigned int i
) { /* nothing */ }
1200 static void set_ioapic_affinity (unsigned int irq
, unsigned long mask
)
1202 unsigned long flags
;
1204 * Only the first 8 bits are valid.
1208 spin_lock_irqsave(&ioapic_lock
, flags
);
1209 __DO_ACTION(1, = mask
, )
1210 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1214 * Level and edge triggered IO-APIC interrupts need different handling,
1215 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1216 * handled with the level-triggered descriptor, but that one has slightly
1217 * more overhead. Level-triggered interrupts cannot be handled with the
1218 * edge-triggered handler, without risking IRQ storms and other ugly
1222 static struct hw_interrupt_type ioapic_edge_irq_type
= {
1224 startup_edge_ioapic_irq
,
1225 shutdown_edge_ioapic_irq
,
1226 enable_edge_ioapic_irq
,
1227 disable_edge_ioapic_irq
,
1228 ack_edge_ioapic_irq
,
1229 end_edge_ioapic_irq
,
1230 set_ioapic_affinity
,
1233 static struct hw_interrupt_type ioapic_level_irq_type
= {
1235 startup_level_ioapic_irq
,
1236 shutdown_level_ioapic_irq
,
1237 enable_level_ioapic_irq
,
1238 disable_level_ioapic_irq
,
1239 mask_and_ack_level_ioapic_irq
,
1240 end_level_ioapic_irq
,
1241 set_ioapic_affinity
,
1244 static inline void init_IO_APIC_traps(void)
1249 * NOTE! The local APIC isn't very good at handling
1250 * multiple interrupts at the same interrupt level.
1251 * As the interrupt level is determined by taking the
1252 * vector number and shifting that right by 4, we
1253 * want to spread these out a bit so that they don't
1254 * all fall in the same interrupt level.
1256 * Also, we've got to be careful not to trash gate
1257 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1259 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1260 if (IO_APIC_IRQ(irq
) && !IO_APIC_VECTOR(irq
)) {
1262 * Hmm.. We don't have an entry for this,
1263 * so default to an old-fashioned 8259
1264 * interrupt if we can..
1267 make_8259A_irq(irq
);
1269 /* Strange. Oh, well.. */
1270 irq_desc
[irq
].handler
= &no_irq_type
;
1275 static void enable_lapic_irq (unsigned int irq
)
1279 v
= apic_read(APIC_LVT0
);
1280 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
1283 static void disable_lapic_irq (unsigned int irq
)
1287 v
= apic_read(APIC_LVT0
);
1288 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
1291 static void ack_lapic_irq (unsigned int irq
)
1296 static void end_lapic_irq (unsigned int i
) { /* nothing */ }
1298 static struct hw_interrupt_type lapic_irq_type
= {
1300 NULL
, /* startup_irq() not used for IRQ0 */
1301 NULL
, /* shutdown_irq() not used for IRQ0 */
1308 static void enable_NMI_through_LVT0 (void * dummy
)
1310 unsigned int v
, ver
;
1312 ver
= apic_read(APIC_LVR
);
1313 ver
= GET_APIC_VERSION(ver
);
1314 v
= APIC_DM_NMI
; /* unmask and set to NMI */
1315 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
1316 v
|= APIC_LVT_LEVEL_TRIGGER
;
1317 apic_write_around(APIC_LVT0
, v
);
1320 static void setup_nmi (void)
1323 * Dirty trick to enable the NMI watchdog ...
1324 * We put the 8259A master into AEOI mode and
1325 * unmask on all local APICs LVT0 as NMI.
1327 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1328 * is from Maciej W. Rozycki - so we do not have to EOI from
1329 * the NMI handler or the timer interrupt.
1331 printk(KERN_INFO
"activating NMI Watchdog ...");
1333 smp_call_function(enable_NMI_through_LVT0
, NULL
, 1, 1);
1334 enable_NMI_through_LVT0(NULL
);
1340 * This looks a bit hackish but it's about the only one way of sending
1341 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1342 * not support the ExtINT mode, unfortunately. We need to send these
1343 * cycles as some i82489DX-based boards have glue logic that keeps the
1344 * 8259A interrupt line asserted until INTA. --macro
1346 static inline void unlock_ExtINT_logic(void)
1349 struct IO_APIC_route_entry entry0
, entry1
;
1350 unsigned char save_control
, save_freq_select
;
1352 pin
= find_isa_irq_pin(8, mp_INT
);
1356 *(((int *)&entry0
) + 1) = io_apic_read(0, 0x11 + 2 * pin
);
1357 *(((int *)&entry0
) + 0) = io_apic_read(0, 0x10 + 2 * pin
);
1358 clear_IO_APIC_pin(0, pin
);
1360 memset(&entry1
, 0, sizeof(entry1
));
1362 entry1
.dest_mode
= 0; /* physical delivery */
1363 entry1
.mask
= 0; /* unmask IRQ now */
1364 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
1365 entry1
.delivery_mode
= dest_ExtINT
;
1366 entry1
.polarity
= entry0
.polarity
;
1370 io_apic_write(0, 0x11 + 2 * pin
, *(((int *)&entry1
) + 1));
1371 io_apic_write(0, 0x10 + 2 * pin
, *(((int *)&entry1
) + 0));
1373 save_control
= CMOS_READ(RTC_CONTROL
);
1374 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
1375 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
1377 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
1382 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
1386 CMOS_WRITE(save_control
, RTC_CONTROL
);
1387 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
1388 clear_IO_APIC_pin(0, pin
);
1390 io_apic_write(0, 0x11 + 2 * pin
, *(((int *)&entry0
) + 1));
1391 io_apic_write(0, 0x10 + 2 * pin
, *(((int *)&entry0
) + 0));
1395 * This code may look a bit paranoid, but it's supposed to cooperate with
1396 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1397 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1398 * fanatically on his truly buggy board.
1400 static inline void check_timer(void)
1402 extern int timer_ack
;
1407 * get/set the timer IRQ vector:
1409 disable_8259A_irq(0);
1410 vector
= assign_irq_vector(0);
1411 set_intr_gate(vector
, interrupt
[0]);
1414 * Subtle, code in do_timer_interrupt() expects an AEOI
1415 * mode for the 8259A whenever interrupts are routed
1416 * through I/O APICs. Also IRQ0 has to be enabled in
1417 * the 8259A which implies the virtual wire has to be
1418 * disabled in the local APIC.
1420 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1423 enable_8259A_irq(0);
1425 pin1
= find_isa_irq_pin(0, mp_INT
);
1426 pin2
= find_isa_irq_pin(0, mp_ExtINT
);
1428 printk(KERN_INFO
"..TIMER: vector=%d pin1=%d pin2=%d\n", vector
, pin1
, pin2
);
1432 * Ok, does IRQ0 through the IOAPIC work?
1434 unmask_IO_APIC_irq(0);
1435 if (timer_irq_works()) {
1437 disable_8259A_irq(0);
1439 enable_8259A_irq(0);
1444 clear_IO_APIC_pin(0, pin1
);
1445 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1448 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
1450 printk("\n..... (found pin %d) ...", pin2
);
1452 * legacy devices should be connected to IO APIC #0
1454 setup_ExtINT_IRQ0_pin(pin2
, vector
);
1455 if (timer_irq_works()) {
1464 * Cleanup, just in case ...
1466 clear_IO_APIC_pin(0, pin2
);
1468 printk(" failed.\n");
1471 printk(KERN_WARNING
"timer doesnt work through the IO-APIC - disabling NMI Watchdog!\n");
1475 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
1477 disable_8259A_irq(0);
1478 irq_desc
[0].handler
= &lapic_irq_type
;
1479 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
1480 enable_8259A_irq(0);
1482 if (timer_irq_works()) {
1483 printk(" works.\n");
1486 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
1487 printk(" failed.\n");
1489 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
1493 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
1495 unlock_ExtINT_logic();
1497 if (timer_irq_works()) {
1498 printk(" works.\n");
1501 printk(" failed :(.\n");
1502 panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
1507 * IRQ's that are handled by the old PIC in all cases:
1508 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1509 * Linux doesn't really care, as it's not actually used
1510 * for any interrupt handling anyway.
1511 * - IRQ13 is the FPU error IRQ, and may be connected
1512 * directly from the FPU to the old PIC. Linux doesn't
1513 * really care, because Linux doesn't want to use IRQ13
1514 * anyway (exception 16 is the proper FPU error signal)
1516 * Additionally, something is definitely wrong with irq9
1519 #define PIC_IRQS ((1<<2)|(1<<13))
1521 void __init
setup_IO_APIC(void)
1525 io_apic_irqs
= ~PIC_IRQS
;
1526 printk("ENABLING IO-APIC IRQs\n");
1529 * Set up the IO-APIC IRQ routing table by parsing the MP-BIOS
1532 setup_ioapic_ids_from_mpc();
1534 setup_IO_APIC_irqs();
1535 init_IO_APIC_traps();
1542 * This initializes the IO-APIC and APIC hardware if this is
1545 void IO_APIC_init_uniprocessor (void)
1547 if (!smp_found_config
)
1552 setup_APIC_clocks();