2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
14 #include <linux/config.h>
15 #include <linux/init.h>
18 #include <linux/irq.h>
19 #include <linux/delay.h>
20 #include <linux/bootmem.h>
21 #include <linux/smp_lock.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
28 #include <asm/mpspec.h>
29 #include <asm/pgalloc.h>
31 int prof_multiplier
[NR_CPUS
] = { 1, };
32 int prof_old_multiplier
[NR_CPUS
] = { 1, };
33 int prof_counter
[NR_CPUS
] = { 1, };
37 unsigned int v
, ver
, maxlvt
;
39 v
= apic_read(APIC_LVR
);
40 ver
= GET_APIC_VERSION(v
);
41 /* 82489DXs do not report # of LVT entries. */
42 maxlvt
= APIC_INTEGRATED(ver
) ? GET_APIC_MAXLVT(v
) : 2;
46 static void clear_local_APIC(void)
51 maxlvt
= get_maxlvt();
54 * Careful: we have to set masks only first to deassert
55 * any level-triggered sources.
57 v
= apic_read(APIC_LVTT
);
58 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
59 v
= apic_read(APIC_LVT0
);
60 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
61 v
= apic_read(APIC_LVT1
);
62 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
64 v
= apic_read(APIC_LVTERR
);
65 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
68 v
= apic_read(APIC_LVTPC
);
69 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
73 * Clean APIC state for other OSs:
75 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
76 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
77 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
79 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
81 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
84 void __init
connect_bsp_APIC(void)
88 * Do not trust the local APIC being empty at bootup.
92 * PIC mode, enable symmetric IO mode in the IMCR,
93 * i.e. connect BSP's local APIC to INT and NMI lines.
95 printk("leaving PIC mode, enabling symmetric IO mode.\n");
101 void disconnect_bsp_APIC(void)
105 * Put the board back into PIC mode (has an effect
106 * only on certain older boards). Note that APIC
107 * interrupts, including IPIs, won't work beyond
108 * this point! The only exception are INIT IPIs.
110 printk("disabling symmetric IO mode, entering PIC mode.\n");
116 void disable_local_APIC(void)
123 * Disable APIC (implies clearing of registers
126 value
= apic_read(APIC_SPIV
);
128 apic_write_around(APIC_SPIV
, value
);
132 * This is to verify that we're looking at a real local APIC.
133 * Check these against your board if the CPUs aren't getting
134 * started for no apparent reason.
136 int __init
verify_local_APIC(void)
138 unsigned int reg0
, reg1
;
141 * The version register is read-only in a real APIC.
143 reg0
= apic_read(APIC_LVR
);
144 Dprintk("Getting VERSION: %x\n", reg0
);
145 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
146 reg1
= apic_read(APIC_LVR
);
147 Dprintk("Getting VERSION: %x\n", reg1
);
150 * The two version reads above should print the same
151 * numbers. If the second one is different, then we
152 * poke at a non-APIC.
158 * Check if the version looks reasonably.
160 reg1
= GET_APIC_VERSION(reg0
);
161 if (reg1
== 0x00 || reg1
== 0xff)
164 if (reg1
< 0x02 || reg1
== 0xff)
168 * The ID register is read/write in a real APIC.
170 reg0
= apic_read(APIC_ID
);
171 Dprintk("Getting ID: %x\n", reg0
);
172 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
173 reg1
= apic_read(APIC_ID
);
174 Dprintk("Getting ID: %x\n", reg1
);
175 apic_write(APIC_ID
, reg0
);
176 if (reg1
!= (reg0
^ APIC_ID_MASK
))
180 * The next two are just to see if we have sane values.
181 * They're only really relevant if we're in Virtual Wire
182 * compatibility mode, but most boxes are anymore.
184 reg0
= apic_read(APIC_LVT0
);
185 Dprintk("Getting LVT0: %x\n", reg0
);
186 reg1
= apic_read(APIC_LVT1
);
187 Dprintk("Getting LVT1: %x\n", reg1
);
192 void __init
sync_Arb_IDs(void)
197 apic_wait_icr_idle();
199 Dprintk("Synchronizing Arb IDs.\n");
200 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
204 extern void __error_in_apic_c (void);
206 void __init
setup_local_APIC (void)
208 unsigned long value
, ver
, maxlvt
;
210 value
= apic_read(APIC_LVR
);
211 ver
= GET_APIC_VERSION(value
);
213 if ((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f)
217 * Double-check wether this APIC is really registered.
219 if (!test_bit(GET_APIC_ID(apic_read(APIC_ID
)), &phys_cpu_present_map
))
223 * Intel recommends to set DFR, LDR and TPR before enabling
224 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
225 * document number 292116). So here it goes...
229 * Put the APIC into flat delivery mode.
230 * Must be "all ones" explicitly for 82489DX.
232 apic_write_around(APIC_DFR
, 0xffffffff);
235 * Set up the logical destination ID.
237 value
= apic_read(APIC_LDR
);
238 value
&= ~APIC_LDR_MASK
;
239 value
|= (1<<(smp_processor_id()+24));
240 apic_write_around(APIC_LDR
, value
);
243 * Set Task Priority to 'accept all'. We never change this
246 value
= apic_read(APIC_TASKPRI
);
247 value
&= ~APIC_TPRI_MASK
;
248 apic_write_around(APIC_TASKPRI
, value
);
251 * Now that we are all set up, enable the APIC
253 value
= apic_read(APIC_SPIV
);
254 value
&= ~APIC_VECTOR_MASK
;
261 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
262 * certain networking cards. If high frequency interrupts are
263 * happening on a particular IOAPIC pin, plus the IOAPIC routing
264 * entry is masked/unmasked at a high rate as well then sooner or
265 * later IOAPIC line gets 'stuck', no more interrupts are received
266 * from the device. If focus CPU is disabled then the hang goes
269 * [ This bug can be reproduced easily with a level-triggered
270 * PCI Ne2000 networking cards and PII/PIII processors, dual
274 /* Enable focus processor (bit==0) */
277 /* Disable focus processor (bit==1) */
281 * Set spurious IRQ vector
283 value
|= SPURIOUS_APIC_VECTOR
;
284 apic_write_around(APIC_SPIV
, value
);
289 * set up through-local-APIC on the BP's LINT0. This is not
290 * strictly necessery in pure symmetric-IO mode, but sometimes
291 * we delegate interrupts to the 8259A.
294 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
296 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
297 if (!smp_processor_id() && (pic_mode
|| !value
)) {
298 value
= APIC_DM_EXTINT
;
299 printk("enabled ExtINT on CPU#%d\n", smp_processor_id());
301 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
302 printk("masked ExtINT on CPU#%d\n", smp_processor_id());
304 apic_write_around(APIC_LVT0
, value
);
307 * only the BP should see the LINT1 NMI signal, obviously.
309 if (!smp_processor_id())
312 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
313 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
314 value
|= APIC_LVT_LEVEL_TRIGGER
;
315 apic_write_around(APIC_LVT1
, value
);
317 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
318 maxlvt
= get_maxlvt();
319 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
320 apic_write(APIC_ESR
, 0);
321 value
= apic_read(APIC_ESR
);
322 printk("ESR value before enabling vector: %08lx\n", value
);
324 value
= ERROR_APIC_VECTOR
; // enables sending errors
325 apic_write_around(APIC_LVTERR
, value
);
327 * spec says clear errors after enabling vector.
330 apic_write(APIC_ESR
, 0);
331 value
= apic_read(APIC_ESR
);
332 printk("ESR value after enabling vector: %08lx\n", value
);
334 printk("No ESR for 82489DX.\n");
337 void __init
init_apic_mappings(void)
339 unsigned long apic_phys
;
341 if (smp_found_config
) {
342 apic_phys
= mp_lapic_addr
;
345 * set up a fake all zeroes page to simulate the
346 * local APIC and another one for the IO-APIC. We
347 * could use the real zero-page, but it's safer
348 * this way if some buggy code writes to this page ...
350 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
351 apic_phys
= __pa(apic_phys
);
353 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
354 Dprintk("mapped APIC to %08lx (%08lx)\n", APIC_BASE
, apic_phys
);
357 * Fetch the APIC ID of the BSP in case we have a
358 * default configuration (or the MP table is broken).
360 if (boot_cpu_id
== -1U)
361 boot_cpu_id
= GET_APIC_ID(apic_read(APIC_ID
));
363 #ifdef CONFIG_X86_IO_APIC
365 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
368 for (i
= 0; i
< nr_ioapics
; i
++) {
369 if (smp_found_config
) {
370 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
372 ioapic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
373 ioapic_phys
= __pa(ioapic_phys
);
375 set_fixmap_nocache(idx
, ioapic_phys
);
376 Dprintk("mapped IOAPIC to %08lx (%08lx)\n",
377 __fix_to_virt(idx
), ioapic_phys
);
385 * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
386 * per second. We assume that the caller has already set up the local
389 * The APIC timer is not exactly sync with the external timer chip, it
390 * closely follows bus clocks.
394 * The timer chip is already set up at HZ interrupts per second here,
395 * but we do not accept timer interrupts yet. We only allow the BP
398 static unsigned int __init
get_8254_timer_count(void)
400 extern spinlock_t i8253_lock
;
405 spin_lock_irqsave(&i8253_lock
, flags
);
409 count
|= inb_p(0x40) << 8;
411 spin_unlock_irqrestore(&i8253_lock
, flags
);
416 void __init
wait_8254_wraparound(void)
418 unsigned int curr_count
, prev_count
=~0;
421 curr_count
= get_8254_timer_count();
424 prev_count
= curr_count
;
425 curr_count
= get_8254_timer_count();
426 delta
= curr_count
-prev_count
;
429 * This limit for delta seems arbitrary, but it isn't, it's
430 * slightly above the level of error a buggy Mercury/Neptune
431 * chipset timer can cause.
434 } while (delta
< 300);
438 * This function sets up the local APIC timer, with a timeout of
439 * 'clocks' APIC bus clock. During calibration we actually call
440 * this function twice on the boot CPU, once with a bogus timeout
441 * value, second time for real. The other (noncalibrating) CPUs
442 * call this function only once, with the real, calibrated value.
444 * We do reads before writes even if unnecessary, to get around the
445 * P5 APIC double write bug.
448 #define APIC_DIVISOR 16
450 void __setup_APIC_LVTT(unsigned int clocks
)
452 unsigned int lvtt1_value
, tmp_value
;
454 lvtt1_value
= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
) |
455 APIC_LVT_TIMER_PERIODIC
| LOCAL_TIMER_VECTOR
;
456 apic_write_around(APIC_LVTT
, lvtt1_value
);
461 tmp_value
= apic_read(APIC_TDCR
);
462 apic_write_around(APIC_TDCR
, (tmp_value
463 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
466 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
469 void setup_APIC_timer(void * data
)
471 unsigned int clocks
= (unsigned int) data
, slice
, t0
, t1
;
478 * ok, Intel has some smart code in their APIC that knows
479 * if a CPU was in 'hlt' lowpower mode, and this increases
480 * its APIC arbitration priority. To avoid the external timer
481 * IRQ APIC event being in synchron with the APIC clock we
482 * introduce an interrupt skew to spread out timer events.
484 * The number of slices within a 'big' timeslice is smp_num_cpus+1
487 slice
= clocks
/ (smp_num_cpus
+1);
488 printk("cpu: %d, clocks: %d, slice: %d\n",
489 smp_processor_id(), clocks
, slice
);
492 * Wait for IRQ0's slice:
494 wait_8254_wraparound();
496 __setup_APIC_LVTT(clocks
);
498 t0
= apic_read(APIC_TMICT
)*APIC_DIVISOR
;
499 /* Wait till TMCCT gets reloaded from TMICT... */
501 t1
= apic_read(APIC_TMCCT
)*APIC_DIVISOR
;
502 delta
= (int)(t0
- t1
- slice
*(smp_processor_id()+1));
503 } while (delta
>= 0);
504 /* Now wait for our slice for real. */
506 t1
= apic_read(APIC_TMCCT
)*APIC_DIVISOR
;
507 delta
= (int)(t0
- t1
- slice
*(smp_processor_id()+1));
510 __setup_APIC_LVTT(clocks
);
512 printk("CPU%d<T0:%d,T1:%d,D:%d,S:%d,C:%d>\n",
513 smp_processor_id(), t0
, t1
, delta
, slice
, clocks
);
515 __restore_flags(flags
);
519 * In this function we calibrate APIC bus clocks to the external
520 * timer. Unfortunately we cannot use jiffies and the timer irq
521 * to calibrate, since some later bootup code depends on getting
522 * the first irq? Ugh.
524 * We want to do the calibration only once since we
525 * want to have local timer irqs syncron. CPUs connected
526 * by the same APIC bus have the very same bus frequency.
527 * And we want to have irqs off anyways, no accidental
531 int __init
calibrate_APIC_clock(void)
533 unsigned long long t1
= 0, t2
= 0;
537 const int LOOPS
= HZ
/10;
539 printk("calibrating APIC timer ...\n");
542 * Put whatever arbitrary (but long enough) timeout
543 * value into the APIC clock, we just want to get the
544 * counter running for calibration.
546 __setup_APIC_LVTT(1000000000);
549 * The timer chip counts down to zero. Let's wait
550 * for a wraparound to start exact measurement:
551 * (the current tick might have been already half done)
554 wait_8254_wraparound();
557 * We wrapped around just now. Let's start:
561 tt1
= apic_read(APIC_TMCCT
);
564 * Let's wait LOOPS wraprounds:
566 for (i
= 0; i
< LOOPS
; i
++)
567 wait_8254_wraparound();
569 tt2
= apic_read(APIC_TMCCT
);
574 * The APIC bus clock counter is 32 bits only, it
575 * might have overflown, but note that we use signed
576 * longs, thus no extra care needed.
578 * underflown to be exact, as the timer counts down ;)
581 result
= (tt1
-tt2
)*APIC_DIVISOR
/LOOPS
;
584 printk("..... CPU clock speed is %ld.%04ld MHz.\n",
585 ((long)(t2
-t1
)/LOOPS
)/(1000000/HZ
),
586 ((long)(t2
-t1
)/LOOPS
)%(1000000/HZ
));
588 printk("..... host bus clock speed is %ld.%04ld MHz.\n",
590 result
%(1000000/HZ
));
595 static unsigned int calibration_result
;
597 void __init
setup_APIC_clocks (void)
601 calibration_result
= calibrate_APIC_clock();
603 * Now set up the timer for real.
605 setup_APIC_timer((void *)calibration_result
);
609 /* and update all other cpus */
610 smp_call_function(setup_APIC_timer
, (void *)calibration_result
, 1, 1);
614 * the frequency of the profiling timer can be changed
615 * by writing a multiplier value into /proc/profile.
617 int setup_profiling_timer(unsigned int multiplier
)
622 * Sanity check. [at least 500 APIC cycles should be
623 * between APIC interrupts as a rule of thumb, to avoid
626 if ( (!multiplier
) || (calibration_result
/multiplier
< 500))
630 * Set the new multiplier for each CPU. CPUs don't start using the
631 * new values until the next timer interrupt in which they do process
632 * accounting. At that time they also adjust their APIC timers
635 for (i
= 0; i
< NR_CPUS
; ++i
)
636 prof_multiplier
[i
] = multiplier
;
644 * Local timer interrupt handler. It does both profiling and
645 * process statistics/rescheduling.
647 * We do profiling in every local tick, statistics/rescheduling
648 * happen only every 'profiling multiplier' ticks. The default
649 * multiplier is 1 and it can be changed by writing the new multiplier
650 * value into /proc/profile.
653 inline void smp_local_timer_interrupt(struct pt_regs
* regs
)
655 int user
= user_mode(regs
);
656 int cpu
= smp_processor_id();
659 * The profiling function is SMP safe. (nothing can mess
660 * around with "current", and the profiling counters are
661 * updated with atomic operations). This is especially
662 * useful with a profiling multiplier != 1
665 x86_do_profile(regs
->eip
);
667 if (--prof_counter
[cpu
] <= 0) {
669 * The multiplier may have changed since the last time we got
670 * to this point as a result of the user writing to
671 * /proc/profile. In this case we need to adjust the APIC
674 * Interrupts are already masked off at this point.
676 prof_counter
[cpu
] = prof_multiplier
[cpu
];
677 if (prof_counter
[cpu
] != prof_old_multiplier
[cpu
]) {
678 __setup_APIC_LVTT(calibration_result
/prof_counter
[cpu
]);
679 prof_old_multiplier
[cpu
] = prof_counter
[cpu
];
683 update_process_times(user
);
688 * We take the 'long' return path, and there every subsystem
689 * grabs the apropriate locks (kernel lock/ irq lock).
691 * we might want to decouple profiling from the 'long path',
692 * and do the profiling totally in assembly.
694 * Currently this isn't too much of an issue (performance wise),
695 * we can take more than 100K local irqs per second on a 100 MHz P5.
700 * Local APIC timer interrupt. This is the most natural way for doing
701 * local interrupts, but local timer interrupts can be emulated by
702 * broadcast interrupts too. [in case the hw doesnt support APIC timers]
704 * [ if a single-CPU system runs an SMP kernel then we call the local
705 * interrupt as well. Thus we cannot inline the local irq ... ]
707 unsigned int apic_timer_irqs
[NR_CPUS
];
709 void smp_apic_timer_interrupt(struct pt_regs
* regs
)
711 int cpu
= smp_processor_id();
714 * the NMI deadlock-detector uses this.
716 apic_timer_irqs
[cpu
]++;
719 * NOTE! We'd better ACK the irq immediately,
720 * because timer handling can be slow.
724 * update_process_times() expects us to have done irq_enter().
725 * Besides, if we don't timer interrupts ignore the global
726 * interrupt lock, which is the WrongThing (tm) to do.
729 smp_local_timer_interrupt(regs
);
734 * This interrupt should _never_ happen with our APIC/SMP architecture
736 asmlinkage
void smp_spurious_interrupt(void)
741 * Check if this really is a spurious interrupt and ACK it
742 * if it is a vectored one. Just in case...
743 * Spurious interrupts should not be ACKed.
745 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
746 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
749 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
750 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, should never happen.\n",
755 * This interrupt should never happen with our APIC/SMP architecture
758 asmlinkage
void smp_error_interrupt(void)
762 /* First tickle the hardware, only then report what went on. -- REW */
763 v
= apic_read(APIC_ESR
);
764 apic_write(APIC_ESR
, 0);
765 v1
= apic_read(APIC_ESR
);
769 /* Here is what the APIC error bits mean:
773 3: Receive accept error
775 5: Send illegal vector
776 6: Received illegal vector
777 7: Illegal register address
779 printk (KERN_ERR
"APIC error on CPU%d: %02lx(%02lx)\n",
780 smp_processor_id(), v
, v1
);