include/linux/cyclades.h

   1 /* $Revision: 3.0 $$Date: 1998/11/02 14:20:59 $
   2  * linux/include/linux/cyclades.h
   3  *
   4  * This file was initially written by
   5  * Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by
   6  * Ivan Passos <ivan@cyclades.com>.
   7  *
   8  * This file contains the general definitions for the cyclades.c driver
   9  *$Log: cyclades.h,v $
  10  *Revision 3.1  2000/04/19 18:52:52  ivan
  11  *converted address fields to unsigned long and added fields for physical
  12  *addresses on cyclades_card structure;
  13  *
  14  *Revision 3.0  1998/11/02 14:20:59  ivan
  15  *added nports field on cyclades_card structure;
  16  *
  17  *Revision 2.5  1998/08/03 16:57:01  ivan
  18  *added cyclades_idle_stats structure;
  19  *
  20  *Revision 2.4  1998/06/01 12:09:53  ivan
  21  *removed closing_wait2 from cyclades_port structure;
  22  *
  23  *Revision 2.3  1998/03/16 18:01:12  ivan
  24  *changes in the cyclades_port structure to get it closer to the
  25  *standard serial port structure;
  26  *added constants for new ioctls;
  27  *
  28  *Revision 2.2  1998/02/17 16:50:00  ivan
  29  *changes in the cyclades_port structure (addition of shutdown_wait and
  30  *chip_rev variables);
  31  *added constants for new ioctls and for CD1400 rev. numbers.
  32  *
  33  *Revision 2.1  1997/10/24 16:03:00  ivan
  34  *added rflow (which allows enabling the CD1400 special flow control
  35  *feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to
  36  *cyclades_port structure;
  37  *added Alpha support
  38  *
  39  *Revision 2.0  1997/06/30 10:30:00  ivan
  40  *added some new doorbell command constants related to IOCTLW and
  41  *UART error signaling
  42  *
  43  *Revision 1.8  1997/06/03 15:30:00  ivan
  44  *added constant ZFIRM_HLT
  45  *added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin)
  46  *
  47  *Revision 1.7  1997/03/26 10:30:00  daniel
  48  *new entries at the end of cyclades_port struct to reallocate
  49  *variables illegally allocated within card memory.
  50  *
  51  *Revision 1.6  1996/09/09 18:35:30  bentson
  52  *fold in changes for Cyclom-Z -- including structures for
  53  *communicating with board as well modest changes to original
  54  *structures to support new features.
  55  *
  56  *Revision 1.5  1995/11/13 21:13:31  bentson
  57  *changes suggested by Michael Chastain <mec@duracef.shout.net>
  58  *to support use of this file in non-kernel applications
  59  *
  60  *
  61  */
  62
  63 #ifndef _LINUX_CYCLADES_H
  64 #define _LINUX_CYCLADES_H
  65
  66 struct cyclades_monitor {
  67         unsigned long           int_count;
  68         unsigned long           char_count;
  69         unsigned long           char_max;
  70         unsigned long           char_last;
  71 };
  72
  73 /*
  74  * These stats all reflect activity since the device was last initialized.
  75  * (i.e., since the port was opened with no other processes already having it
  76  * open)
  77  */
  78 struct cyclades_idle_stats {
  79     time_t         in_use;      /* Time device has been in use (secs) */
  80     time_t         recv_idle;   /* Time since last char received (secs) */
  81     time_t         xmit_idle;   /* Time since last char transmitted (secs) */
  82     unsigned long  recv_bytes;  /* Bytes received */
  83     unsigned long  xmit_bytes;  /* Bytes transmitted */
  84     unsigned long  overruns;    /* Input overruns */
  85     unsigned long  frame_errs;  /* Input framing errors */
  86     unsigned long  parity_errs; /* Input parity errors */
  87 };
  88
  89 #define CYCLADES_MAGIC  0x4359
  90
  91 #define CYGETMON                0x435901
  92 #define CYGETTHRESH             0x435902
  93 #define CYSETTHRESH             0x435903
  94 #define CYGETDEFTHRESH          0x435904
  95 #define CYSETDEFTHRESH          0x435905
  96 #define CYGETTIMEOUT            0x435906
  97 #define CYSETTIMEOUT            0x435907
  98 #define CYGETDEFTIMEOUT         0x435908
  99 #define CYSETDEFTIMEOUT         0x435909
 100 #define CYSETRFLOW              0x43590a
 101 #define CYGETRFLOW              0x43590b
 102 #define CYSETRTSDTR_INV         0x43590c
 103 #define CYGETRTSDTR_INV         0x43590d
 104 #define CYZSETPOLLCYCLE         0x43590e
 105 #define CYZGETPOLLCYCLE         0x43590f
 106 #define CYGETCD1400VER          0x435910
 107 #define CYGETCARDINFO           0x435911
 108 #define CYSETWAIT               0x435912
 109 #define CYGETWAIT               0x435913
 110
 111 /*************** CYCLOM-Z ADDITIONS ***************/
 112
 113 #define CZIOC           ('M' << 8)
 114 #define CZ_NBOARDS      (CZIOC|0xfa)
 115 #define CZ_BOOT_START   (CZIOC|0xfb)
 116 #define CZ_BOOT_DATA    (CZIOC|0xfc)
 117 #define CZ_BOOT_END     (CZIOC|0xfd)
 118 #define CZ_TEST         (CZIOC|0xfe)
 119
 120 #define CZ_DEF_POLL     (HZ/25)
 121
 122 #define MAX_BOARD       4       /* Max number of boards */
 123 #define MAX_DEV         256     /* Max number of ports total */
 124 #define CYZ_MAX_SPEED   921600
 125
 126 #define CYZ_FIFO_SIZE   16
 127
 128 #define CYZ_BOOT_NWORDS 0x100
 129 struct CYZ_BOOT_CTRL {
 130         unsigned short  nboard;
 131         int             status[MAX_BOARD];
 132         int             nchannel[MAX_BOARD];
 133         int             fw_rev[MAX_BOARD];
 134         unsigned long   offset;
 135         unsigned long   data[CYZ_BOOT_NWORDS];
 136 };
 137
 138
 139 #ifndef DP_WINDOW_SIZE
 140 /* #include "cyclomz.h" */
 141 /****************** ****************** *******************/
 142 /*
 143  *      The data types defined below are used in all ZFIRM interface
 144  *      data structures. They accomodate differences between HW
 145  *      architectures and compilers.
 146  */
 147
 148 #if defined(__alpha__)
 149 typedef unsigned long   ucdouble;       /* 64 bits, unsigned */
 150 typedef unsigned int    uclong;         /* 32 bits, unsigned */
 151 #else
 152 typedef unsigned long   uclong;         /* 32 bits, unsigned */
 153 #endif
 154 typedef unsigned short  ucshort;        /* 16 bits, unsigned */
 155 typedef unsigned char   ucchar;         /* 8 bits, unsigned */
 156
 157 /*
 158  *      Memory Window Sizes
 159  */
 160
 161 #define DP_WINDOW_SIZE          (0x00080000)    /* window size 512 Kb */
 162 #define ZE_DP_WINDOW_SIZE       (0x00100000)    /* window size 1 Mb (Ze and
 163                                                   8Zo V.2 */
 164 #define CTRL_WINDOW_SIZE        (0x00000080)    /* runtime regs 128 bytes */
 165
 166 /*
 167  *      CUSTOM_REG - Cyclom-Z/PCI Custom Registers Set. The driver
 168  *      normally will access only interested on the fpga_id, fpga_version,
 169  *      start_cpu and stop_cpu.
 170  */
 171
 172 struct  CUSTOM_REG {
 173         uclong  fpga_id;                /* FPGA Identification Register */
 174         uclong  fpga_version;           /* FPGA Version Number Register */
 175         uclong  cpu_start;              /* CPU start Register (write) */
 176         uclong  cpu_stop;               /* CPU stop Register (write) */
 177         uclong  misc_reg;               /* Miscelaneous Register */
 178         uclong  idt_mode;               /* IDT mode Register */
 179         uclong  uart_irq_status;        /* UART IRQ status Register */
 180         uclong  clear_timer0_irq;       /* Clear timer interrupt Register */
 181         uclong  clear_timer1_irq;       /* Clear timer interrupt Register */
 182         uclong  clear_timer2_irq;       /* Clear timer interrupt Register */
 183         uclong  test_register;          /* Test Register */
 184         uclong  test_count;             /* Test Count Register */
 185         uclong  timer_select;           /* Timer select register */
 186         uclong  pr_uart_irq_status;     /* Prioritized UART IRQ stat Reg */
 187         uclong  ram_wait_state;         /* RAM wait-state Register */
 188         uclong  uart_wait_state;        /* UART wait-state Register */
 189         uclong  timer_wait_state;       /* timer wait-state Register */
 190         uclong  ack_wait_state;         /* ACK wait State Register */
 191 };
 192
 193 /*
 194  *      RUNTIME_9060 - PLX PCI9060ES local configuration and shared runtime
 195  *      registers. This structure can be used to access the 9060 registers
 196  *      (memory mapped).
 197  */
 198
 199 struct RUNTIME_9060 {
 200         uclong  loc_addr_range; /* 00h - Local Address Range */
 201         uclong  loc_addr_base;  /* 04h - Local Address Base */
 202         uclong  loc_arbitr;     /* 08h - Local Arbitration */
 203         uclong  endian_descr;   /* 0Ch - Big/Little Endian Descriptor */
 204         uclong  loc_rom_range;  /* 10h - Local ROM Range */
 205         uclong  loc_rom_base;   /* 14h - Local ROM Base */
 206         uclong  loc_bus_descr;  /* 18h - Local Bus descriptor */
 207         uclong  loc_range_mst;  /* 1Ch - Local Range for Master to PCI */
 208         uclong  loc_base_mst;   /* 20h - Local Base for Master PCI */
 209         uclong  loc_range_io;   /* 24h - Local Range for Master IO */
 210         uclong  pci_base_mst;   /* 28h - PCI Base for Master PCI */
 211         uclong  pci_conf_io;    /* 2Ch - PCI configuration for Master IO */
 212         uclong  filler1;        /* 30h */
 213         uclong  filler2;        /* 34h */
 214         uclong  filler3;        /* 38h */
 215         uclong  filler4;        /* 3Ch */
 216         uclong  mail_box_0;     /* 40h - Mail Box 0 */
 217         uclong  mail_box_1;     /* 44h - Mail Box 1 */
 218         uclong  mail_box_2;     /* 48h - Mail Box 2 */
 219         uclong  mail_box_3;     /* 4Ch - Mail Box 3 */
 220         uclong  filler5;        /* 50h */
 221         uclong  filler6;        /* 54h */
 222         uclong  filler7;        /* 58h */
 223         uclong  filler8;        /* 5Ch */
 224         uclong  pci_doorbell;   /* 60h - PCI to Local Doorbell */
 225         uclong  loc_doorbell;   /* 64h - Local to PCI Doorbell */
 226         uclong  intr_ctrl_stat; /* 68h - Interrupt Control/Status */
 227         uclong  init_ctrl;      /* 6Ch - EEPROM control, Init Control, etc */
 228 };
 229
 230 /* Values for the Local Base Address re-map register */
 231
 232 #define WIN_RAM         0x00000001L     /* set the sliding window to RAM */
 233 #define WIN_CREG        0x14000001L     /* set the window to custom Registers */
 234
 235 /* Values timer select registers */
 236
 237 #define TIMER_BY_1M     0x00            /* clock divided by 1M */
 238 #define TIMER_BY_256K   0x01            /* clock divided by 256k */
 239 #define TIMER_BY_128K   0x02            /* clock divided by 128k */
 240 #define TIMER_BY_32K    0x03            /* clock divided by 32k */
 241
 242 /****************** ****************** *******************/
 243 #endif
 244
 245 #ifndef ZFIRM_ID
 246 /* #include "zfwint.h" */
 247 /****************** ****************** *******************/
 248 /*
 249  *      This file contains the definitions for interfacing with the
 250  *      Cyclom-Z ZFIRM Firmware.
 251  */
 252
 253 /* General Constant definitions */
 254
 255 #define MAX_CHAN        64              /* max number of channels per board */
 256
 257 /* firmware id structure (set after boot) */
 258
 259 #define ID_ADDRESS      0x00000180L     /* signature/pointer address */
 260 #define ZFIRM_ID        0x5557465AL     /* ZFIRM/U signature */
 261 #define ZFIRM_HLT       0x59505B5CL     /* ZFIRM needs external power supply */
 262 #define ZFIRM_RST       0x56040674L     /* RST signal (due to FW reset) */
 263
 264 #define ZF_TINACT_DEF   1000            /* default inactivity timeout
 265                                            (1000 ms) */
 266 #define ZF_TINACT       ZF_TINACT_DEF
 267
 268 struct  FIRM_ID {
 269         uclong  signature;              /* ZFIRM/U signature */
 270         uclong  zfwctrl_addr;           /* pointer to ZFW_CTRL structure */
 271 };
 272
 273 /* Op. System id */
 274
 275 #define C_OS_LINUX      0x00000030      /* generic Linux system */
 276
 277 /* channel op_mode */
 278
 279 #define C_CH_DISABLE    0x00000000      /* channel is disabled */
 280 #define C_CH_TXENABLE   0x00000001      /* channel Tx enabled */
 281 #define C_CH_RXENABLE   0x00000002      /* channel Rx enabled */
 282 #define C_CH_ENABLE     0x00000003      /* channel Tx/Rx enabled */
 283 #define C_CH_LOOPBACK   0x00000004      /* Loopback mode */
 284
 285 /* comm_parity - parity */
 286
 287 #define C_PR_NONE       0x00000000      /* None */
 288 #define C_PR_ODD        0x00000001      /* Odd */
 289 #define C_PR_EVEN       0x00000002      /* Even */
 290 #define C_PR_MARK       0x00000004      /* Mark */
 291 #define C_PR_SPACE      0x00000008      /* Space */
 292 #define C_PR_PARITY     0x000000ff
 293
 294 #define C_PR_DISCARD    0x00000100      /* discard char with frame/par error */
 295 #define C_PR_IGNORE     0x00000200      /* ignore frame/par error */
 296
 297 /* comm_data_l - data length and stop bits */
 298
 299 #define C_DL_CS5        0x00000001
 300 #define C_DL_CS6        0x00000002
 301 #define C_DL_CS7        0x00000004
 302 #define C_DL_CS8        0x00000008
 303 #define C_DL_CS         0x0000000f
 304 #define C_DL_1STOP      0x00000010
 305 #define C_DL_15STOP     0x00000020
 306 #define C_DL_2STOP      0x00000040
 307 #define C_DL_STOP       0x000000f0
 308
 309 /* interrupt enabling/status */
 310
 311 #define C_IN_DISABLE    0x00000000      /* zero, disable interrupts */
 312 #define C_IN_TXBEMPTY   0x00000001      /* tx buffer empty */
 313 #define C_IN_TXLOWWM    0x00000002      /* tx buffer below LWM */
 314 #define C_IN_RXHIWM     0x00000010      /* rx buffer above HWM */
 315 #define C_IN_RXNNDT     0x00000020      /* rx no new data timeout */
 316 #define C_IN_MDCD       0x00000100      /* modem DCD change */
 317 #define C_IN_MDSR       0x00000200      /* modem DSR change */
 318 #define C_IN_MRI        0x00000400      /* modem RI change */
 319 #define C_IN_MCTS       0x00000800      /* modem CTS change */
 320 #define C_IN_RXBRK      0x00001000      /* Break received */
 321 #define C_IN_PR_ERROR   0x00002000      /* parity error */
 322 #define C_IN_FR_ERROR   0x00004000      /* frame error */
 323 #define C_IN_OVR_ERROR  0x00008000      /* overrun error */
 324 #define C_IN_RXOFL      0x00010000      /* RX buffer overflow */
 325 #define C_IN_IOCTLW     0x00020000      /* I/O control w/ wait */
 326 #define C_IN_MRTS       0x00040000      /* modem RTS drop */
 327 #define C_IN_ICHAR      0x00080000
 328
 329 /* flow control */
 330
 331 #define C_FL_OXX        0x00000001      /* output Xon/Xoff flow control */
 332 #define C_FL_IXX        0x00000002      /* output Xon/Xoff flow control */
 333 #define C_FL_OIXANY     0x00000004      /* output Xon/Xoff (any xon) */
 334 #define C_FL_SWFLOW     0x0000000f
 335
 336 /* flow status */
 337
 338 #define C_FS_TXIDLE     0x00000000      /* no Tx data in the buffer or UART */
 339 #define C_FS_SENDING    0x00000001      /* UART is sending data */
 340 #define C_FS_SWFLOW     0x00000002      /* Tx is stopped by received Xoff */
 341
 342 /* rs_control/rs_status RS-232 signals */
 343
 344 #define C_RS_PARAM      0x80000000      /* Indicates presence of parameter in
 345                                            IOCTLM command */
 346 #define C_RS_RTS        0x00000001      /* RTS */
 347 #define C_RS_DTR        0x00000004      /* DTR */
 348 #define C_RS_DCD        0x00000100      /* CD */
 349 #define C_RS_DSR        0x00000200      /* DSR */
 350 #define C_RS_RI         0x00000400      /* RI */
 351 #define C_RS_CTS        0x00000800      /* CTS */
 352
 353 /* commands Host <-> Board */
 354
 355 #define C_CM_RESET      0x01            /* reset/flush buffers */
 356 #define C_CM_IOCTL      0x02            /* re-read CH_CTRL */
 357 #define C_CM_IOCTLW     0x03            /* re-read CH_CTRL, intr when done */
 358 #define C_CM_IOCTLM     0x04            /* RS-232 outputs change */
 359 #define C_CM_SENDXOFF   0x10            /* send Xoff */
 360 #define C_CM_SENDXON    0x11            /* send Xon */
 361 #define C_CM_CLFLOW     0x12            /* Clear flow control (resume) */
 362 #define C_CM_SENDBRK    0x41            /* send break */
 363 #define C_CM_INTBACK    0x42            /* Interrupt back */
 364 #define C_CM_SET_BREAK  0x43            /* Tx break on */
 365 #define C_CM_CLR_BREAK  0x44            /* Tx break off */
 366 #define C_CM_CMD_DONE   0x45            /* Previous command done */
 367 #define C_CM_INTBACK2   0x46            /* Alternate Interrupt back */
 368 #define C_CM_TINACT     0x51            /* set inactivity detection */
 369 #define C_CM_IRQ_ENBL   0x52            /* enable generation of interrupts */
 370 #define C_CM_IRQ_DSBL   0x53            /* disable generation of interrupts */
 371 #define C_CM_ACK_ENBL   0x54            /* enable acknowledged interrupt mode */
 372 #define C_CM_ACK_DSBL   0x55            /* disable acknowledged intr mode */
 373 #define C_CM_FLUSH_RX   0x56            /* flushes Rx buffer */
 374 #define C_CM_FLUSH_TX   0x57            /* flushes Tx buffer */
 375 #define C_CM_Q_ENABLE   0x58            /* enables queue access from the
 376                                            driver */
 377 #define C_CM_Q_DISABLE  0x59            /* disables queue access from the
 378                                            driver */
 379
 380 #define C_CM_TXBEMPTY   0x60            /* Tx buffer is empty */
 381 #define C_CM_TXLOWWM    0x61            /* Tx buffer low water mark */
 382 #define C_CM_RXHIWM     0x62            /* Rx buffer high water mark */
 383 #define C_CM_RXNNDT     0x63            /* rx no new data timeout */
 384 #define C_CM_TXFEMPTY   0x64
 385 #define C_CM_ICHAR      0x65
 386 #define C_CM_MDCD       0x70            /* modem DCD change */
 387 #define C_CM_MDSR       0x71            /* modem DSR change */
 388 #define C_CM_MRI        0x72            /* modem RI change */
 389 #define C_CM_MCTS       0x73            /* modem CTS change */
 390 #define C_CM_MRTS       0x74            /* modem RTS drop */
 391 #define C_CM_RXBRK      0x84            /* Break received */
 392 #define C_CM_PR_ERROR   0x85            /* Parity error */
 393 #define C_CM_FR_ERROR   0x86            /* Frame error */
 394 #define C_CM_OVR_ERROR  0x87            /* Overrun error */
 395 #define C_CM_RXOFL      0x88            /* RX buffer overflow */
 396 #define C_CM_CMDERROR   0x90            /* command error */
 397 #define C_CM_FATAL      0x91            /* fatal error */
 398 #define C_CM_HW_RESET   0x92            /* reset board */
 399
 400 /*
 401  *      CH_CTRL - This per port structure contains all parameters
 402  *      that control an specific port. It can be seen as the
 403  *      configuration registers of a "super-serial-controller".
 404  */
 405
 406 struct CH_CTRL {
 407         uclong  op_mode;        /* operation mode */
 408         uclong  intr_enable;    /* interrupt masking */
 409         uclong  sw_flow;        /* SW flow control */
 410         uclong  flow_status;    /* output flow status */
 411         uclong  comm_baud;      /* baud rate  - numerically specified */
 412         uclong  comm_parity;    /* parity */
 413         uclong  comm_data_l;    /* data length/stop */
 414         uclong  comm_flags;     /* other flags */
 415         uclong  hw_flow;        /* HW flow control */
 416         uclong  rs_control;     /* RS-232 outputs */
 417         uclong  rs_status;      /* RS-232 inputs */
 418         uclong  flow_xon;       /* xon char */
 419         uclong  flow_xoff;      /* xoff char */
 420         uclong  hw_overflow;    /* hw overflow counter */
 421         uclong  sw_overflow;    /* sw overflow counter */
 422         uclong  comm_error;     /* frame/parity error counter */
 423         uclong ichar;
 424         uclong filler[7];
 425 };
 426
 427
 428 /*
 429  *      BUF_CTRL - This per channel structure contains
 430  *      all Tx and Rx buffer control for a given channel.
 431  */
 432
 433 struct  BUF_CTRL        {
 434         uclong  flag_dma;       /* buffers are in Host memory */
 435         uclong  tx_bufaddr;     /* address of the tx buffer */
 436         uclong  tx_bufsize;     /* tx buffer size */
 437         uclong  tx_threshold;   /* tx low water mark */
 438         uclong  tx_get;         /* tail index tx buf */
 439         uclong  tx_put;         /* head index tx buf */
 440         uclong  rx_bufaddr;     /* address of the rx buffer */
 441         uclong  rx_bufsize;     /* rx buffer size */
 442         uclong  rx_threshold;   /* rx high water mark */
 443         uclong  rx_get;         /* tail index rx buf */
 444         uclong  rx_put;         /* head index rx buf */
 445         uclong  filler[5];      /* filler to align structures */
 446 };
 447
 448 /*
 449  *      BOARD_CTRL - This per board structure contains all global
 450  *      control fields related to the board.
 451  */
 452
 453 struct BOARD_CTRL {
 454
 455         /* static info provided by the on-board CPU */
 456         uclong  n_channel;      /* number of channels */
 457         uclong  fw_version;     /* firmware version */
 458
 459         /* static info provided by the driver */
 460         uclong  op_system;      /* op_system id */
 461         uclong  dr_version;     /* driver version */
 462
 463         /* board control area */
 464         uclong  inactivity;     /* inactivity control */
 465
 466         /* host to FW commands */
 467         uclong  hcmd_channel;   /* channel number */
 468         uclong  hcmd_param;     /* pointer to parameters */
 469
 470         /* FW to Host commands */
 471         uclong  fwcmd_channel;  /* channel number */
 472         uclong  fwcmd_param;    /* pointer to parameters */
 473         uclong  zf_int_queue_addr; /* offset for INT_QUEUE structure */
 474
 475         /* filler so the structures are aligned */
 476         uclong  filler[6];
 477 };
 478
 479 /* Host Interrupt Queue */
 480
 481 #define QUEUE_SIZE      (10*MAX_CHAN)
 482
 483 struct  INT_QUEUE {
 484         unsigned char   intr_code[QUEUE_SIZE];
 485         unsigned long   channel[QUEUE_SIZE];
 486         unsigned long   param[QUEUE_SIZE];
 487         unsigned long   put;
 488         unsigned long   get;
 489 };
 490
 491 /*
 492  *      ZFW_CTRL - This is the data structure that includes all other
 493  *      data structures used by the Firmware.
 494  */
 495
 496 struct ZFW_CTRL {
 497         struct BOARD_CTRL       board_ctrl;
 498         struct CH_CTRL          ch_ctrl[MAX_CHAN];
 499         struct BUF_CTRL         buf_ctrl[MAX_CHAN];
 500 };
 501
 502 /****************** ****************** *******************/
 503 #endif
 504
 505 /* Per card data structure */
 506 struct cyclades_card {
 507     unsigned long base_phys;
 508     unsigned long ctl_phys;
 509     unsigned long base_addr;
 510     unsigned long ctl_addr;
 511     int irq;
 512     int num_chips;      /* 0 if card absent, -1 if Z/PCI, else Y */
 513     int first_line;     /* minor number of first channel on card */
 514     int nports;         /* Number of ports in the card */
 515     int bus_index;      /* address shift - 0 for ISA, 1 for PCI */
 516     int intr_enabled;   /* FW Interrupt flag - 0 disabled, 1 enabled */
 517 #ifdef __KERNEL__
 518     spinlock_t card_lock;
 519 #else
 520     uclong filler;
 521 #endif
 522 };
 523
 524 struct cyclades_chip {
 525   int filler;
 526 };
 527
 528
 529 #ifdef __KERNEL__
 530
 531 /***************************************
 532  * Memory access functions/macros      *
 533  * (required to support Alpha systems) *
 534  ***************************************/
 535
 536 #define cy_writeb(port,val)     {writeb((ucchar)(val),(ulong)(port)); mb();}
 537 #define cy_writew(port,val)     {writew((ushort)(val),(ulong)(port)); mb();}
 538 #define cy_writel(port,val)     {writel((uclong)(val),(ulong)(port)); mb();}
 539
 540 #define cy_readb(port)  readb(port)
 541 #define cy_readw(port)  readw(port)
 542 #define cy_readl(port)  readl(port)
 543
 544 /*
 545  * Statistics counters
 546  */
 547 struct cyclades_icount {
 548         __u32   cts, dsr, rng, dcd, tx, rx;
 549         __u32   frame, parity, overrun, brk;
 550         __u32   buf_overrun;
 551 };
 552
 553 /*
 554  * This is our internal structure for each serial port's state.
 555  *
 556  * Many fields are paralleled by the structure used by the serial_struct
 557  * structure.
 558  *
 559  * For definitions of the flags field, see tty.h
 560  */
 561
 562 struct cyclades_port {
 563         int                     magic;
 564         int                     card;
 565         int                     line;
 566         int                     flags;          /* defined in tty.h */
 567         int                     type;           /* UART type */
 568         struct tty_struct       *tty;
 569         int                     read_status_mask;
 570         int                     ignore_status_mask;
 571         int                     timeout;
 572         int                     xmit_fifo_size;
 573         int                     cor1,cor2,cor3,cor4,cor5;
 574         int                     tbpr,tco,rbpr,rco;
 575         int                     baud;
 576         int                     rflow;
 577         int                     rtsdtr_inv;
 578         int                     chip_rev;
 579         int                     custom_divisor;
 580         int                     x_char; /* to be pushed out ASAP */
 581         int                     close_delay;
 582         unsigned short          closing_wait;
 583         unsigned long           event;
 584         unsigned long           last_active;
 585         int                     count;  /* # of fd on device */
 586         int                     breakon;
 587         int                     breakoff;
 588         int                     blocked_open; /* # of blocked opens */
 589         long                    session; /* Session of opening process */
 590         long                    pgrp; /* pgrp of opening process */
 591         unsigned char           *xmit_buf;
 592         int                     xmit_head;
 593         int                     xmit_tail;
 594         int                     xmit_cnt;
 595         int                     default_threshold;
 596         int                     default_timeout;
 597         unsigned long           jiffies[3];
 598         unsigned long           rflush_count;
 599         struct termios          normal_termios;
 600         struct termios          callout_termios;
 601         struct cyclades_monitor mon;
 602         struct cyclades_idle_stats      idle_stats;
 603         struct cyclades_icount  icount;
 604         struct tq_struct        tqueue;
 605         wait_queue_head_t       open_wait;
 606         wait_queue_head_t       close_wait;
 607         wait_queue_head_t       shutdown_wait;
 608         wait_queue_head_t       delta_msr_wait;
 609 };
 610
 611 /*
 612  * Events are used to schedule things to happen at timer-interrupt
 613  * time, instead of at cy interrupt time.
 614  */
 615 #define Cy_EVENT_READ_PROCESS           0
 616 #define Cy_EVENT_WRITE_WAKEUP           1
 617 #define Cy_EVENT_HANGUP                 2
 618 #define Cy_EVENT_BREAK                  3
 619 #define Cy_EVENT_OPEN_WAKEUP            4
 620 #define Cy_EVENT_SHUTDOWN_WAKEUP        5
 621 #define Cy_EVENT_DELTA_WAKEUP           6
 622 #define Cy_EVENT_Z_RX_FULL              7
 623
 624 #define CLOSING_WAIT_DELAY      30*HZ
 625 #define CY_CLOSING_WAIT_NONE    65535
 626 #define CY_CLOSING_WAIT_INF     0
 627
 628
 629 #define CyMAX_CHIPS_PER_CARD    8
 630 #define CyMAX_CHAR_FIFO         12
 631 #define CyPORTS_PER_CHIP        4
 632 #define CD1400_MAX_SPEED        115200
 633
 634 #define CyISA_Ywin      0x2000
 635
 636 #define CyPCI_Ywin      0x4000
 637 #define CyPCI_Yctl      0x80
 638 #define CyPCI_Zctl      CTRL_WINDOW_SIZE
 639 #define CyPCI_Zwin      0x80000
 640 #define CyPCI_Ze_win    (2 * CyPCI_Zwin)
 641
 642 #define PCI_DEVICE_ID_MASK      0x06
 643
 644 /**** CD1400 registers ****/
 645
 646 #define CD1400_REV_G    0x46
 647 #define CD1400_REV_J    0x48
 648
 649 #define CyRegSize       0x0400
 650 #define Cy_HwReset      0x1400
 651 #define Cy_ClrIntr      0x1800
 652 #define Cy_EpldRev      0x1e00
 653
 654 /* Global Registers */
 655
 656 #define CyGFRCR         (0x40*2)
 657 #define      CyRevE             (44)
 658 #define CyCAR           (0x68*2)
 659 #define      CyCHAN_0           (0x00)
 660 #define      CyCHAN_1           (0x01)
 661 #define      CyCHAN_2           (0x02)
 662 #define      CyCHAN_3           (0x03)
 663 #define CyGCR           (0x4B*2)
 664 #define      CyCH0_SERIAL       (0x00)
 665 #define      CyCH0_PARALLEL     (0x80)
 666 #define CySVRR          (0x67*2)
 667 #define      CySRModem          (0x04)
 668 #define      CySRTransmit       (0x02)
 669 #define      CySRReceive        (0x01)
 670 #define CyRICR          (0x44*2)
 671 #define CyTICR          (0x45*2)
 672 #define CyMICR          (0x46*2)
 673 #define      CyICR0             (0x00)
 674 #define      CyICR1             (0x01)
 675 #define      CyICR2             (0x02)
 676 #define      CyICR3             (0x03)
 677 #define CyRIR           (0x6B*2)
 678 #define CyTIR           (0x6A*2)
 679 #define CyMIR           (0x69*2)
 680 #define      CyIRDirEq          (0x80)
 681 #define      CyIRBusy           (0x40)
 682 #define      CyIRUnfair         (0x20)
 683 #define      CyIRContext        (0x1C)
 684 #define      CyIRChannel        (0x03)
 685 #define CyPPR           (0x7E*2)
 686 #define      CyCLOCK_20_1MS     (0x27)
 687 #define      CyCLOCK_25_1MS     (0x31)
 688 #define      CyCLOCK_25_5MS     (0xf4)
 689 #define      CyCLOCK_60_1MS     (0x75)
 690 #define      CyCLOCK_60_2MS     (0xea)
 691
 692 /* Virtual Registers */
 693
 694 #define CyRIVR          (0x43*2)
 695 #define CyTIVR          (0x42*2)
 696 #define CyMIVR          (0x41*2)
 697 #define      CyIVRMask (0x07)
 698 #define      CyIVRRxEx (0x07)
 699 #define      CyIVRRxOK (0x03)
 700 #define      CyIVRTxOK (0x02)
 701 #define      CyIVRMdmOK (0x01)
 702 #define CyTDR           (0x63*2)
 703 #define CyRDSR          (0x62*2)
 704 #define      CyTIMEOUT          (0x80)
 705 #define      CySPECHAR          (0x70)
 706 #define      CyBREAK            (0x08)
 707 #define      CyPARITY           (0x04)
 708 #define      CyFRAME            (0x02)
 709 #define      CyOVERRUN          (0x01)
 710 #define CyMISR          (0x4C*2)
 711 /* see CyMCOR_ and CyMSVR_ for bits*/
 712 #define CyEOSRR         (0x60*2)
 713
 714 /* Channel Registers */
 715
 716 #define CyLIVR          (0x18*2)
 717 #define      CyMscsr            (0x01)
 718 #define      CyTdsr             (0x02)
 719 #define      CyRgdsr            (0x03)
 720 #define      CyRedsr            (0x07)
 721 #define CyCCR           (0x05*2)
 722 /* Format 1 */
 723 #define      CyCHAN_RESET       (0x80)
 724 #define      CyCHIP_RESET       (0x81)
 725 #define      CyFlushTransFIFO   (0x82)
 726 /* Format 2 */
 727 #define      CyCOR_CHANGE       (0x40)
 728 #define      CyCOR1ch           (0x02)
 729 #define      CyCOR2ch           (0x04)
 730 #define      CyCOR3ch           (0x08)
 731 /* Format 3 */
 732 #define      CySEND_SPEC_1      (0x21)
 733 #define      CySEND_SPEC_2      (0x22)
 734 #define      CySEND_SPEC_3      (0x23)
 735 #define      CySEND_SPEC_4      (0x24)
 736 /* Format 4 */
 737 #define      CyCHAN_CTL         (0x10)
 738 #define      CyDIS_RCVR         (0x01)
 739 #define      CyENB_RCVR         (0x02)
 740 #define      CyDIS_XMTR         (0x04)
 741 #define      CyENB_XMTR         (0x08)
 742 #define CySRER          (0x06*2)
 743 #define      CyMdmCh            (0x80)
 744 #define      CyRxData           (0x10)
 745 #define      CyTxRdy            (0x04)
 746 #define      CyTxMpty           (0x02)
 747 #define      CyNNDT             (0x01)
 748 #define CyCOR1          (0x08*2)
 749 #define      CyPARITY_NONE      (0x00)
 750 #define      CyPARITY_0         (0x20)
 751 #define      CyPARITY_1         (0xA0)
 752 #define      CyPARITY_E         (0x40)
 753 #define      CyPARITY_O         (0xC0)
 754 #define      Cy_1_STOP          (0x00)
 755 #define      Cy_1_5_STOP        (0x04)
 756 #define      Cy_2_STOP          (0x08)
 757 #define      Cy_5_BITS          (0x00)
 758 #define      Cy_6_BITS          (0x01)
 759 #define      Cy_7_BITS          (0x02)
 760 #define      Cy_8_BITS          (0x03)
 761 #define CyCOR2          (0x09*2)
 762 #define      CyIXM              (0x80)
 763 #define      CyTxIBE            (0x40)
 764 #define      CyETC              (0x20)
 765 #define      CyAUTO_TXFL        (0x60)
 766 #define      CyLLM              (0x10)
 767 #define      CyRLM              (0x08)
 768 #define      CyRtsAO            (0x04)
 769 #define      CyCtsAE            (0x02)
 770 #define      CyDsrAE            (0x01)
 771 #define CyCOR3          (0x0A*2)
 772 #define      CySPL_CH_DRANGE    (0x80)  /* special character detect range */
 773 #define      CySPL_CH_DET1      (0x40)  /* enable special character detection
 774                                                                on SCHR4-SCHR3 */
 775 #define      CyFL_CTRL_TRNSP    (0x20)  /* Flow Control Transparency */
 776 #define      CySPL_CH_DET2      (0x10)  /* Enable special character detection
 777                                                                on SCHR2-SCHR1 */
 778 #define      CyREC_FIFO         (0x0F)  /* Receive FIFO threshold */
 779 #define CyCOR4          (0x1E*2)
 780 #define CyCOR5          (0x1F*2)
 781 #define CyCCSR          (0x0B*2)
 782 #define      CyRxEN             (0x80)
 783 #define      CyRxFloff          (0x40)
 784 #define      CyRxFlon           (0x20)
 785 #define      CyTxEN             (0x08)
 786 #define      CyTxFloff          (0x04)
 787 #define      CyTxFlon           (0x02)
 788 #define CyRDCR          (0x0E*2)
 789 #define CySCHR1         (0x1A*2)
 790 #define CySCHR2         (0x1B*2)
 791 #define CySCHR3         (0x1C*2)
 792 #define CySCHR4         (0x1D*2)
 793 #define CySCRL          (0x22*2)
 794 #define CySCRH          (0x23*2)
 795 #define CyLNC           (0x24*2)
 796 #define CyMCOR1         (0x15*2)
 797 #define CyMCOR2         (0x16*2)
 798 #define CyRTPR          (0x21*2)
 799 #define CyMSVR1         (0x6C*2)
 800 #define CyMSVR2         (0x6D*2)
 801 #define      CyANY_DELTA        (0xF0)
 802 #define      CyDSR              (0x80)
 803 #define      CyCTS              (0x40)
 804 #define      CyRI               (0x20)
 805 #define      CyDCD              (0x10)
 806 #define      CyDTR              (0x02)
 807 #define      CyRTS              (0x01)
 808 #define CyPVSR          (0x6F*2)
 809 #define CyRBPR          (0x78*2)
 810 #define CyRCOR          (0x7C*2)
 811 #define CyTBPR          (0x72*2)
 812 #define CyTCOR          (0x76*2)
 813
 814 /* Custom Registers */
 815
 816 #define CyPLX_VER       (0x3400)
 817 #define PLX_9050        0x0b
 818 #define PLX_9060        0x0c
 819 #define PLX_9080        0x0d
 820
 821 /***************************************************************************/
 822
 823 #endif /* __KERNEL__ */
 824 #endif /* _LINUX_CYCLADES_H */