arch/ppc/mm/4xx_tlb.c

   1 /*
   2  *
   3  *    Copyright (c) 1998-1999 TiVo, Inc.
   4  *      Original implementation.
   5  *    Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
   6  *      Minor rework.
   7  *
   8  *    Module name: 4xx_tlb.c
   9  *
  10  *    Description:
  11  *      Routines for manipulating the TLB on PowerPC 400-class processors.
  12  *
  13  */
  14
  15 #include <linux/mm.h>
  16
  17 #include <asm/processor.h>
  18 #include <asm/io.h>
  19 #include <asm/mmu.h>
  20 #include <asm/pgtable.h>
  21 #include <asm/system.h>
  22
  23
  24 /* Preprocessor Defines */
  25
  26 #if !defined(TRUE) || TRUE != 1
  27 #define TRUE    1
  28 #endif
  29
  30 #if !defined(FALSE) || FALSE != 0
  31 #define FALSE   0
  32 #endif
  33
  34
  35 /* Global Variables */
  36
  37 static int pinned = 0;
  38
  39
  40 /* Function Prototypes */
  41
  42 static int PPC4xx_tlb_miss(struct pt_regs *, unsigned long, int);
  43
  44 extern void do_page_fault(struct pt_regs *, unsigned long, unsigned long);
  45
  46
  47 /*
  48  * ()
  49  *
  50  * Description:
  51  *   This routine...
  52  *
  53  * Input(s):
  54  *
  55  *
  56  * Output(s):
  57  *
  58  *
  59  * Returns:
  60  *
  61  *
  62  */
  63 static inline void
  64 PPC4xx_tlb_write(unsigned long tag, unsigned long data, unsigned int index)
  65 {
  66         asm("tlbwe %0,%1,1" : : "r" (data), "r" (index));
  67         asm("tlbwe %0,%1,0" : : "r" (tag), "r" (index));
  68 }
  69
  70 /*
  71  * ()
  72  *
  73  * Description:
  74  *   This routine...
  75  *
  76  * Input(s):
  77  *
  78  *
  79  * Output(s):
  80  *
  81  *
  82  * Returns:
  83  *
  84  *
  85  */
  86 void
  87 PPC4xx_flush_tlb_all(void)
  88 {
  89         int i;
  90         unsigned long flags, pid;
  91
  92         save_flags(flags);
  93         cli();
  94
  95         pid = mfspr(SPRN_PID);
  96         mtspr(SPRN_PID, 0);
  97
  98         for (i = pinned; i < PPC4XX_TLB_SIZE; i++) {
  99                 PPC4xx_tlb_write(0, 0, i);
 100         }
 101         asm("sync;isync");
 102
 103         mtspr(SPRN_PID, pid);
 104         restore_flags(flags);
 105 }
 106
 107 /*
 108  * ()
 109  *
 110  * Description:
 111  *   This routine...
 112  *
 113  * Input(s):
 114  *
 115  *
 116  * Output(s):
 117  *
 118  *
 119  * Returns:
 120  *
 121  *
 122  */
 123 void
 124 PPC4xx_dtlb_miss(struct pt_regs *regs)
 125 {
 126         unsigned long addr = mfspr(SPRN_DEAR);
 127         int write = mfspr(SPRN_ESR) & ESR_DST;
 128
 129         if (PPC4xx_tlb_miss(regs, addr, write) < 0) {
 130                 sti();
 131                 do_page_fault(regs, addr, write);
 132                 cli();
 133         }
 134
 135 }
 136
 137 /*
 138  * ()
 139  *
 140  * Description:
 141  *   This routine...
 142  *
 143  * Input(s):
 144  *
 145  *
 146  * Output(s):
 147  *
 148  *
 149  * Returns:
 150  *
 151  *
 152  */
 153 void
 154 PPC4xx_itlb_miss(struct pt_regs *regs)
 155 {
 156         unsigned long addr = regs->nip;
 157
 158         if (PPC4xx_tlb_miss(regs, addr, 0) < 0) {
 159                 sti();
 160                 do_page_fault(regs, addr, 0);
 161                 cli();
 162         }
 163 }
 164
 165 /*
 166  * ()
 167  *
 168  * Description:
 169  *   This routine...
 170  *
 171  * Input(s):
 172  *
 173  *
 174  * Output(s):
 175  *
 176  *
 177  * Returns:
 178  *
 179  *
 180  */
 181 void
 182 PPC4xx_tlb_pin(unsigned long va, unsigned long pa, int pagesz, int cache)
 183 {
 184         unsigned long tag, data;
 185         unsigned long opid;
 186
 187         if (pinned >= PPC4XX_TLB_SIZE)
 188                 return;
 189
 190         opid = mfspr(SPRN_PID);
 191         mtspr(SPRN_PID, 0);
 192
 193         data = (pa & TLB_RPN_MASK) | TLB_WR;
 194
 195         if (cache)
 196                 data |= (TLB_EX);
 197         else
 198                 data |= (TLB_G | TLB_I);
 199
 200         tag = (va & TLB_EPN_MASK) | TLB_VALID | pagesz;
 201
 202         PPC4xx_tlb_write(tag, data, pinned++);
 203
 204         mtspr(SPRN_PID, opid);
 205         return;
 206 }
 207
 208 /*
 209  * ()
 210  *
 211  * Description:
 212  *   This routine...
 213  *
 214  * Input(s):
 215  *
 216  *
 217  * Output(s):
 218  *
 219  *
 220  * Returns:
 221  *
 222  *
 223  */
 224 void
 225 PPC4xx_tlb_unpin(unsigned long va, unsigned long pa, int size)
 226 {
 227         /* XXX - To be implemented. */
 228 }
 229
 230 /*
 231  * ()
 232  *
 233  * Description:
 234  *   This routine...
 235  *
 236  * Input(s):
 237  *
 238  *
 239  * Output(s):
 240  *
 241  *
 242  * Returns:
 243  *
 244  *
 245  */
 246 static inline void
 247 PPC4xx_tlb_update(unsigned long addr, pte_t *pte)
 248 {
 249         unsigned long data, tag, rand;
 250         int i, found = 1;
 251
 252         /* Construct the hardware TLB entry from the Linux-style PTE */
 253
 254         tag = tag = (addr & PAGE_MASK) | TLB_VALID | TLB_PAGESZ(PAGESZ_4K);
 255         data = data = (pte_val(*pte) & PAGE_MASK) | TLB_EX | TLB_WR;
 256
 257 #if 0
 258         if (pte_val(*pte) & _PAGE_HWWRITE)
 259                 data |= TLB_WR;
 260 #endif
 261
 262         if (pte_val(*pte) & _PAGE_NO_CACHE)
 263                 data |= TLB_I;
 264
 265         if (pte_val(*pte) & _PAGE_GUARDED)
 266                 data |= TLB_G;
 267
 268         if (addr < KERNELBASE)
 269                 data |= TLB_ZSEL(1);
 270
 271         /* Attempt to match the new tag to an existing entry in the TLB. */
 272
 273         asm("tlbsx. %0,0,%2;"
 274             "beq 1f;"
 275             "li %1,0;1:" : "=r" (i), "=r" (found) : "r" (tag));
 276
 277         /*
 278          * If we found a match for the tag, reuse the entry index and update
 279          * the tag and data portions. Otherwise, we did not find a match. Use
 280          * the lower 5 bits of the lower time base register as a pseudo-random
 281          * index into the TLB and replace the entry at that index.
 282          */
 283
 284         if (found) {
 285                 PPC4xx_tlb_write(tag, data, i);
 286         } else {
 287                 rand = mfspr(SPRN_TBLO) & (PPC4XX_TLB_SIZE - 1);
 288                 rand += pinned;
 289                 if (rand >= PPC4XX_TLB_SIZE)
 290                         rand -= pinned;
 291
 292                 PPC4xx_tlb_write(tag, data, rand);
 293                 asm("isync;sync");
 294         }
 295 }
 296
 297 /*
 298  * ()
 299  *
 300  * Description:
 301  *   This routine...
 302  *
 303  * Input(s):
 304  *
 305  *
 306  * Output(s):
 307  *
 308  *
 309  * Returns:
 310  *
 311  *
 312  */
 313 static int
 314 PPC4xx_tlb_miss(struct pt_regs *regs, unsigned long addr, int write)
 315 {
 316         unsigned long spid, ospid;
 317         struct mm_struct *mm;
 318         pgd_t *pgd;
 319         pmd_t *pmd;
 320         pte_t *pte;
 321
 322         if (!user_mode(regs) && (addr >= KERNELBASE)) {
 323                 mm = &init_mm;
 324                 spid = 0;
 325         } else {
 326                 mm = current->mm;
 327                 spid = mfspr(SPRN_PID);
 328         }
 329
 330         pgd = pgd_offset(mm, addr);
 331         if (pgd_none(*pgd))
 332                 goto bad;
 333
 334         pmd = pmd_offset(pgd, addr);
 335         if (pmd_none(*pmd))
 336                 goto bad;
 337
 338         pte = pte_offset(pmd, addr);
 339         if (pte_none(*pte) || !pte_present(*pte))
 340                 goto bad;
 341
 342         if (write) {
 343                 if (!pte_write(*pte))
 344                         goto bad;
 345
 346                 set_pte(pte, pte_mkdirty(*pte));
 347         }
 348         set_pte(pte, pte_mkyoung(*pte));
 349
 350         ospid = mfspr(SPRN_PID);
 351         mtspr(SPRN_PID, spid);
 352         PPC4xx_tlb_update(addr, pte);
 353         mtspr(SPRN_PID, ospid);
 354
 355         return (0);
 356 bad:
 357         return (-1);
 358 }