2 pi2.c: Driver for the Ottawa Amateur Radio Club PI and PI2 interface.
3 Copyright (c) 1994 David Perry
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License version 2, as
7 published by the Free Software Foundation.
9 This program is distributed in the hope that it will be useful, but
10 WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software Foundation,
16 Inc., 675 Mass Ave, Cambridge MA 02139, USA.
18 The file skeleton.c by Donald Becker was used as a starting point
23 April 6, 1994 (dp) Created
25 April 10, 1994 (dp) Included cleanup, suggestions from J. P. Morrison.
27 April 13, 1994 (dp) Included address probing from JPM, autoirq
29 April 14, 1994 (ac) Sketched in the NET3 changes.
30 April 17, 1994 (dp) Finished the NET3 changes. Used init_etherdev()
31 instead of kmalloc() to ensure that DMA buffers will
32 reside under the 16 meg line.
34 April 18, 1994 (dp) Now using the kernel provided sk_buff handling functions.
35 Fixed a nasty problem with DMA.
37 June 6, 1994 (ac) Fixed to match the buffer locking changes. Added a hack to
38 fix a funny I see (search for HACK) and fixed the calls in
39 init() so it doesn't migrate module based ethernet cards up
40 to eth2 Took out the old module ideas as they are no longer
41 relevant to the PI driver.
42 July 16, 1994 (dp) Fixed the B channel rx overrun problem ac referred to
43 above. Also added a bit of a hack to improve the maximum
44 baud rate on the B channel (Search for STUFF2). Included
45 ioctl stuff from John Paul Morrison. version 0.6 ALPHA
46 Feb 9, 1995 (dp) Updated for 1.1.90 kernel
48 Apr 6, 1995 (ac) Tweaks for NET3 pre snapshot 002 AX.25
49 April 23, 1995 (dp) Fixed ioctl so it works properly with piconfig program
50 when changing the baud rate or clock mode.
52 July 17, 1995 (ac) Finally polishing of AX25.030+ support
53 Oct 29, 1995 (ac) A couple of minor fixes before this, and this release changes
54 to the proper set_mac_address semantics which will break
55 a few programs I suspect.
56 Aug 18, 1996 (jsn) Converted to be used as a module.
57 Dec 13, 1996 (jsn) Fixed to match Linux networking changes.
60 /* The following #define invokes a hack that will improve performance (baud)
61 for the B port. The up side is it makes 9600 baud work ok on the B port.
62 It may do 38400, depending on the host. The down side is it burns up
63 CPU cycles with ints locked for up to 1 character time, at the beginning
64 of each transmitted packet. If this causes you to lose sleep, #undefine it.
69 /* The default configuration */
72 #define DEF_A_SPEED 0 /* 0 means external clock */
73 #define DEF_A_TXDELAY 15 /* 15 mS transmit delay */
74 #define DEF_A_PERSIST 128 /* 50% persistence */
75 #define DEF_A_SLOTIME 15 /* 15 mS slot time */
76 #define DEF_A_SQUELDELAY 1 /* 1 mS squelch delay - allows fcs and flag */
77 #define DEF_A_CLOCKMODE 0 /* clock mode - 0 is normal */
79 #define DEF_B_SPEED 1200 /* 1200 baud */
80 #define DEF_B_TXDELAY 40 /* 400 mS */
81 #define DEF_B_PERSIST 128 /* 50% */
82 #define DEF_B_SLOTIME 30 /* 300 mS */
83 #define DEF_B_SQUELDELAY 3 /* 30 mS */
84 #define DEF_B_CLOCKMODE 0 /* Normal clock mode */
86 /* The following #define is only really required for the PI card, not
87 the PI2 - but it's safer to leave it in. */
88 #define REALLY_SLOW_IO 1
90 #include <linux/config.h>
91 #include <linux/module.h>
92 #include <linux/kernel.h>
93 #include <linux/sched.h>
94 #include <linux/types.h>
95 #include <linux/fcntl.h>
96 #include <linux/interrupt.h>
97 #include <linux/ptrace.h>
98 #include <linux/ioport.h>
100 #include <linux/malloc.h>
101 #include <linux/string.h>
102 #include <linux/errno.h>
103 #include <asm/system.h>
104 #include <asm/bitops.h>
107 #include <asm/uaccess.h>
108 #include <linux/inet.h>
109 #include <linux/netdevice.h>
110 #include <linux/etherdevice.h>
111 #include <linux/skbuff.h>
112 #include <linux/timer.h>
113 #include <linux/if_arp.h>
114 #include <linux/pi2.h>
115 #include <linux/init.h>
117 #include <net/ax25.h>
126 * The actual devices we will use
130 * PI device declarations.
133 static int pi0_preprobe(struct device
*dev
){return 0;} /* Dummy probe function */
134 static struct device pi0a
= { "pi0a", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL
, pi0_preprobe
};
135 static struct device pi0b
= { "pi0b", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL
, pi0_preprobe
};
138 /* The number of low I/O ports used by the card. */
139 #define PI_TOTAL_SIZE 8
142 /* Index to functions, as function prototypes. */
144 static int pi_probe(struct device
*dev
, int card_type
);
145 static int pi_open(struct device
*dev
);
146 static int pi_send_packet(struct sk_buff
*skb
, struct device
*dev
);
147 static void pi_interrupt(int reg_ptr
, void *dev_id
, struct pt_regs
*regs
);
148 static int pi_close(struct device
*dev
);
149 static int pi_ioctl(struct device
*dev
, struct ifreq
*ifr
, int cmd
);
150 static struct net_device_stats
*pi_get_stats(struct device
*dev
);
151 static void rts(struct pi_local
*lp
, int x
);
152 static void b_rxint(struct device
*dev
, struct pi_local
*lp
);
153 static void b_txint(struct pi_local
*lp
);
154 static void b_exint(struct pi_local
*lp
);
155 static void a_rxint(struct device
*dev
, struct pi_local
*lp
);
156 static void a_txint(struct pi_local
*lp
);
157 static void a_exint(struct pi_local
*lp
);
158 static char *get_dma_buffer(unsigned long *mem_ptr
);
159 static int valid_dma_page(unsigned long addr
, unsigned long dev_buffsize
);
161 static char ax25_bcast
[7] =
162 {'Q' << 1, 'S' << 1, 'T' << 1, ' ' << 1, ' ' << 1, ' ' << 1, '0' << 1};
163 static char ax25_test
[7] =
164 {'L' << 1, 'I' << 1, 'N' << 1, 'U' << 1, 'X' << 1, ' ' << 1, '1' << 1};
166 static int ext2_secrm_seed
= 152; /* Random generator base */
168 extern inline unsigned char random(void)
170 return (unsigned char) (ext2_secrm_seed
= ext2_secrm_seed
174 extern inline void wrtscc(int cbase
, int ctl
, int sccreg
, int val
)
176 /* assume caller disables interrupts! */
177 outb_p(0, cbase
+ DMAEN
); /* Disable DMA while we touch the scc */
178 outb_p(sccreg
, ctl
); /* Select register */
179 outb_p(val
, ctl
); /* Output value */
180 outb_p(1, cbase
+ DMAEN
); /* Enable DMA */
183 extern inline int rdscc(int cbase
, int ctl
, int sccreg
)
187 /* assume caller disables interrupts! */
188 outb_p(0, cbase
+ DMAEN
); /* Disable DMA while we touch the scc */
189 outb_p(sccreg
, ctl
); /* Select register */
191 outb_p(1, cbase
+ DMAEN
); /* Enable DMA */
195 static void switchbuffers(struct pi_local
*lp
)
197 if (lp
->rcvbuf
== lp
->rxdmabuf1
)
198 lp
->rcvbuf
= lp
->rxdmabuf2
;
200 lp
->rcvbuf
= lp
->rxdmabuf1
;
203 static void hardware_send_packet(struct pi_local
*lp
, struct sk_buff
*skb
)
208 lp
->stats
.tx_packets
++;
212 kickflag
= (skb_peek(&lp
->sndq
) == NULL
) && (lp
->sndbuf
== NULL
);
213 restore_flags(flags
);
215 skb_queue_tail(&lp
->sndq
, skb
);
218 /* simulate interrupt to xmit */
219 switch (lp
->base
& 2)
222 a_txint(lp
); /* process interrupt */
227 if (lp
->tstate
== IDLE
)
229 restore_flags(flags
);
235 static void setup_rx_dma(struct pi_local
*lp
)
239 unsigned long dma_abs
;
245 dma_abs
= (unsigned long) (lp
->rcvbuf
->data
);
246 dmachan
= lp
->dmachan
;
247 cmd
= lp
->base
+ CTL
;
249 if(!valid_dma_page(dma_abs
, DMA_BUFF_SIZE
+ sizeof(struct mbuf
)))
250 panic("PI: RX buffer violates DMA boundary!");
252 /* Get ready for RX DMA */
253 wrtscc(lp
->cardbase
, cmd
, R1
, WT_FN_RDYFN
| WT_RDY_RT
| INT_ERR_Rx
| EXT_INT_ENAB
);
255 disable_dma(dmachan
);
256 clear_dma_ff(dmachan
);
258 /* Set DMA mode register to single transfers, incrementing address,
261 set_dma_mode(dmachan
, DMA_MODE_READ
| 0x10);
262 set_dma_addr(dmachan
, dma_abs
);
263 set_dma_count(dmachan
, lp
->bufsiz
);
266 /* If a packet is already coming in, this line is supposed to
267 avoid receiving a partial packet.
269 wrtscc(lp
->cardbase
, cmd
, R0
, RES_Rx_CRC
);
272 wrtscc(lp
->cardbase
, cmd
, R1
,
273 WT_RDY_ENAB
| WT_FN_RDYFN
| WT_RDY_RT
| INT_ERR_Rx
| EXT_INT_ENAB
);
275 restore_flags(flags
);
278 static void setup_tx_dma(struct pi_local
*lp
, int length
)
280 unsigned long dma_abs
;
282 unsigned long dmachan
;
287 dmachan
= lp
->dmachan
;
288 dma_abs
= (unsigned long) (lp
->txdmabuf
);
290 if(!valid_dma_page(dma_abs
, DMA_BUFF_SIZE
+ sizeof(struct mbuf
)))
291 panic("PI: TX buffer violates DMA boundary!");
293 disable_dma(dmachan
);
294 /* Set DMA mode register to single transfers, incrementing address,
295 * no auto init, reads
297 set_dma_mode(dmachan
, DMA_MODE_WRITE
);
298 clear_dma_ff(dmachan
);
299 set_dma_addr(dmachan
, dma_abs
);
300 /* output byte count */
301 set_dma_count(dmachan
, length
);
303 restore_flags(flags
);
306 static void tdelay(struct pi_local
*lp
, int time
)
312 if (lp
->base
& 2) { /* If A channel */
315 port
= lp
->cardbase
+ TMR1
;
318 t1
= 10 * time
; /* 10s of milliseconds for the B channel */
319 port
= lp
->cardbase
+ TMR2
;
320 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R1
, INT_ALL_Rx
| EXT_INT_ENAB
);
324 outb_p(sc
| LSB_MSB
| MODE0
, lp
->cardbase
+ TMRCMD
);
326 /* times 2 to make millisecs */
327 outb_p((t1
<< 1) & 0xFF, port
);
328 outb_p((t1
>> 7) & 0xFF, port
);
330 /* Enable correct int for timeout */
331 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R15
, CTSIE
);
332 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R0
, RES_EXT_INT
);
335 static void free_p(struct sk_buff
*skb
)
337 dev_kfree_skb(skb
, FREE_WRITE
);
340 static void a_txint(struct pi_local
*lp
)
348 cmd
= CTL
+ lp
->base
;
350 switch (lp
->tstate
) {
352 /* Transmitter idle. Find a frame for transmission */
353 if ((lp
->sndbuf
= skb_dequeue(&lp
->sndq
)) == NULL
) {
355 restore_flags(flags
);
358 /* If a buffer to send, we drop thru here */
360 /* we may have deferred prev xmit attempt */
361 /* Check DCD - debounce it
362 * See Intel Microcommunications Handbook, p2-308
364 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
365 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
366 if ((rdscc(lp
->cardbase
, cmd
, R0
) & DCD
) != 0) {
369 /* defer until DCD transition or timeout */
370 wrtscc(lp
->cardbase
, cmd
, R15
, CTSIE
| DCDIE
);
371 restore_flags(flags
);
374 if (random() > lp
->persist
) {
376 tdelay(lp
, lp
->slotime
);
377 restore_flags(flags
);
380 /* Assert RTS early minimize collision window */
381 wrtscc(lp
->cardbase
, cmd
, R5
, TxCRC_ENAB
| RTS
| Tx8
);
382 rts(lp
, ON
); /* Transmitter on */
383 lp
->tstate
= ST_TXDELAY
;
384 tdelay(lp
, lp
->txdelay
);
385 restore_flags(flags
);
389 } /* end switch(lp->state) */
391 restore_flags(flags
);
394 static void a_exint(struct pi_local
*lp
)
402 cli(); /* disable interrupts */
404 st
= rdscc(lp
->cardbase
, lp
->base
+ CTL
, R0
); /* Fetch status */
406 /* reset external status latch */
407 wrtscc(lp
->cardbase
, CTL
+ lp
->base
, R0
, RES_EXT_INT
);
408 cmd
= lp
->base
+ CTL
;
410 if ((lp
->rstate
>= ACTIVE
) && (st
& BRK_ABRT
)) {
414 switch (lp
->tstate
) {
418 lp
->tstate
= FLAGOUT
;
419 tdelay(lp
, lp
->squeldelay
);
422 if ((lp
->sndbuf
= skb_dequeue(&lp
->sndq
)) == NULL
) {
423 /* Nothing to send - return to receive mode */
426 restore_flags(flags
);
429 /* NOTE - fall through if more to send */
431 /* Disable DMA chan */
432 disable_dma(lp
->dmachan
);
434 /* Set up for TX dma */
435 wrtscc(lp
->cardbase
, cmd
, R1
, WT_FN_RDYFN
| EXT_INT_ENAB
);
439 /* Strip KISS control byte */
440 length
= lp
->sndbuf
->len
- 1;
441 memcpy(lp
->txdmabuf
, &lp
->sndbuf
->data
[1], length
);
444 /* Setup DMA controller for tx */
445 setup_tx_dma(lp
, length
);
447 /* select transmit interrupts to enable */
448 /* Allow DMA on chan */
449 enable_dma(lp
->dmachan
);
451 /* reset CRC, Txint pend*/
452 wrtscc(lp
->cardbase
, cmd
, R0
, RES_Tx_CRC
| RES_Tx_P
);
454 /* allow Underrun int only */
455 wrtscc(lp
->cardbase
, cmd
, R15
, TxUIE
);
458 wrtscc(lp
->cardbase
, cmd
, R1
, WT_RDY_ENAB
| WT_FN_RDYFN
| EXT_INT_ENAB
);
460 /* Send CRC on underrun */
461 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EOM_L
);
464 /* packet going out now */
468 /* we have deferred prev xmit attempt
469 * See Intel Microcommunications Handbook, p2-308
471 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
472 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
473 if ((rdscc(lp
->cardbase
, cmd
, R0
) & DCD
) != 0) {
476 /* Defer until dcd transition or 100mS timeout */
477 wrtscc(lp
->cardbase
, CTL
+ lp
->base
, R15
, CTSIE
| DCDIE
);
478 restore_flags(flags
);
481 if (random() > lp
->persist
) {
483 tdelay(lp
, lp
->slotime
);
484 restore_flags(flags
);
487 /* Assert RTS early minimize collision window */
488 wrtscc(lp
->cardbase
, cmd
, R5
, TxCRC_ENAB
| RTS
| Tx8
);
489 rts(lp
, ON
); /* Transmitter on */
490 lp
->tstate
= ST_TXDELAY
;
491 tdelay(lp
, lp
->txdelay
);
492 restore_flags(flags
);
494 } /* switch(lp->tstate) */
496 restore_flags(flags
);
499 /* Receive interrupt handler for the A channel
501 static void a_rxint(struct device
*dev
, struct pi_local
*lp
)
509 struct mbuf
*cur_buf
;
513 cli(); /* disable interrupts */
514 cmd
= lp
->base
+ CTL
;
516 rse
= rdscc(lp
->cardbase
, cmd
, R1
); /* Get special condition bits from R1 */
518 lp
->rstate
= RXERROR
;
521 /* If end of frame */
522 /* figure length of frame from 8237 */
523 clear_dma_ff(lp
->dmachan
);
524 bytecount
= lp
->bufsiz
- get_dma_residue(lp
->dmachan
);
526 if ((rse
& CRC_ERR
) || (lp
->rstate
> ACTIVE
) || (bytecount
< 10)) {
527 if ((bytecount
>= 10) && (rse
& CRC_ERR
)) {
528 lp
->stats
.rx_crc_errors
++;
530 if (lp
->rstate
== RXERROR
) {
531 lp
->stats
.rx_errors
++;
532 lp
->stats
.rx_over_errors
++;
534 /* Reset buffer pointers */
538 /* Here we have a valid frame */
539 /* Toss 2 crc bytes , add one for KISS */
540 pkt_len
= lp
->rcvbuf
->cnt
= bytecount
- 2 + 1;
542 /* Get buffer for next frame */
543 cur_buf
= lp
->rcvbuf
;
548 /* Malloc up new buffer. */
551 skb
= dev_alloc_skb(sksize
);
553 printk(KERN_ERR
"PI: %s: Memory squeeze, dropping packet.\n", dev
->name
);
554 lp
->stats
.rx_dropped
++;
555 restore_flags(flags
);
560 /* KISS kludge - prefix with a 0 byte */
561 cfix
=skb_put(skb
,pkt_len
);
563 /* 'skb->data' points to the start of sk_buff data area. */
564 memcpy(cfix
, (char *) cur_buf
->data
,
566 skb
->protocol
=htons(ETH_P_AX25
);
567 skb
->mac
.raw
=skb
->data
;
569 lp
->stats
.rx_packets
++;
570 } /* end good frame */
571 } /* end EOF check */
572 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R0
, ERR_RES
); /* error reset */
573 restore_flags(flags
);
576 static void b_rxint(struct device
*dev
, struct pi_local
*lp
)
587 cli(); /* disable interrupts */
588 cmd
= CTL
+ lp
->base
;
590 rse
= rdscc(lp
->cardbase
, cmd
, R1
); /* get status byte from R1 */
592 if ((rdscc(lp
->cardbase
, cmd
, R0
)) & Rx_CH_AV
) {
593 /* there is a char to be stored
594 * read special condition bits before reading the data char
597 /* Rx overrun - toss buffer */
598 /* reset buffer pointers */
599 lp
->rcp
= lp
->rcvbuf
->data
;
602 lp
->rstate
= RXERROR
; /* set error flag */
603 lp
->stats
.rx_errors
++;
604 lp
->stats
.rx_over_errors
++;
605 } else if (lp
->rcvbuf
->cnt
>= lp
->bufsiz
) {
606 /* Too large -- toss buffer */
607 /* reset buffer pointers */
608 lp
->rcp
= lp
->rcvbuf
->data
;
610 lp
->rstate
= TOOBIG
;/* when set, chars are not stored */
612 /* ok, we can store the received character now */
613 if (lp
->rstate
== ACTIVE
) { /* If no errors... */
614 *lp
->rcp
++ = rdscc(lp
->cardbase
, cmd
, R8
); /* char to rcv buff */
615 lp
->rcvbuf
->cnt
++; /* bump count */
617 /* got to empty FIFO */
618 (void) rdscc(lp
->cardbase
, cmd
, R8
);
619 wrtscc(lp
->cardbase
, cmd
, R0
, ERR_RES
); /* reset err latch */
624 /* END OF FRAME -- Make sure Rx was active */
625 if (lp
->rcvbuf
->cnt
> 0) {
626 if ((rse
& CRC_ERR
) || (lp
->rstate
> ACTIVE
) || (lp
->rcvbuf
->cnt
< 10)) {
627 if ((lp
->rcvbuf
->cnt
>= 10) && (rse
& CRC_ERR
)) {
628 lp
->stats
.rx_crc_errors
++;
630 lp
->rcp
= lp
->rcvbuf
->data
;
633 /* Here we have a valid frame */
634 pkt_len
= lp
->rcvbuf
->cnt
-= 2; /* Toss 2 crc bytes */
635 pkt_len
+= 1; /* Make room for KISS control byte */
637 /* Malloc up new buffer. */
639 skb
= dev_alloc_skb(sksize
);
641 printk(KERN_ERR
"PI: %s: Memory squeeze, dropping packet.\n", dev
->name
);
642 lp
->stats
.rx_dropped
++;
643 restore_flags(flags
);
648 /* KISS kludge - prefix with a 0 byte */
649 cfix
=skb_put(skb
,pkt_len
);
651 /* 'skb->data' points to the start of sk_buff data area. */
652 memcpy(cfix
, lp
->rcvbuf
->data
, pkt_len
- 1);
653 skb
->protocol
=ntohs(ETH_P_AX25
);
654 skb
->mac
.raw
=skb
->data
;
656 lp
->stats
.rx_packets
++;
657 /* packet queued - initialize buffer for next frame */
658 lp
->rcp
= lp
->rcvbuf
->data
;
661 } /* end good frame queued */
662 } /* end check for active receive upon EOF */
663 lp
->rstate
= ACTIVE
; /* and clear error status */
664 } /* end EOF check */
665 restore_flags(flags
);
669 static void b_txint(struct pi_local
*lp
)
677 cmd
= CTL
+ lp
->base
;
679 switch (lp
->tstate
) {
681 lp
->tstate
= FLAGOUT
;
682 tdelay(lp
, lp
->squeldelay
);
683 restore_flags(flags
);
686 /* Transmitter idle. Find a frame for transmission */
687 if ((lp
->sndbuf
= skb_dequeue(&lp
->sndq
)) == NULL
) {
688 /* Nothing to send - return to receive mode
689 * Tx OFF now - flag should have gone
693 restore_flags(flags
);
696 lp
->txptr
= lp
->sndbuf
->data
;
697 lp
->txptr
++; /* Ignore KISS control byte */
698 lp
->txcnt
= (int) lp
->sndbuf
->len
- 1;
699 /* If a buffer to send, we drop thru here */
700 case DEFER
: /* we may have deferred prev xmit attempt */
701 /* Check DCD - debounce it */
702 /* See Intel Microcommunications Handbook, p2-308 */
703 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
704 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
705 if ((rdscc(lp
->cardbase
, cmd
, R0
) & DCD
) != 0) {
708 /* defer until DCD transition or timeout */
709 wrtscc(lp
->cardbase
, cmd
, R15
, CTSIE
| DCDIE
);
710 restore_flags(flags
);
713 if (random() > lp
->persist
) {
715 tdelay(lp
, lp
->slotime
);
716 restore_flags(flags
);
719 rts(lp
, ON
); /* Transmitter on */
720 lp
->tstate
= ST_TXDELAY
;
721 tdelay(lp
, lp
->txdelay
);
722 restore_flags(flags
);
726 /* Here we are actively sending a frame */
729 /* next char is gone */
730 wrtscc(lp
->cardbase
, cmd
, R8
, c
);
731 /* stuffing a char satisfies Interrupt condition */
733 /* No more to send */
736 if ((rdscc(lp
->cardbase
, cmd
, R0
) & 0x40)) {
737 /* Did we underrun? */
738 /* unexpected underrun */
739 lp
->stats
.tx_errors
++;
740 lp
->stats
.tx_fifo_errors
++;
741 wrtscc(lp
->cardbase
, cmd
, R0
, SEND_ABORT
);
742 lp
->tstate
= FLAGOUT
;
743 tdelay(lp
, lp
->squeldelay
);
744 restore_flags(flags
);
747 lp
->tstate
= UNDERRUN
; /* Now we expect to underrun */
748 /* Send flags on underrun */
749 if (lp
->speed
) { /* If internally clocked */
750 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| NRZI
);
752 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
);
754 wrtscc(lp
->cardbase
, cmd
, R0
, RES_Tx_P
); /* reset Tx Int Pend */
756 restore_flags(flags
);
757 return; /* back to wait for interrupt */
759 restore_flags(flags
);
762 /* Pi SIO External/Status interrupts (for the B channel)
763 * This can be caused by a receiver abort, or a Tx UNDERRUN/EOM.
764 * Receiver automatically goes to Hunt on an abort.
766 * If the Tx Underrun interrupt hits, change state and
767 * issue a reset command for it, and return.
769 static void b_exint(struct pi_local
*lp
)
776 cmd
= CTL
+ lp
->base
;
778 cli(); /* disable interrupts */
779 st
= rdscc(lp
->cardbase
, cmd
, R0
); /* Fetch status */
780 /* reset external status latch */
781 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
784 switch (lp
->tstate
) {
785 case ACTIVE
: /* Unexpected underrun */
788 wrtscc(lp
->cardbase
, cmd
, R0
, SEND_ABORT
);
789 lp
->tstate
= FLAGOUT
;
790 lp
->stats
.tx_errors
++;
791 lp
->stats
.tx_fifo_errors
++;
792 tdelay(lp
, lp
->squeldelay
);
793 restore_flags(flags
);
797 restore_flags(flags
);
800 /* Find a frame for transmission */
801 if ((lp
->sndbuf
= skb_dequeue(&lp
->sndq
)) == NULL
) {
802 /* Nothing to send - return to receive mode
803 * Tx OFF now - flag should have gone
807 restore_flags(flags
);
810 lp
->txptr
= lp
->sndbuf
->data
;
811 lp
->txptr
++; /* Ignore KISS control byte */
812 lp
->txcnt
= (int) lp
->sndbuf
->len
- 1;
813 /* Get first char to send */
816 wrtscc(lp
->cardbase
, cmd
, R0
, RES_Tx_CRC
); /* reset for next frame */
818 /* Send abort on underrun */
819 if (lp
->speed
) { /* If internally clocked */
820 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| NRZI
| ABUNDER
);
822 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| ABUNDER
);
825 wrtscc(lp
->cardbase
, cmd
, R8
, c
); /* First char out now */
826 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EOM_L
); /* Reset end of message latch */
829 /* stuff an extra one if we can */
833 /* Wait for tx buffer empty */
834 while((rdscc(lp
->cardbase
, cmd
, R0
) & 0x04) == 0)
836 wrtscc(lp
->cardbase
, cmd
, R8
, c
);
840 /* select transmit interrupts to enable */
842 wrtscc(lp
->cardbase
, cmd
, R15
, TxUIE
); /* allow Underrun int only */
843 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
844 wrtscc(lp
->cardbase
, cmd
, R1
, TxINT_ENAB
| EXT_INT_ENAB
); /* Tx/Ext ints */
846 lp
->tstate
= ACTIVE
; /* char going out now */
847 restore_flags(flags
);
851 /* Check DCD - debounce it
852 * See Intel Microcommunications Handbook, p2-308
854 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
855 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
856 if ((rdscc(lp
->cardbase
, cmd
, R0
) & DCD
) != 0) {
859 /* defer until DCD transition or timeout */
860 wrtscc(lp
->cardbase
, cmd
, R15
, CTSIE
| DCDIE
);
861 restore_flags(flags
);
864 if (random() > lp
->persist
) {
866 tdelay(lp
, lp
->slotime
);
867 restore_flags(flags
);
870 rts(lp
, ON
); /* Transmitter on */
871 lp
->tstate
= ST_TXDELAY
;
872 tdelay(lp
, lp
->txdelay
);
873 restore_flags(flags
);
878 /* Get first char to send */
881 wrtscc(lp
->cardbase
, cmd
, R0
, RES_Tx_CRC
); /* reset for next frame */
883 /* Send abort on underrun */
884 if (lp
->speed
) { /* If internally clocked */
885 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| NRZI
| ABUNDER
);
887 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| ABUNDER
);
890 wrtscc(lp
->cardbase
, cmd
, R8
, c
); /* First char out now */
891 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EOM_L
); /* Reset end of message latch */
894 /* stuff an extra one if we can */
898 /* Wait for tx buffer empty */
899 while((rdscc(lp
->cardbase
, cmd
, R0
) & 0x04) == 0)
901 wrtscc(lp
->cardbase
, cmd
, R8
, c
);
905 /* select transmit interrupts to enable */
907 wrtscc(lp
->cardbase
, cmd
, R15
, TxUIE
); /* allow Underrun int only */
908 wrtscc(lp
->cardbase
, cmd
, R0
, RES_EXT_INT
);
909 /* Tx/Extern ints on */
910 wrtscc(lp
->cardbase
, cmd
, R1
, TxINT_ENAB
| EXT_INT_ENAB
);
912 lp
->tstate
= ACTIVE
; /* char going out now */
913 restore_flags(flags
);
918 * This triggers when hunt mode is entered, & since an ABORT
919 * automatically enters hunt mode, we use that to clean up
920 * any waiting garbage
922 if ((lp
->rstate
== ACTIVE
) && (st
& BRK_ABRT
)) {
923 (void) rdscc(lp
->cardbase
, cmd
, R8
);
924 (void) rdscc(lp
->cardbase
, cmd
, R8
);
925 (void) rdscc(lp
->cardbase
, cmd
, R8
);
926 lp
->rcp
= lp
->rcvbuf
->data
;
927 lp
->rcvbuf
->cnt
= 0; /* rewind on DCD transition */
929 restore_flags(flags
);
932 /* Probe for a PI card. */
933 /* This routine also initializes the timer chip */
935 __initfunc(static int hw_probe(int ioaddr
))
937 int time
= 1000; /* Number of milliseconds for test */
938 unsigned long start_time
, end_time
;
940 int base
, tmr0
, tmr1
, tmrcmd
;
944 base
= ioaddr
& 0x3f0;
947 tmrcmd
= TMRCMD
+ base
;
949 /* Set up counter chip timer 0 for 500 uS period square wave */
950 /* assuming a 3.68 mhz clock for now */
951 outb_p(SC0
| LSB_MSB
| MODE3
, tmrcmd
);
952 outb_p(922 & 0xFF, tmr0
);
953 outb_p(922 >> 8, tmr0
);
955 /* Setup timer control word for timer 1*/
956 outb_p(SC1
| LSB_MSB
| MODE0
, tmrcmd
);
957 outb_p((time
<< 1) & 0xFF, tmr1
);
958 outb_p((time
>> 7) & 0XFF, tmr1
);
960 /* wait until counter reg is loaded */
962 /* Latch count for reading */
967 start_time
= jiffies
;
969 /* Latch count for reading */
974 /* Don't wait forever - there may be no card here */
975 if ((end_time
- start_time
) > 200)
976 return 0; /* No card found */
979 /* 87 jiffies, for a 3.68 mhz clock, half that for a double speed clock */
980 if ((end_time
- start_time
) > 65) {
981 return (1); /* PI card found */
983 /* Faster crystal - tmr0 needs adjusting */
984 /* Set up counter chip */
985 /* 500 uS square wave */
986 outb_p(SC0
| LSB_MSB
| MODE3
, tmrcmd
);
987 outb_p(1844 & 0xFF, tmr0
);
988 outb_p(1844 >> 8, tmr0
);
989 return (2); /* PI2 card found */
993 static void rts(struct pi_local
*lp
, int x
)
1000 /* assumes interrupts are off */
1001 cmd
= CTL
+ lp
->base
;
1003 /* Reprogram BRG and turn on transmitter to send flags */
1004 if (x
== ON
) { /* Turn Tx ON and Receive OFF */
1005 /* Exints off first to avoid abort int */
1006 wrtscc(lp
->cardbase
, cmd
, R15
, 0);
1007 wrtscc(lp
->cardbase
, cmd
, R3
, Rx8
); /* Rx off */
1009 if (cmd
& 2) { /* if channel a */
1010 /* Set up for TX dma */
1011 wrtscc(lp
->cardbase
, cmd
, R1
, WT_FN_RDYFN
| EXT_INT_ENAB
);
1013 wrtscc(lp
->cardbase
, cmd
, R1
, 0); /* No interrupts */
1016 if (!lp
->clockmode
) {
1017 if (lp
->speed
) { /* if internally clocked */
1018 br
= lp
->speed
; /* get desired speed */
1019 tc
= (lp
->xtal
/ br
) - 2; /* calc 1X BRG divisor */
1020 wrtscc(lp
->cardbase
, cmd
, R12
, tc
& 0xFF); /* lower byte */
1021 wrtscc(lp
->cardbase
, cmd
, R13
, (tc
>> 8) & 0xFF); /* upper byte */
1024 wrtscc(lp
->cardbase
, cmd
, R5
, TxCRC_ENAB
| RTS
| TxENAB
| Tx8
| DTR
);
1025 /* Transmitter now on */
1026 } else { /* Tx OFF and Rx ON */
1028 wrtscc(lp
->cardbase
, cmd
, R5
, Tx8
| DTR
); /* TX off */
1030 if (!lp
->clockmode
) {
1031 if (lp
->speed
) { /* if internally clocked */
1032 /* Reprogram BRG for 32x clock for receive DPLL */
1033 /* BRG off, keep Pclk source */
1034 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
);
1035 br
= lp
->speed
; /* get desired speed */
1036 /* calc 32X BRG divisor */
1037 tc
= ((lp
->xtal
/ 32) / br
) - 2;
1038 wrtscc(lp
->cardbase
, cmd
, R12
, tc
& 0xFF); /* lower byte */
1039 wrtscc(lp
->cardbase
, cmd
, R13
, (tc
>> 8) & 0xFF); /* upper byte */
1040 /* SEARCH mode, BRG source */
1041 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| SEARCH
);
1042 /* Enable the BRG */
1043 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| BRENABL
);
1047 wrtscc(lp
->cardbase
, cmd
, R3
, Rx8
); /* Make sure rx is off */
1048 wrtscc(lp
->cardbase
, cmd
, R0
, ERR_RES
); /* reset err latch */
1049 dummy
= rdscc(lp
->cardbase
, cmd
, R1
); /* get status byte from R1 */
1050 (void) rdscc(lp
->cardbase
, cmd
, R8
);
1051 (void) rdscc(lp
->cardbase
, cmd
, R8
);
1053 (void) rdscc(lp
->cardbase
, cmd
, R8
);
1055 /* Now, turn on the receiver and hunt for a flag */
1056 wrtscc(lp
->cardbase
, cmd
, R3
, RxENABLE
| Rx8
);
1057 lp
->rstate
= ACTIVE
; /* Normal state */
1059 if (cmd
& 2) { /* if channel a */
1062 /* reset buffer pointers */
1063 lp
->rcp
= lp
->rcvbuf
->data
;
1064 lp
->rcvbuf
->cnt
= 0;
1065 wrtscc(lp
->cardbase
, cmd
, R1
, (INT_ALL_Rx
| EXT_INT_ENAB
));
1067 wrtscc(lp
->cardbase
, cmd
, R15
, BRKIE
); /* allow ABORT int */
1071 static void scc_init(struct device
*dev
)
1073 unsigned long flags
;
1074 struct pi_local
*lp
= (struct pi_local
*) dev
->priv
;
1080 /* Initialize 8530 channel for SDLC operation */
1082 cmd
= CTL
+ lp
->base
;
1086 switch (cmd
& CHANA
) {
1088 wrtscc(lp
->cardbase
, cmd
, R9
, CHRA
); /* Reset channel A */
1089 wrtscc(lp
->cardbase
, cmd
, R2
, 0xff); /* Initialize interrupt vector */
1092 wrtscc(lp
->cardbase
, cmd
, R9
, CHRB
); /* Reset channel B */
1096 /* Deselect all Rx and Tx interrupts */
1097 wrtscc(lp
->cardbase
, cmd
, R1
, 0);
1099 /* Turn off external interrupts (like CTS/CD) */
1100 wrtscc(lp
->cardbase
, cmd
, R15
, 0);
1102 /* X1 clock, SDLC mode */
1103 wrtscc(lp
->cardbase
, cmd
, R4
, SDLC
| X1CLK
);
1105 /* Tx/Rx parameters */
1106 if (lp
->speed
) { /* Use internal clocking */
1107 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
| NRZI
);
1109 /* Tx Clk from BRG. Rcv Clk from DPLL, TRxC pin outputs DPLL */
1110 wrtscc(lp
->cardbase
, cmd
, R11
, TCBR
| RCDPLL
| TRxCDP
| TRxCOI
);
1112 /* Tx Clk from DPLL, Rcv Clk from DPLL, TRxC Outputs BRG */
1113 wrtscc(lp
->cardbase
, cmd
, R11
, TCDPLL
| RCDPLL
| TRxCBR
| TRxCOI
);
1114 } else { /* Use external clocking */
1115 wrtscc(lp
->cardbase
, cmd
, R10
, CRCPS
);
1116 /* Tx Clk from Trxcl. Rcv Clk from Rtxcl, TRxC pin is input */
1117 wrtscc(lp
->cardbase
, cmd
, R11
, TCTRxCP
);
1120 /* Null out SDLC start address */
1121 wrtscc(lp
->cardbase
, cmd
, R6
, 0);
1124 wrtscc(lp
->cardbase
, cmd
, R7
, FLAG
);
1126 /* Set up the Transmitter but don't enable it
1127 * DTR, 8 bit TX chars only
1129 wrtscc(lp
->cardbase
, cmd
, R5
, Tx8
| DTR
);
1131 /* Receiver initial setup */
1132 wrtscc(lp
->cardbase
, cmd
, R3
, Rx8
); /* 8 bits/char */
1134 /* Setting up BRG now - turn it off first */
1135 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
); /* BRG off, keep Pclk source */
1137 /* set the 32x time constant for the BRG in Receive mode */
1140 br
= lp
->speed
; /* get desired speed */
1141 tc
= ((lp
->xtal
/ 32) / br
) - 2; /* calc 32X BRG divisor */
1146 wrtscc(lp
->cardbase
, cmd
, R12
, tc
& 0xFF); /* lower byte */
1147 wrtscc(lp
->cardbase
, cmd
, R13
, (tc
>> 8) & 0xFF); /* upper byte */
1149 /* Following subroutine sets up and ENABLES the receiver */
1150 rts(lp
, OFF
); /* TX OFF and RX ON */
1153 /* DPLL frm BRG, BRG src PCLK */
1154 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| SSBR
);
1156 /* DPLL frm rtxc,BRG src PCLK */
1157 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| SSRTxC
);
1159 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| SEARCH
); /* SEARCH mode, keep BRG src */
1160 wrtscc(lp
->cardbase
, cmd
, R14
, BRSRC
| BRENABL
); /* Enable the BRG */
1162 if (!(cmd
& 2)) /* if channel b */
1163 wrtscc(lp
->cardbase
, cmd
, R1
, (INT_ALL_Rx
| EXT_INT_ENAB
));
1165 wrtscc(lp
->cardbase
, cmd
, R15
, BRKIE
); /* ABORT int */
1167 /* Now, turn on the receiver and hunt for a flag */
1168 wrtscc(lp
->cardbase
, cmd
, R3
, RxENABLE
| RxCRC_ENAB
| Rx8
);
1170 restore_flags(flags
);
1173 static void chipset_init(struct device
*dev
)
1176 unsigned long flags
;
1178 cardbase
= dev
->base_addr
& 0x3f0;
1182 wrtscc(cardbase
, dev
->base_addr
+ CTL
, R9
, FHWRES
); /* Hardware reset */
1183 /* Disable interrupts with master interrupt ctrl reg */
1184 wrtscc(cardbase
, dev
->base_addr
+ CTL
, R9
, 0);
1185 restore_flags(flags
);
1190 __initfunc(int pi_init(void))
1195 int ports
[] = {0x380, 0x300, 0x320, 0x340, 0x360, 0x3a0, 0};
1197 printk(KERN_INFO
"PI: V0.8 ALPHA April 23 1995 David Perry (dp@hydra.carleton.ca)\n");
1199 /* Only one card supported for now */
1200 for (port
= &ports
[0]; *port
&& !card_type
; port
++) {
1203 if (check_region(ioaddr
, PI_TOTAL_SIZE
) == 0) {
1204 printk(KERN_INFO
"PI: Probing for card at address %#3x\n",ioaddr
);
1205 card_type
= hw_probe(ioaddr
);
1209 switch (card_type
) {
1211 printk(KERN_INFO
"PI: Found a PI card at address %#3x\n", ioaddr
);
1214 printk(KERN_INFO
"PI: Found a PI2 card at address %#3x\n", ioaddr
);
1217 printk(KERN_ERR
"PI: ERROR: No card found\n");
1221 /* Link a couple of device structures into the chain */
1222 /* For the A port */
1223 /* Allocate space for 4 buffers even though we only need 3,
1224 because one of them may cross a DMA page boundary and
1225 be rejected by get_dma_buffer().
1227 register_netdev(&pi0a
);
1229 pi0a
.priv
= kmalloc(sizeof(struct pi_local
) + (DMA_BUFF_SIZE
+ sizeof(struct mbuf
)) * 4, GFP_KERNEL
| GFP_DMA
);
1232 pi0a
.base_addr
= ioaddr
+ 2;
1235 /* And the B port */
1236 register_netdev(&pi0b
);
1237 pi0b
.base_addr
= ioaddr
;
1240 pi0b
.priv
= kmalloc(sizeof(struct pi_local
) + (DMA_BUFF_SIZE
+ sizeof(struct mbuf
)) * 4, GFP_KERNEL
| GFP_DMA
);
1242 /* Now initialize them */
1243 pi_probe(&pi0a
, card_type
);
1244 pi_probe(&pi0b
, card_type
);
1246 pi0b
.irq
= pi0a
.irq
; /* IRQ is shared */
1251 static int valid_dma_page(unsigned long addr
, unsigned long dev_buffsize
)
1253 if (((addr
& 0xffff) + dev_buffsize
) <= 0x10000)
1259 static int pi_set_mac_address(struct device
*dev
, void *addr
)
1261 struct sockaddr
*sa
= (struct sockaddr
*)addr
;
1262 memcpy(dev
->dev_addr
, sa
->sa_data
, dev
->addr_len
); /* addr is an AX.25 shifted ASCII */
1263 return 0; /* mac address */
1266 /* Allocate a buffer which does not cross a DMA page boundary */
1268 get_dma_buffer(unsigned long *mem_ptr
)
1272 ret
= (char *)*mem_ptr
;
1274 if(!valid_dma_page(*mem_ptr
, DMA_BUFF_SIZE
+ sizeof(struct mbuf
))){
1275 *mem_ptr
+= (DMA_BUFF_SIZE
+ sizeof(struct mbuf
));
1276 ret
= (char *)*mem_ptr
;
1278 *mem_ptr
+= (DMA_BUFF_SIZE
+ sizeof(struct mbuf
));
1282 static int pi_probe(struct device
*dev
, int card_type
)
1285 struct pi_local
*lp
;
1286 unsigned long flags
;
1287 unsigned long mem_ptr
;
1289 ioaddr
= dev
->base_addr
;
1291 /* Initialize the device structure. */
1292 /* Must be done before chipset_init */
1293 /* Make certain the data structures used by the PI2 are aligned. */
1294 dev
->priv
= (void *) (((int) dev
->priv
+ 7) & ~7);
1295 lp
= (struct pi_local
*) dev
->priv
;
1297 memset(dev
->priv
, 0, sizeof(struct pi_local
));
1299 /* Allocate some buffers which do not cross DMA page boundaries */
1300 mem_ptr
= (unsigned long) dev
->priv
+ sizeof(struct pi_local
);
1301 lp
->txdmabuf
= get_dma_buffer(&mem_ptr
);
1302 lp
->rxdmabuf1
= (struct mbuf
*) get_dma_buffer(&mem_ptr
);
1303 lp
->rxdmabuf2
= (struct mbuf
*) get_dma_buffer(&mem_ptr
);
1305 /* Initialize rx buffer */
1306 lp
->rcvbuf
= lp
->rxdmabuf1
;
1307 lp
->rcp
= lp
->rcvbuf
->data
;
1308 lp
->rcvbuf
->cnt
= 0;
1310 /* Initialize the transmit queue head structure */
1311 skb_queue_head_init(&lp
->sndq
);
1313 /* These need to be initialized before scc_init is called. */
1315 lp
->xtal
= (unsigned long) SINGLE
/ 2;
1317 lp
->xtal
= (unsigned long) DOUBLE
/ 2;
1318 lp
->base
= dev
->base_addr
;
1319 lp
->cardbase
= dev
->base_addr
& 0x3f0;
1320 if (dev
->base_addr
& CHANA
) {
1321 lp
->speed
= DEF_A_SPEED
;
1322 /* default channel access Params */
1323 lp
->txdelay
= DEF_A_TXDELAY
;
1324 lp
->persist
= DEF_A_PERSIST
;
1325 lp
->slotime
= DEF_A_SLOTIME
;
1326 lp
->squeldelay
= DEF_A_SQUELDELAY
;
1327 lp
->clockmode
= DEF_A_CLOCKMODE
;
1330 lp
->speed
= DEF_B_SPEED
;
1331 /* default channel access Params */
1332 lp
->txdelay
= DEF_B_TXDELAY
;
1333 lp
->persist
= DEF_B_PERSIST
;
1334 lp
->slotime
= DEF_B_SLOTIME
;
1335 lp
->squeldelay
= DEF_B_SQUELDELAY
;
1336 lp
->clockmode
= DEF_B_CLOCKMODE
;
1338 lp
->bufsiz
= DMA_BUFF_SIZE
;
1343 if (dev
->base_addr
& CHANA
) { /* Do these things only for the A port */
1344 /* Note that a single IRQ services 2 devices (A and B channels) */
1346 lp
->dmachan
= dev
->dma
;
1347 if (lp
->dmachan
< 1 || lp
->dmachan
> 3)
1348 printk(KERN_ERR
"PI: DMA channel %d out of range\n", lp
->dmachan
);
1350 /* chipset_init() was already called */
1356 wrtscc(lp
->cardbase
, CTL
+ lp
->base
, R1
, EXT_INT_ENAB
);
1357 /* enable PI card interrupts */
1358 wrtscc(lp
->cardbase
, CTL
+ lp
->base
, R9
, MIE
| NV
);
1359 restore_flags(flags
);
1360 /* request a timer interrupt for 1 mS hence */
1362 /* 20 "jiffies" should be plenty of time... */
1363 dev
->irq
= autoirq_report(20);
1365 printk(KERN_ERR
"PI: Failed to detect IRQ line.\n");
1369 wrtscc(lp
->cardbase
, dev
->base_addr
+ CTL
, R9
, FHWRES
); /* Hardware reset */
1370 /* Disable interrupts with master interrupt ctrl reg */
1371 wrtscc(lp
->cardbase
, dev
->base_addr
+ CTL
, R9
, 0);
1372 restore_flags(flags
);
1375 printk(KERN_INFO
"PI: Autodetected IRQ %d, assuming DMA %d.\n",
1376 dev
->irq
, dev
->dma
);
1378 /* This board has jumpered interrupts. Snarf the interrupt vector
1379 now. There is no point in waiting since no other device can use
1380 the interrupt, and this marks the 'irqaction' as busy. */
1382 int irqval
= request_irq(dev
->irq
, &pi_interrupt
,0, "pi2", NULL
);
1384 printk(KERN_ERR
"PI: unable to get IRQ %d (irqval=%d).\n",
1390 /* Grab the region */
1391 request_region(ioaddr
& 0x3f0, PI_TOTAL_SIZE
, "pi2" );
1394 } /* Only for A port */
1395 dev
->open
= pi_open
;
1396 dev
->stop
= pi_close
;
1397 dev
->do_ioctl
= pi_ioctl
;
1398 dev
->hard_start_xmit
= pi_send_packet
;
1399 dev
->get_stats
= pi_get_stats
;
1401 /* Fill in the fields of the device structure */
1403 dev_init_buffers(dev
);
1405 #if defined(CONFIG_AX25) || defined(CONFIG_AX25_MODULE)
1406 dev
->hard_header
= ax25_encapsulate
;
1407 dev
->rebuild_header
= ax25_rebuild_header
;
1410 dev
->set_mac_address
= pi_set_mac_address
;
1412 dev
->type
= ARPHRD_AX25
; /* AF_AX25 device */
1413 dev
->hard_header_len
= 73; /* We do digipeaters now */
1414 dev
->mtu
= 1500; /* eth_mtu is the default */
1415 dev
->addr_len
= 7; /* sizeof an ax.25 address */
1416 memcpy(dev
->broadcast
, ax25_bcast
, 7);
1417 memcpy(dev
->dev_addr
, ax25_test
, 7);
1419 /* New-style flags. */
1421 dev
->family
= AF_INET
;
1423 dev
->pa_brdaddr
= 0;
1430 /* Open/initialize the board. This is called (in the current kernel)
1431 sometime after booting when the 'ifconfig' program is run.
1433 This routine should set everything up anew at each open, even
1434 registers that "should" only need to be set once at boot, so that
1435 there is non-reboot way to recover if something goes wrong.
1437 static int pi_open(struct device
*dev
)
1439 unsigned long flags
;
1440 static first_time
= 1;
1442 struct pi_local
*lp
= (struct pi_local
*) dev
->priv
;
1444 if (dev
->base_addr
& 2) { /* if A channel */
1446 if (request_dma(dev
->dma
,"pi2")) {
1447 free_irq(dev
->irq
, NULL
);
1450 irq2dev_map
[dev
->irq
] = dev
;
1452 /* Reset the hardware here. */
1457 if (dev
->base_addr
& 2) { /* if A channel */
1458 scc_init(dev
); /* Called once for each channel */
1459 scc_init(dev
->next
);
1461 /* master interrupt enable */
1464 wrtscc(lp
->cardbase
, CTL
+ lp
->base
, R9
, MIE
| NV
);
1465 restore_flags(flags
);
1467 lp
->open_time
= jiffies
;
1479 static int pi_send_packet(struct sk_buff
*skb
, struct device
*dev
)
1481 struct pi_local
*lp
= (struct pi_local
*) dev
->priv
;
1483 hardware_send_packet(lp
, skb
);
1484 dev
->trans_start
= jiffies
;
1489 /* The typical workload of the driver:
1490 Handle the network interface interrupts. */
1491 static void pi_interrupt(int reg_ptr
, void *dev_id
, struct pt_regs
*regs
)
1493 /* int irq = -(((struct pt_regs *) reg_ptr)->orig_eax + 2);*/
1494 struct pi_local
*lp
;
1496 unsigned long flags
;
1498 /* dev_b = dev_a->next; Relies on the order defined in Space.c */
1501 if (dev_a
== NULL
) {
1502 printk(KERN_ERR
"PI: pi_interrupt(): irq %d for unknown device.\n", irq
);
1506 /* Read interrupt status register (only valid from channel A)
1507 * Process all pending interrupts in while loop
1509 lp
= (struct pi_local
*) pi0a
.priv
; /* Assume channel A */
1510 while ((st
= rdscc(lp
->cardbase
, pi0a
.base_addr
| CHANA
| CTL
, R3
)) != 0) {
1512 /* Channel B Transmit Int Pending */
1513 lp
= (struct pi_local
*) pi0b
.priv
;
1515 } else if (st
& CHARxIP
) {
1516 /* Channel A Rcv Interrupt Pending */
1517 lp
= (struct pi_local
*) pi0a
.priv
;
1519 } else if (st
& CHATxIP
) {
1520 /* Channel A Transmit Int Pending */
1521 lp
= (struct pi_local
*) pi0a
.priv
;
1523 } else if (st
& CHAEXT
) {
1524 /* Channel A External Status Int */
1525 lp
= (struct pi_local
*) pi0a
.priv
;
1527 } else if (st
& CHBRxIP
) {
1528 /* Channel B Rcv Interrupt Pending */
1529 lp
= (struct pi_local
*) pi0b
.priv
;
1531 } else if (st
& CHBEXT
) {
1532 /* Channel B External Status Int */
1533 lp
= (struct pi_local
*) pi0b
.priv
;
1536 /* Reset highest interrupt under service */
1539 wrtscc(lp
->cardbase
, lp
->base
+ CTL
, R0
, RES_H_IUS
);
1540 restore_flags(flags
);
1541 } /* End of while loop on int processing */
1545 /* The inverse routine to pi_open(). */
1546 static int pi_close(struct device
*dev
)
1548 unsigned long flags
;
1549 struct pi_local
*lp
;
1550 struct sk_buff
*ptr
;
1555 lp
= (struct pi_local
*) dev
->priv
;
1558 chipset_init(dev
); /* reset the scc */
1559 disable_dma(lp
->dmachan
);
1566 /* Free any buffers left in the hardware transmit queue */
1567 while ((ptr
= skb_dequeue(&lp
->sndq
)) != NULL
)
1570 restore_flags(flags
);
1577 static int pi_ioctl(struct device
*dev
, struct ifreq
*ifr
, int cmd
)
1579 unsigned long flags
;
1581 struct pi_local
*lp
= (struct pi_local
*) dev
->priv
;
1583 int ret
= verify_area(VERIFY_WRITE
, ifr
->ifr_data
, sizeof(struct pi_req
));
1587 if(cmd
!=SIOCDEVPRIVATE
)
1590 copy_from_user(&rq
, ifr
->ifr_data
, sizeof(struct pi_req
));
1599 lp
->txdelay
= rq
.txdelay
;
1600 lp
->persist
= rq
.persist
;
1601 lp
->slotime
= rq
.slotime
;
1602 lp
->squeldelay
= rq
.squeldelay
;
1603 lp
->clockmode
= rq
.clockmode
;
1604 lp
->speed
= rq
.speed
;
1605 pi_open(&pi0a
); /* both channels get reset %%% */
1606 restore_flags(flags
);
1615 if (dev
->base_addr
& 2) { /* if A channel */
1616 if (rq
.dmachan
< 1 || rq
.dmachan
> 3)
1621 free_dma(lp
->dmachan
);
1622 dev
->dma
= lp
->dmachan
= rq
.dmachan
;
1623 if (request_dma(lp
->dmachan
,"pi2"))
1626 restore_flags(flags
);
1631 ret
= -EINVAL
; /* add this later */
1638 rq
.speed
= lp
->speed
;
1639 rq
.txdelay
= lp
->txdelay
;
1640 rq
.persist
= lp
->persist
;
1641 rq
.slotime
= lp
->slotime
;
1642 rq
.squeldelay
= lp
->squeldelay
;
1643 rq
.clockmode
= lp
->clockmode
;
1644 rq
.dmachan
= lp
->dmachan
;
1646 copy_to_user(ifr
->ifr_data
, &rq
, sizeof(struct pi_req
));
1656 /* Get the current statistics. This may be called with the card open or
1658 static struct net_device_stats
*pi_get_stats(struct device
*dev
)
1660 struct pi_local
*lp
= (struct pi_local
*) dev
->priv
;
1668 int init_module(void)
1673 void cleanup_module(void)
1675 free_irq(pi0a
.irq
, NULL
); /* IRQs and IO Ports are shared */
1676 release_region(pi0a
.base_addr
& 0x3f0, PI_TOTAL_SIZE
);
1677 irq2dev_map
[pi0a
.irq
] = NULL
;
1681 unregister_netdev(&pi0a
);
1685 unregister_netdev(&pi0b
);
1691 * compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c skeleton.c"
1692 * version-control: t
1693 * kept-new-versions: 5