| blob | 5e50cbfa553241ce1888d56b9bf4a351b173c109 |
1 /*
2 * File Name:
3 * defxx.c
4 *
5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996.
7 *
8 * This software may be used and distributed according to the terms of
9 * the GNU Public License, incorporated herein by reference.
10 *
11 * Abstract:
12 * A Linux device driver supporting the Digital Equipment Corporation
13 * FDDI EISA and PCI controller families. Supported adapters include:
14 *
15 * DEC FDDIcontroller/EISA (DEFEA)
16 * DEC FDDIcontroller/PCI (DEFPA)
17 *
18 * Maintainers:
19 * LVS Lawrence V. Stefani
20 *
21 * Contact:
22 * The author may be reached at:
23 *
24 * Inet: stefani@lkg.dec.com
25 * Mail: Digital Equipment Corporation
26 * 550 King Street
27 * M/S: LKG1-3/M07
28 * Littleton, MA 01460
29 *
30 * Credits:
31 * I'd like to thank Patricia Cross for helping me get started with
32 * Linux, David Davies for a lot of help upgrading and configuring
33 * my development system and for answering many OS and driver
34 * development questions, and Alan Cox for recommendations and
35 * integration help on getting FDDI support into Linux. LVS
36 *
37 * Driver Architecture:
38 * The driver architecture is largely based on previous driver work
39 * for other operating systems. The upper edge interface and
40 * functions were largely taken from existing Linux device drivers
41 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
42 * driver.
43 *
44 * Adapter Probe -
45 * The driver scans for supported EISA adapters by reading the
46 * SLOT ID register for each EISA slot and making a match
47 * against the expected value. The supported PCI adapters are
48 * discovered using successive calls to pcibios_find_device.
49 * The first time the probe routine is called, all supported
50 * devices are discovered and initialized. The adapters aren't
51 * brought up to an operational state until the open routine is
52 * called.
53 *
54 * Bus-Specific Initialization -
55 * This driver currently supports both EISA and PCI controller
56 * families. While the custom DMA chip and FDDI logic is similar
57 * or identical, the bus logic is very different. After
58 * initialization, the only bus-specific differences is in how the
59 * driver enables and disables interrupts. Other than that, the
60 * run-time critical code behaves the same on both families.
61 * It's important to note that both adapter families are configured
62 * to I/O map, rather than memory map, the adapter registers.
63 *
64 * Driver Open/Close -
65 * In the driver open routine, the driver ISR (interrupt service
66 * routine) is registered and the adapter is brought to an
67 * operational state. In the driver close routine, the opposite
68 * occurs; the driver ISR is deregistered and the adapter is
69 * brought to a safe, but closed state. Users may use consecutive
70 * commands to bring the adapter up and down as in the following
71 * example:
72 * ifconfig fddi0 up
73 * ifconfig fddi0 down
74 * ifconfig fddi0 up
75 *
76 * Driver Shutdown -
77 * Apparently, there is no shutdown or halt routine support under
78 * Linux. This routine would be called during "reboot" or
79 * "shutdown" to allow the driver to place the adapter in a safe
80 * state before a warm reboot occurs. To be really safe, the user
81 * should close the adapter before shutdown (eg. ifconfig fddi0 down)
82 * to ensure that the adapter DMA engine is taken off-line. However,
83 * the current driver code anticipates this problem and always issues
84 * a soft reset of the adapter at the beginning of driver initialization.
85 * A future driver enhancement in this area may occur in 2.1.X where
86 * Alan indicated that a shutdown handler may be implemented.
87 *
88 * Interrupt Service Routine -
89 * The driver supports shared interrupts, so the ISR is registered for
90 * each board with the appropriate flag and the pointer to that board's
91 * device structure. This provides the context during interrupt
92 * processing to support shared interrupts and multiple boards.
93 *
94 * Interrupt enabling/disabling can occur at many levels. At the host
95 * end, you can disable system interrupts, or disable interrupts at the
96 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters
97 * have a bus-logic chip interrupt enable/disable as well as a DMA
98 * controller interrupt enable/disable.
99 *
100 * The driver currently enables and disables adapter interrupts at the
101 * bus-logic chip and assumes that Linux will take care of clearing or
102 * acknowledging any host-based interrupt chips.
103 *
104 * Control Functions -
105 * Control functions are those used to support functions such as adding
106 * or deleting multicast addresses, enabling or disabling packet
107 * reception filters, or other custom/proprietary commands. Presently,
108 * the driver supports the "get statistics", "set multicast list", and
109 * "set mac address" functions defined by Linux. A list of possible
110 * enhancements include:
111 *
112 * - Custom ioctl interface for executing port interface commands
113 * - Custom ioctl interface for adding unicast addresses to
114 * adapter CAM (to support bridge functions).
115 * - Custom ioctl interface for supporting firmware upgrades.
116 *
117 * Hardware (port interface) Support Routines -
118 * The driver function names that start with "dfx_hw_" represent
119 * low-level port interface routines that are called frequently. They
120 * include issuing a DMA or port control command to the adapter,
121 * resetting the adapter, or reading the adapter state. Since the
122 * driver initialization and run-time code must make calls into the
123 * port interface, these routines were written to be as generic and
124 * usable as possible.
125 *
126 * Receive Path -
127 * The adapter DMA engine supports a 256 entry receive descriptor block
128 * of which up to 255 entries can be used at any given time. The
129 * architecture is a standard producer, consumer, completion model in
130 * which the driver "produces" receive buffers to the adapter, the
131 * adapter "consumes" the receive buffers by DMAing incoming packet data,
132 * and the driver "completes" the receive buffers by servicing the
133 * incoming packet, then "produces" a new buffer and starts the cycle
134 * again. Receive buffers can be fragmented in up to 16 fragments
135 * (descriptor entries). For simplicity, this driver posts
136 * single-fragment receive buffers of 4608 bytes, then allocates a
137 * sk_buff, copies the data, then reposts the buffer. To reduce CPU
138 * utilization, a better approach would be to pass up the receive
139 * buffer (no extra copy) then allocate and post a replacement buffer.
140 * This is a performance enhancement that should be looked into at
141 * some point.
142 *
143 * Transmit Path -
144 * Like the receive path, the adapter DMA engine supports a 256 entry
145 * transmit descriptor block of which up to 255 entries can be used at
146 * any given time. Transmit buffers can be fragmented in up to 255
147 * fragments (descriptor entries). This driver always posts one
148 * fragment per transmit packet request.
149 *
150 * The fragment contains the entire packet from FC to end of data.
151 * Before posting the buffer to the adapter, the driver sets a three-byte
152 * packet request header (PRH) which is required by the Motorola MAC chip
153 * used on the adapters. The PRH tells the MAC the type of token to
154 * receive/send, whether or not to generate and append the CRC, whether
155 * synchronous or asynchronous framing is used, etc. Since the PRH
156 * definition is not necessarily consistent across all FDDI chipsets,
157 * the driver, rather than the common FDDI packet handler routines,
158 * sets these bytes.
159 *
160 * To reduce the amount of descriptor fetches needed per transmit request,
161 * the driver takes advantage of the fact that there are at least three
162 * bytes available before the skb->data field on the outgoing transmit
163 * request. This is guaranteed by having fddi_setup() in net_init.c set
164 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest
165 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad"
166 * bytes which we'll use to store the PRH.
167 *
168 * There's a subtle advantage to adding these pad bytes to the
169 * hard_header_len, it ensures that the data portion of the packet for
170 * an 802.2 SNAP frame is longword aligned. Other FDDI driver
171 * implementations may not need the extra padding and can start copying
172 * or DMAing directly from the FC byte which starts at skb->data. Should
173 * another driver implementation need ADDITIONAL padding, the net_init.c
174 * module should be updated and dev->hard_header_len should be increased.
175 * NOTE: To maintain the alignment on the data portion of the packet,
176 * dev->hard_header_len should always be evenly divisible by 4 and at
177 * least 24 bytes in size.
178 *
179 * Modification History:
180 * Date Name Description
181 * 16-Aug-96 LVS Created.
182 * 20-Aug-96 LVS Updated dfx_probe so that version information
183 * string is only displayed if 1 or more cards are
184 * found. Changed dfx_rcv_queue_process to copy
185 * 3 NULL bytes before FC to ensure that data is
186 * longword aligned in receive buffer.
187 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable
188 * LLC group promiscuous mode if multicast list
189 * is too large. LLC individual/group promiscuous
190 * mode is now disabled if IFF_PROMISC flag not set.
191 * dfx_xmt_queue_pkt no longer checks for NULL skb
192 * on Alan Cox recommendation. Added node address
193 * override support.
194 * 12-Sep-96 LVS Reset current address to factory address during
195 * device open. Updated transmit path to post a
196 * single fragment which includes PRH->end of data.
197 */
199 /* Version information string - should be updated prior to each new release!!! */
201 static const char *version = "defxx.c:v1.04 09/16/96 Lawrence V. Stefani (stefani@lkg.dec.com)\n";
203 /* Include files */
205 #include <linux/module.h>
207 #include <linux/kernel.h>
208 #include <linux/sched.h>
209 #include <linux/string.h>
210 #include <linux/ptrace.h>
211 #include <linux/errno.h>
212 #include <linux/ioport.h>
213 #include <linux/malloc.h>
214 #include <linux/interrupt.h>
215 #include <linux/pci.h>
216 #include <linux/bios32.h>
217 #include <linux/delay.h>
218 #include <linux/init.h>
219 #include <asm/byteorder.h>
220 #include <asm/bitops.h>
221 #include <asm/io.h>
223 #include <linux/netdevice.h>
224 #include <linux/fddidevice.h>
225 #include <linux/skbuff.h>
229 /* Define global routines */
233 /* Define module-wide (static) routines */
258 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
270 /* Define module-wide (static) variables */
275 \f
276 /*
277 * =======================
278 * = dfx_port_write_byte =
279 * = dfx_port_read_byte =
280 * = dfx_port_write_long =
281 * = dfx_port_read_long =
282 * =======================
283 *
284 * Overview:
285 * Routines for reading and writing values from/to adapter
286 *
287 * Returns:
288 * None
289 *
290 * Arguments:
291 * bp - pointer to board information
292 * offset - register offset from base I/O address
293 * data - for dfx_port_write_byte and dfx_port_write_long, this
294 * is a value to write.
295 * for dfx_port_read_byte and dfx_port_read_byte, this
296 * is a pointer to store the read value.
297 *
298 * Functional Description:
299 * These routines perform the correct operation to read or write
300 * the adapter register.
301 *
302 * EISA port block base addresses are based on the slot number in which the
303 * controller is installed. For example, if the EISA controller is installed
304 * in slot 4, the port block base address is 0x4000. If the controller is
305 * installed in slot 2, the port block base address is 0x2000, and so on.
306 * This port block can be used to access PDQ, ESIC, and DEFEA on-board
307 * registers using the register offsets defined in DEFXX.H.
308 *
309 * PCI port block base addresses are assigned by the PCI BIOS or system
310 * firmware. There is one 128 byte port block which can be accessed. It
311 * allows for I/O mapping of both PDQ and PFI registers using the register
312 * offsets defined in DEFXX.H.
313 *
314 * Return Codes:
315 * None
316 *
317 * Assumptions:
318 * bp->base_addr is a valid base I/O address for this adapter.
319 * offset is a valid register offset for this adapter.
320 *
321 * Side Effects:
322 * Rather than produce macros for these functions, these routines
323 * are defined using "inline" to ensure that the compiler will
324 * generate inline code and not waste a procedure call and return.
325 * This provides all the benefits of macros, but with the
326 * advantage of strict data type checking.
327 */
332 u8 data
333 )
335 {
340 }
345 u8 *data
346 )
348 {
353 }
358 u32 data
359 )
361 {
366 }
371 u32 *data
372 )
374 {
379 }
381 \f
382 /*
383 * =============
384 * = dfx_probe =
385 * =============
386 *
387 * Overview:
388 * Probes for supported FDDI EISA and PCI controllers
389 *
390 * Returns:
391 * Condition code
392 *
393 * Arguments:
394 * dev - pointer to device information
395 *
396 * Functional Description:
397 * This routine is called by the OS for each FDDI device name (fddi0,
398 * fddi1,...,fddi6, fddi7) specified in drivers/net/Space.c. Since
399 * the DEFXX.C driver currently does not support being loaded as a
400 * module, dfx_probe() will initialize all devices the first time
401 * it is called.
402 *
403 * Let's say that dfx_probe() is getting called to initialize fddi0.
404 * Furthermore, let's say there are three supported controllers in the
405 * system. Before dfx_probe() leaves, devices fddi0, fddi1, and fddi2
406 * will be initialized and a global flag will be set to indicate that
407 * dfx_probe() has already been called.
408 *
409 * However...the OS doesn't know that we've already initialized
410 * devices fddi1 and fddi2 so dfx_probe() gets called again and again
411 * until it reaches the end of the device list for FDDI (presently,
412 * fddi7). It's important that the driver "pretend" to probe for
413 * devices fddi1 and fddi2 and return success. Devices fddi3
414 * through fddi7 will return failure since they weren't initialized.
415 *
416 * This algorithm seems to work for the time being. As other FDDI
417 * drivers are written for Linux, a more generic approach (perhaps
418 * similar to the Ethernet card approach) may need to be implemented.
419 *
420 * Return Codes:
421 * 0 - This device (fddi0, fddi1, etc) configured successfully
422 * -ENODEV - No devices present, or no Digital FDDI EISA or PCI device
423 * present for this device name
424 *
425 * Assumptions:
426 * For the time being, DEFXX.C is the only FDDI driver under Linux.
427 * As this assumption changes, this routine will likely be impacted.
428 * Also, it is assumed that no more than eight (8) FDDI controllers
429 * will be configured in the system (fddi0 through fddi7). This
430 * routine will not allocate new device structures. If more than
431 * eight FDDI controllers need to be configured, drivers/net/Space.c
432 * should be updated as well as the DFX_MAX_NUM_BOARDS constant in
433 * DEFXX.H.
434 *
435 * Side Effects:
436 * Device structures for FDDI adapters (fddi0, fddi1, etc) are
437 * initialized and the board resources are read and stored in
438 * the device structure.
439 */
443 ))
445 {
458 /*
459 * Verify whether we're going through dfx_probe() again
460 *
461 * If so, see if we're going through for a subsequent fddi device that
462 * we've already initialized. If we are, return success (0). If not,
463 * return failure (-ENODEV).
464 */
468 {
472 {
473 DBG_printk("In dfx_probe for fddi adapter (%s) we've already initialized it, so return success\n", dev->name);
475 }
477 }
480 /* Scan for FDDI EISA controllers */
483 {
487 {
489 {
492 }
496 /* Verify port address range is not already being used */
500 {
501 /* Allocate a new device structure for this adapter */
505 {
506 /* Initialize board structure with bus-specific info */
513 else
515 }
516 }
517 else
518 printk("I/O range allocated to adapter (0x%X-0x%X) is already being used!\n", port, (port + port_len-1));
519 }
520 }
522 /* Scan for FDDI PCI controllers */
526 if (pcibios_find_device(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI, i, &pci_bus, &pci_dev_fun) == 0)
527 {
529 {
532 }
534 /* Verify that I/O enable bit is set (PCI slot is enabled) */
539 else
540 {
541 /* Turn off memory mapped space and enable mastering */
547 /* Read I/O base address from PCI Configuration Space */
552 /* Verify port address range is not already being used */
556 {
557 /* Allocate a new device structure for this adapter */
561 {
562 /* Initialize board structure with bus-specific info */
571 else
573 }
574 }
575 else
576 printk("I/O range allocated to adapter (0x%X-0x%X) is already being used!\n", port, (port + port_len-1));
577 }
578 }
580 /*
581 * If we're at this point we're going through dfx_probe() for the first
582 * time. Return success (0) if we've initialized 1 or more boards.
583 * Otherwise, return failure (-ENODEV).
584 */
588 else
590 }
592 \f
593 /*
594 * ====================
595 * = dfx_alloc_device =
596 * ====================
597 *
598 * Overview:
599 * Allocate new device structure for adapter
600 *
601 * Returns:
602 * Pointer to device structure for this adapter or NULL if
603 * none are available or could not allocate memory for
604 * private board structure.
605 *
606 * Arguments:
607 * dev - pointer to device information for last device
608 * iobase - base I/O address of new adapter
609 *
610 * Functional Description:
611 * The algorithm for allocating a new device structure is
612 * fairly simple. Since we're presently the only FDDI driver
613 * under Linux, we'll find the first device structure with an
614 * "fddi*" device name that's free. If we run out of devices,
615 * we'll fail on error. This is simpler than trying to
616 * allocate the memory for a new device structure, determine
617 * the next free number (beyond 7) and link it into the chain
618 * of devices. A user can always modify drivers/net/Space.c
619 * to add new FDDI device structures if necessary.
620 *
621 * Beyond finding a free FDDI device structure, this routine
622 * initializes most of the fields, resource tags, and dispatch
623 * pointers in the device structure and calls the common
624 * fddi_setup() routine to perform the rest of the device
625 * structure initialization.
626 *
627 * Return Codes:
628 * None
629 *
630 * Assumptions:
631 * If additional FDDI drivers are integrated into Linux,
632 * we'll likely need to use a different approach to
633 * allocate a device structure. Perhaps one that is
634 * similar to what the Ethernet drivers use.
635 *
636 * Side Effects:
637 * None
638 */
642 u16 iobase
643 ))
645 {
650 /* Find next free fddi entry */
656 {
659 }
662 /* Allocate space for private board structure */
666 {
669 }
672 /* Initialize new device structure */
697 /* Initialize remaining device structure information */
701 }
703 \f
704 /*
705 * ================
706 * = dfx_bus_init =
707 * ================
708 *
709 * Overview:
710 * Initializes EISA and PCI controller bus-specific logic.
711 *
712 * Returns:
713 * None
714 *
715 * Arguments:
716 * dev - pointer to device information
717 *
718 * Functional Description:
719 * Determine and save adapter IRQ in device table,
720 * then perform bus-specific logic initialization.
721 *
722 * Return Codes:
723 * None
724 *
725 * Assumptions:
726 * dev->base_addr has already been set with the proper
727 * base I/O address for this device.
728 *
729 * Side Effects:
730 * Interrupts are enabled at the adapter bus-specific logic.
731 * Note: Interrupts at the DMA engine (PDQ chip) are not
732 * enabled yet.
733 */
737 ))
739 {
745 /*
746 * Initialize base I/O address field in bp structure
747 *
748 * Note: bp->base_addr is the same as dev->base_addr.
749 * It's useful because often we'll need to read
750 * or write registers where we already have the
751 * bp pointer instead of the dev pointer. Having
752 * the base address in the bp structure will
753 * save a pointer dereference.
754 *
755 * IMPORTANT!! This field must be defined before
756 * any of the dfx_port_* inline functions are
757 * called.
758 */
762 /* Initialize adapter based on bus type */
765 {
766 /* Get the interrupt level from the ESIC chip */
770 {
786 }
788 /* Enable access to I/O on the board by writing 0x03 to Function Control Register */
792 /* Set the I/O decode range of the board */
798 /* Enable access to rest of module (including PDQ and packet memory) */
802 /*
803 * Map PDQ registers into I/O space. This is done by clearing a bit
804 * in Burst Holdoff register.
805 */
810 /* Enable interrupts at EISA bus interface chip (ESIC) */
814 }
815 else
816 {
817 /* Get the interrupt level from the PCI Configuration Table */
822 /* Check Latency Timer and set if less than minimal */
826 {
829 }
831 /* Enable interrupts at PCI bus interface chip (PFI) */
834 }
836 }
838 \f
839 /*
840 * ========================
841 * = dfx_bus_config_check =
842 * ========================
843 *
844 * Overview:
845 * Checks the configuration (burst size, full-duplex, etc.) If any parameters
846 * are illegal, then this routine will set new defaults.
847 *
848 * Returns:
849 * None
850 *
851 * Arguments:
852 * bp - pointer to board information
853 *
854 * Functional Description:
855 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
856 * PDQ, and all FDDI PCI controllers, all values are legal.
857 *
858 * Return Codes:
859 * None
860 *
861 * Assumptions:
862 * dfx_adap_init has NOT been called yet so burst size and other items have
863 * not been set.
864 *
865 * Side Effects:
866 * None
867 */
870 DFX_board_t *bp
871 ))
873 {
880 /* Configuration check only valid for EISA adapter */
883 {
886 /*
887 * First check if revision 2 EISA controller. Rev. 1 cards used
888 * PDQ revision B, so no workaround needed in this case. Rev. 3
889 * cards used PDQ revision E, so no workaround needed in this
890 * case, either. Only Rev. 2 cards used either Rev. D or E
891 * chips, so we must verify the chip revision on Rev. 2 cards.
892 */
895 {
896 /*
897 * Revision 2 FDDI EISA controller found, so let's check PDQ
898 * revision of adapter.
899 */
902 PI_PCTRL_M_SUB_CMD,
903 PI_SUB_CMD_K_PDQ_REV_GET,
907 {
908 /*
909 * Either we couldn't determine the PDQ revision, or
910 * we determined that it is at revision D. In either case,
911 * we need to implement the workaround.
912 */
914 /* Ensure that the burst size is set to 8 longwords or less */
917 {
925 }
927 /* Ensure that full-duplex mode is not enabled */
930 }
931 }
932 }
934 }
936 \f
937 /*
938 * ===================
939 * = dfx_driver_init =
940 * ===================
941 *
942 * Overview:
943 * Initializes remaining adapter board structure information
944 * and makes sure adapter is in a safe state prior to dfx_open().
945 *
946 * Returns:
947 * Condition code
948 *
949 * Arguments:
950 * dev - pointer to device information
951 *
952 * Functional Description:
953 * This function allocates additional resources such as the host memory
954 * blocks needed by the adapter (eg. descriptor and consumer blocks).
955 * Remaining bus initialization steps are also completed. The adapter
956 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS
957 * must call dfx_open() to open the adapter and bring it on-line.
958 *
959 * Return Codes:
960 * DFX_K_SUCCESS - initialization succeeded
961 * DFX_K_FAILURE - initialization failed - could not allocate memory
962 * or read adapter MAC address
963 *
964 * Assumptions:
965 * Memory allocated from kmalloc() call is physically contiguous, locked
966 * memory whose physical address equals its virtual address.
967 *
968 * Side Effects:
969 * Adapter is reset and should be in DMA_UNAVAILABLE state before
970 * returning from this routine.
971 */
975 ))
977 {
986 /* Initialize bus-specific hardware registers */
990 /*
991 * Initialize default values for configurable parameters
992 *
993 * Note: All of these parameters are ones that a user may
994 * want to customize. It'd be nice to break these
995 * out into Space.c or someplace else that's more
996 * accessible/understandable than this file.
997 */
1004 /*
1005 * Ensure that HW configuration is OK
1006 *
1007 * Note: Depending on the hardware revision, we may need to modify
1008 * some of the configurable parameters to workaround hardware
1009 * limitations. We'll perform this configuration check AFTER
1010 * setting the parameters to their default values.
1011 */
1015 /* Disable PDQ interrupts first */
1019 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1023 /* Read the factory MAC address from the adapter then save it */
1026 PI_PCTRL_M_MLA,
1027 PI_PDATA_A_MLA_K_LO,
1030 {
1033 }
1037 PI_PCTRL_M_MLA,
1038 PI_PDATA_A_MLA_K_HI,
1041 {
1044 }
1047 /*
1048 * Set current address to factory address
1049 *
1050 * Note: Node address override support is handled through
1051 * dfx_ctl_set_mac_address.
1052 */
1056 printk("%s: DEFEA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
1066 else
1067 printk("%s: DEFPA at I/O addr = 0x%lX, IRQ = %d, Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
1078 /*
1079 * Get memory for descriptor block, consumer block, and other buffers
1080 * that need to be DMA read or written to by the adapter.
1081 */
1084 PI_CMD_REQ_K_SIZE_MAX +
1085 PI_CMD_RSP_K_SIZE_MAX +
1091 {
1094 }
1098 /*
1099 * To guarantee the 8K alignment required for the descriptor block, 8K - 1
1100 * plus the amount of memory needed was allocated. The physical address
1101 * is now 8K aligned. By carving up the memory in a specific order,
1102 * we'll guarantee the alignment requirements for all other structures.
1103 *
1104 * Note: If the assumptions change regarding the non-paged, non-cached,
1105 * physically contiguous nature of the memory block or the address
1106 * alignments, then we'll need to implement a different algorithm
1107 * for allocating the needed memory.
1108 */
1113 /* Reserve space for descriptor block */
1120 /* Reserve space for command request buffer */
1127 /* Reserve space for command response buffer */
1134 /* Reserve space for the LLC host receive queue buffers */
1141 /* Reserve space for the consumer block */
1146 /* Display virtual and physical addresses if debug driver */
1148 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", dev->name, (long)bp->descr_block_virt, bp->descr_block_phys);
1149 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", dev->name, (long)bp->cmd_req_virt, bp->cmd_req_phys);
1150 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", dev->name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys);
1151 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", dev->name, (long)bp->rcv_block_virt, bp->rcv_block_phys);
1152 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", dev->name, (long)bp->cons_block_virt, bp->cons_block_phys);
1155 }
1157 \f
1158 /*
1159 * =================
1160 * = dfx_adap_init =
1161 * =================
1162 *
1163 * Overview:
1164 * Brings the adapter to the link avail/link unavailable state.
1165 *
1166 * Returns:
1167 * Condition code
1168 *
1169 * Arguments:
1170 * bp - pointer to board information
1171 *
1172 * Functional Description:
1173 * Issues the low-level firmware/hardware calls necessary to bring
1174 * the adapter up, or to properly reset and restore adapter during
1175 * run-time.
1176 *
1177 * Return Codes:
1178 * DFX_K_SUCCESS - Adapter brought up successfully
1179 * DFX_K_FAILURE - Adapter initialization failed
1180 *
1181 * Assumptions:
1182 * bp->reset_type should be set to a valid reset type value before
1183 * calling this routine.
1184 *
1185 * Side Effects:
1186 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1187 * upon a successful return of this routine.
1188 */
1191 DFX_board_t *bp
1192 )
1194 {
1197 /* Disable PDQ interrupts first */
1201 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1204 {
1207 }
1209 /*
1210 * When the PDQ is reset, some false Type 0 interrupts may be pending,
1211 * so we'll acknowledge all Type 0 interrupts now before continuing.
1212 */
1216 /*
1217 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
1218 *
1219 * Note: We only need to clear host copies of these registers. The PDQ reset
1220 * takes care of the on-board register values.
1221 */
1227 /* Clear consumer block before going to DMA_AVAILABLE state */
1231 /* Initialize the DMA Burst Size */
1234 PI_PCTRL_M_SUB_CMD,
1235 PI_SUB_CMD_K_BURST_SIZE_SET,
1238 {
1241 }
1243 /*
1244 * Set base address of Consumer Block
1245 *
1246 * Assumption: 32-bit physical address of consumer block is 64 byte
1247 * aligned. That is, bits 0-5 of the address must be zero.
1248 */
1251 PI_PCTRL_M_CONS_BLOCK,
1255 {
1258 }
1260 /*
1261 * Set base address of Descriptor Block and bring adapter to DMA_AVAILABLE state
1262 *
1263 * Note: We also set the literal and data swapping requirements in this
1264 * command. Since this driver presently runs on Intel platforms
1265 * which are Little Endian, we'll tell the adapter to byte swap
1266 * data only. This code will need to change when we support
1267 * Big Endian systems (eg. PowerPC).
1268 *
1269 * Assumption: 32-bit physical address of descriptor block is 8Kbyte
1270 * aligned. That is, bits 0-12 of the address must be zero.
1271 */
1274 PI_PCTRL_M_INIT,
1278 {
1281 }
1283 /* Set transmit flush timeout value */
1291 {
1294 }
1296 /* Set the initial values for eFDXEnable and MACTReq MIB objects */
1307 {
1310 }
1312 /* Initialize adapter CAM */
1315 {
1318 }
1320 /* Initialize adapter filters */
1323 {
1326 }
1328 /* Initialize receive descriptor block and produce buffers */
1332 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
1336 {
1339 }
1341 /* Initialization succeeded, reenable PDQ interrupts */
1345 }
1347 \f
1348 /*
1349 * ============
1350 * = dfx_open =
1351 * ============
1352 *
1353 * Overview:
1354 * Opens the adapter
1355 *
1356 * Returns:
1357 * Condition code
1358 *
1359 * Arguments:
1360 * dev - pointer to device information
1361 *
1362 * Functional Description:
1363 * This function brings the adapter to an operational state.
1364 *
1365 * Return Codes:
1366 * 0 - Adapter was successfully opened
1367 * -EAGAIN - Could not register IRQ or adapter initialization failed
1368 *
1369 * Assumptions:
1370 * This routine should only be called for a device that was
1371 * initialized successfully during the dfx_probe process.
1372 *
1373 * Side Effects:
1374 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1375 * if the open is successful.
1376 */
1380 )
1382 {
1387 /* Register IRQ - support shared interrupts by passing device ptr */
1390 {
1393 }
1395 /*
1396 * Set current address to factory MAC address
1397 *
1398 * Note: We've already done this step in dfx_driver_init.
1399 * However, it's possible that a user has set a node
1400 * address override, then closed and reopened the
1401 * adapter. Unless we reset the device address field
1402 * now, we'll continue to use the existing modified
1403 * address.
1404 */
1408 /* Clear local unicast/multicast address tables and counts */
1415 /* Disable promiscuous filter settings */
1420 /* Reset and initialize adapter */
1424 {
1427 }
1429 /* Set device structure info */
1435 }
1437 \f
1438 /*
1439 * =============
1440 * = dfx_close =
1441 * =============
1442 *
1443 * Overview:
1444 * Closes the device/module.
1445 *
1446 * Returns:
1447 * Condition code
1448 *
1449 * Arguments:
1450 * dev - pointer to device information
1451 *
1452 * Functional Description:
1453 * This routine closes the adapter and brings it to a safe state.
1454 * The interrupt service routine is deregistered with the OS.
1455 * The adapter can be opened again with another call to dfx_open().
1456 *
1457 * Return Codes:
1458 * Always return 0.
1459 *
1460 * Assumptions:
1461 * No further requests for this adapter are made after this routine is
1462 * called. dfx_open() can be called to reset and reinitialize the
1463 * adapter.
1464 *
1465 * Side Effects:
1466 * Adapter should be in DMA_UNAVAILABLE state upon completion of this
1467 * routine.
1468 */
1472 )
1474 {
1479 /* Disable PDQ interrupts first */
1483 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1487 /*
1488 * Flush any pending transmit buffers
1489 *
1490 * Note: It's important that we flush the transmit buffers
1491 * BEFORE we clear our copy of the Type 2 register.
1492 * Otherwise, we'll have no idea how many buffers
1493 * we need to free.
1494 */
1498 /*
1499 * Clear Type 1 and Type 2 registers after adapter reset
1500 *
1501 * Note: Even though we're closing the adapter, it's
1502 * possible that an interrupt will occur after
1503 * dfx_close is called. Without some assurance to
1504 * the contrary we want to make sure that we don't
1505 * process receive and transmit LLC frames and update
1506 * the Type 2 register with bad information.
1507 */
1513 /* Clear consumer block for the same reason given above */
1517 /* Clear device structure flags */
1522 /* Deregister (free) IRQ */
1526 }
1528 \f
1529 /*
1530 * ======================
1531 * = dfx_int_pr_halt_id =
1532 * ======================
1533 *
1534 * Overview:
1535 * Displays halt id's in string form.
1536 *
1537 * Returns:
1538 * None
1539 *
1540 * Arguments:
1541 * bp - pointer to board information
1542 *
1543 * Functional Description:
1544 * Determine current halt id and display appropriate string.
1545 *
1546 * Return Codes:
1547 * None
1548 *
1549 * Assumptions:
1550 * None
1551 *
1552 * Side Effects:
1553 * None
1554 */
1557 DFX_board_t *bp
1558 )
1560 {
1564 /* Read the latest port status */
1568 /* Display halt state transition information */
1572 {
1612 }
1614 }
1616 \f
1617 /*
1618 * ==========================
1619 * = dfx_int_type_0_process =
1620 * ==========================
1621 *
1622 * Overview:
1623 * Processes Type 0 interrupts.
1624 *
1625 * Returns:
1626 * None
1627 *
1628 * Arguments:
1629 * bp - pointer to board information
1630 *
1631 * Functional Description:
1632 * Processes all enabled Type 0 interrupts. If the reason for the interrupt
1633 * is a serious fault on the adapter, then an error message is displayed
1634 * and the adapter is reset.
1635 *
1636 * One tricky potential timing window is the rapid succession of "link avail"
1637 * "link unavail" state change interrupts. The acknowledgement of the Type 0
1638 * interrupt must be done before reading the state from the Port Status
1639 * register. This is true because a state change could occur after reading
1640 * the data, but before acknowledging the interrupt. If this state change
1641 * does happen, it would be lost because the driver is using the old state,
1642 * and it will never know about the new state because it subsequently
1643 * acknowledges the state change interrupt.
1644 *
1645 * INCORRECT CORRECT
1646 * read type 0 int reasons read type 0 int reasons
1647 * read adapter state ack type 0 interrupts
1648 * ack type 0 interrupts read adapter state
1649 * ... process interrupt ... ... process interrupt ...
1650 *
1651 * Return Codes:
1652 * None
1653 *
1654 * Assumptions:
1655 * None
1656 *
1657 * Side Effects:
1658 * An adapter reset may occur if the adapter has any Type 0 error interrupts
1659 * or if the port status indicates that the adapter is halted. The driver
1660 * is responsible for reinitializing the adapter with the current CAM
1661 * contents and adapter filter settings.
1662 */
1665 DFX_board_t *bp
1666 )
1668 {
1672 /*
1673 * Read host interrupt Type 0 register to determine which Type 0
1674 * interrupts are pending. Immediately write it back out to clear
1675 * those interrupts.
1676 */
1681 /* Check for Type 0 error interrupts */
1684 PI_TYPE_0_STAT_M_PM_PAR_ERR |
1685 PI_TYPE_0_STAT_M_BUS_PAR_ERR))
1686 {
1687 /* Check for Non-Existent Memory error */
1692 /* Check for Packet Memory Parity error */
1697 /* Check for Host Bus Parity error */
1702 /* Reset adapter and bring it back on-line */
1708 {
1712 }
1715 }
1717 /* Check for transmit flush interrupt */
1720 {
1721 /* Flush any pending xmt's and acknowledge the flush interrupt */
1726 PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
1729 NULL);
1730 }
1732 /* Check for adapter state change */
1735 {
1736 /* Get latest adapter state */
1740 {
1741 /*
1742 * Adapter has transitioned to HALTED state, try to reset
1743 * adapter to bring it back on-line. If reset fails,
1744 * leave the adapter in the broken state.
1745 */
1750 /* Reset adapter and bring it back on-line */
1756 {
1760 }
1762 }
1764 {
1766 }
1767 }
1769 }
1771 \f
1772 /*
1773 * ==================
1774 * = dfx_int_common =
1775 * ==================
1776 *
1777 * Overview:
1778 * Interrupt service routine (ISR)
1779 *
1780 * Returns:
1781 * None
1782 *
1783 * Arguments:
1784 * bp - pointer to board information
1785 *
1786 * Functional Description:
1787 * This is the ISR which processes incoming adapter interrupts.
1788 *
1789 * Return Codes:
1790 * None
1791 *
1792 * Assumptions:
1793 * This routine assumes PDQ interrupts have not been disabled.
1794 * When interrupts are disabled at the PDQ, the Port Status register
1795 * is automatically cleared. This routine uses the Port Status
1796 * register value to determine whether a Type 0 interrupt occurred,
1797 * so it's important that adapter interrupts are not normally
1798 * enabled/disabled at the PDQ.
1799 *
1800 * It's vital that this routine is NOT reentered for the
1801 * same board and that the OS is not in another section of
1802 * code (eg. dfx_xmt_queue_pkt) for the same board on a
1803 * different thread.
1804 *
1805 * Side Effects:
1806 * Pending interrupts are serviced. Depending on the type of
1807 * interrupt, acknowledging and clearing the interrupt at the
1808 * PDQ involves writing a register to clear the interrupt bit
1809 * or updating completion indices.
1810 */
1813 DFX_board_t *bp
1814 )
1816 {
1819 /* Process xmt interrupts - frequent case, so always call this routine */
1823 /* Process rcv interrupts - frequent case, so always call this routine */
1827 /*
1828 * Transmit and receive producer and completion indices are updated on the
1829 * adapter by writing to the Type 2 Producer register. Since the frequent
1830 * case is that we'll be processing either LLC transmit or receive buffers,
1831 * we'll optimize I/O writes by doing a single register write here.
1832 */
1836 /* Read PDQ Port Status register to find out which interrupts need processing */
1840 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
1845 }
1847 \f
1848 /*
1849 * =================
1850 * = dfx_interrupt =
1851 * =================
1852 *
1853 * Overview:
1854 * Interrupt processing routine
1855 *
1856 * Returns:
1857 * None
1858 *
1859 * Arguments:
1860 * irq - interrupt vector
1861 * dev_id - pointer to device information
1862 * regs - pointer to registers structure
1863 *
1864 * Functional Description:
1865 * This routine calls the interrupt processing routine for this adapter. It
1866 * disables and reenables adapter interrupts, as appropriate. We can support
1867 * shared interrupts since the incoming dev_id pointer provides our device
1868 * structure context.
1869 *
1870 * Return Codes:
1871 * None
1872 *
1873 * Assumptions:
1874 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
1875 * on Intel-based systems) is done by the operating system outside this
1876 * routine.
1877 *
1878 * System interrupts are enabled through this call.
1879 *
1880 * Side Effects:
1881 * Interrupts are disabled, then reenabled at the adapter.
1882 */
1888 )
1890 {
1895 /* Get board pointer only if device structure is valid */
1898 {
1901 }
1904 /* See if we're already servicing an interrupt */
1910 /* Service adapter interrupts */
1913 {
1914 /* Disable PDQ-PFI interrupts at PFI */
1918 /* Call interrupt service routine for this adapter */
1922 /* Clear PDQ interrupt status bit and reenable interrupts */
1927 }
1928 else
1929 {
1930 /* Disable interrupts at the ESIC */
1936 /* Call interrupt service routine for this adapter */
1940 /* Reenable interrupts at the ESIC */
1945 }
1949 }
1951 \f
1952 /*
1953 * =====================
1954 * = dfx_ctl_get_stats =
1955 * =====================
1956 *
1957 * Overview:
1958 * Get statistics for FDDI adapter
1959 *
1960 * Returns:
1961 * Pointer to FDDI statistics structure
1962 *
1963 * Arguments:
1964 * dev - pointer to device information
1965 *
1966 * Functional Description:
1967 * Gets current MIB objects from adapter, then
1968 * returns FDDI statistics structure as defined
1969 * in if_fddi.h.
1970 *
1971 * Note: Since the FDDI statistics structure is
1972 * still new and the device structure doesn't
1973 * have an FDDI-specific get statistics handler,
1974 * we'll return the FDDI statistics structure as
1975 * a pointer to an Ethernet statistics structure.
1976 * That way, at least the first part of the statistics
1977 * structure can be decoded properly, and it allows
1978 * "smart" applications to perform a second cast to
1979 * decode the FDDI-specific statistics.
1980 *
1981 * We'll have to pay attention to this routine as the
1982 * device structure becomes more mature and LAN media
1983 * independent.
1984 *
1985 * Return Codes:
1986 * None
1987 *
1988 * Assumptions:
1989 * None
1990 *
1991 * Side Effects:
1992 * None
1993 */
1997 )
1999 {
2002 /* Fill the bp->stats structure with driver-maintained counters */
2006 bp->stats.rx_errors = (u32)(bp->rcv_crc_errors + bp->rcv_frame_status_errors + bp->rcv_length_errors);
2013 /* Get FDDI SMT MIB objects */
2019 /* Fill the bp->stats structure with the SMT MIB object values */
2021 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
2025 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
2040 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
2044 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
2045 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
2050 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
2051 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
2052 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
2053 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
2057 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
2074 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
2079 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
2080 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
2085 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
2086 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
2093 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
2094 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
2114 /* Get FDDI counters */
2120 /* Fill the bp->stats structure with the FDDI counter values */
2135 }
2137 \f
2138 /*
2139 * ==============================
2140 * = dfx_ctl_set_multicast_list =
2141 * ==============================
2142 *
2143 * Overview:
2144 * Enable/Disable LLC frame promiscuous mode reception
2145 * on the adapter and/or update multicast address table.
2146 *
2147 * Returns:
2148 * None
2149 *
2150 * Arguments:
2151 * dev - pointer to device information
2152 *
2153 * Functional Description:
2154 * This routine follows a fairly simple algorithm for setting the
2155 * adapter filters and CAM:
2156 *
2157 * if IFF_PROMISC flag is set
2158 * enable LLC individual/group promiscuous mode
2159 * else
2160 * disable LLC individual/group promiscuous mode
2161 * if number of incoming multicast addresses >
2162 * (CAM max size - number of unicast addresses in CAM)
2163 * enable LLC group promiscuous mode
2164 * set driver-maintained multicast address count to zero
2165 * else
2166 * disable LLC group promiscuous mode
2167 * set driver-maintained multicast address count to incoming count
2168 * update adapter CAM
2169 * update adapter filters
2170 *
2171 * Return Codes:
2172 * None
2173 *
2174 * Assumptions:
2175 * Multicast addresses are presented in canonical (LSB) format.
2176 *
2177 * Side Effects:
2178 * On-board adapter CAM and filters are updated.
2179 */
2183 )
2185 {
2190 /* Enable LLC frame promiscuous mode, if necessary */
2195 /* Else, update multicast address table */
2197 else
2198 {
2200 /*
2201 * Check whether incoming multicast address count exceeds table size
2202 *
2203 * Note: The adapters utilize an on-board 64 entry CAM for
2204 * supporting perfect filtering of multicast packets
2205 * and bridge functions when adding unicast addresses.
2206 * There is no hash function available. To support
2207 * additional multicast addresses, the all multicast
2208 * filter (LLC group promiscuous mode) must be enabled.
2209 *
2210 * The firmware reserves two CAM entries for SMT-related
2211 * multicast addresses, which leaves 62 entries available.
2212 * The following code ensures that we're not being asked
2213 * to add more than 62 addresses to the CAM. If we are,
2214 * the driver will enable the all multicast filter.
2215 * Should the number of multicast addresses drop below
2216 * the high water mark, the filter will be disabled and
2217 * perfect filtering will be used.
2218 */
2221 {
2224 }
2225 else
2226 {
2229 }
2231 /* Copy addresses to multicast address table, then update adapter CAM */
2235 {
2238 }
2240 {
2242 }
2243 else
2244 {
2245 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count);
2246 }
2247 }
2249 /* Update adapter filters */
2252 {
2254 }
2255 else
2256 {
2258 }
2260 }
2262 \f
2263 /*
2264 * ===========================
2265 * = dfx_ctl_set_mac_address =
2266 * ===========================
2267 *
2268 * Overview:
2269 * Add node address override (unicast address) to adapter
2270 * CAM and update dev_addr field in device table.
2271 *
2272 * Returns:
2273 * None
2274 *
2275 * Arguments:
2276 * dev - pointer to device information
2277 * addr - pointer to sockaddr structure containing unicast address to add
2278 *
2279 * Functional Description:
2280 * The adapter supports node address overrides by adding one or more
2281 * unicast addresses to the adapter CAM. This is similar to adding
2282 * multicast addresses. In this routine we'll update the driver and
2283 * device structures with the new address, then update the adapter CAM
2284 * to ensure that the adapter will copy and strip frames destined and
2285 * sourced by that address.
2286 *
2287 * Return Codes:
2288 * Always returns zero.
2289 *
2290 * Assumptions:
2291 * The address pointed to by addr->sa_data is a valid unicast
2292 * address and is presented in canonical (LSB) format.
2293 *
2294 * Side Effects:
2295 * On-board adapter CAM is updated. On-board adapter filters
2296 * may be updated.
2297 */
2302 )
2304 {
2308 /* Copy unicast address to driver-maintained structs and update count */
2314 /*
2315 * Verify we're not exceeding the CAM size by adding unicast address
2316 *
2317 * Note: It's possible that before entering this routine we've
2318 * already filled the CAM with 62 multicast addresses.
2319 * Since we need to place the node address override into
2320 * the CAM, we have to check to see that we're not
2321 * exceeding the CAM size. If we are, we have to enable
2322 * the LLC group (multicast) promiscuous mode filter as
2323 * in dfx_ctl_set_multicast_list.
2324 */
2327 {
2331 /* Update adapter filters */
2334 {
2336 }
2337 else
2338 {
2340 }
2341 }
2343 /* Update adapter CAM with new unicast address */
2346 {
2348 }
2349 else
2350 {
2352 }
2354 }
2356 \f
2357 /*
2358 * ======================
2359 * = dfx_ctl_update_cam =
2360 * ======================
2361 *
2362 * Overview:
2363 * Procedure to update adapter CAM (Content Addressable Memory)
2364 * with desired unicast and multicast address entries.
2365 *
2366 * Returns:
2367 * Condition code
2368 *
2369 * Arguments:
2370 * bp - pointer to board information
2371 *
2372 * Functional Description:
2373 * Updates adapter CAM with current contents of board structure
2374 * unicast and multicast address tables. Since there are only 62
2375 * free entries in CAM, this routine ensures that the command
2376 * request buffer is not overrun.
2377 *
2378 * Return Codes:
2379 * DFX_K_SUCCESS - Request succeeded
2380 * DFX_K_FAILURE - Request failed
2381 *
2382 * Assumptions:
2383 * All addresses being added (unicast and multicast) are in canonical
2384 * order.
2385 *
2386 * Side Effects:
2387 * On-board adapter CAM is updated.
2388 */
2391 DFX_board_t *bp
2392 )
2394 {
2398 /*
2399 * Fill in command request information
2400 *
2401 * Note: Even though both the unicast and multicast address
2402 * table entries are stored as contiguous 6 byte entries,
2403 * the firmware address filter set command expects each
2404 * entry to be two longwords (8 bytes total). We must be
2405 * careful to only copy the six bytes of each unicast and
2406 * multicast table entry into each command entry. This
2407 * is also why we must first clear the entire command
2408 * request buffer.
2409 */
2415 /* Now add unicast addresses to command request buffer, if any */
2418 {
2420 {
2423 }
2424 }
2426 /* Now add multicast addresses to command request buffer, if any */
2429 {
2431 {
2434 }
2435 }
2437 /* Issue command to update adapter CAM, then return */
2442 }
2444 \f
2445 /*
2446 * ==========================
2447 * = dfx_ctl_update_filters =
2448 * ==========================
2449 *
2450 * Overview:
2451 * Procedure to update adapter filters with desired
2452 * filter settings.
2453 *
2454 * Returns:
2455 * Condition code
2456 *
2457 * Arguments:
2458 * bp - pointer to board information
2459 *
2460 * Functional Description:
2461 * Enables or disables filter using current filter settings.
2462 *
2463 * Return Codes:
2464 * DFX_K_SUCCESS - Request succeeded.
2465 * DFX_K_FAILURE - Request failed.
2466 *
2467 * Assumptions:
2468 * We must always pass up packets destined to the broadcast
2469 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the
2470 * broadcast filter enabled.
2471 *
2472 * Side Effects:
2473 * On-board adapter filters are updated.
2474 */
2477 DFX_board_t *bp
2478 )
2480 {
2483 /* Fill in command request information */
2487 /* Initialize Broadcast filter - * ALWAYS ENABLED * */
2492 /* Initialize LLC Individual/Group Promiscuous filter */
2497 /* Initialize LLC Group Promiscuous filter */
2502 /* Terminate the item code list */
2506 /* Issue command to update adapter filters, then return */
2511 }
2513 \f
2514 /*
2515 * ======================
2516 * = dfx_hw_dma_cmd_req =
2517 * ======================
2518 *
2519 * Overview:
2520 * Sends PDQ DMA command to adapter firmware
2521 *
2522 * Returns:
2523 * Condition code
2524 *
2525 * Arguments:
2526 * bp - pointer to board information
2527 *
2528 * Functional Description:
2529 * The command request and response buffers are posted to the adapter in the manner
2530 * described in the PDQ Port Specification:
2531 *
2532 * 1. Command Response Buffer is posted to adapter.
2533 * 2. Command Request Buffer is posted to adapter.
2534 * 3. Command Request consumer index is polled until it indicates that request
2535 * buffer has been DMA'd to adapter.
2536 * 4. Command Response consumer index is polled until it indicates that response
2537 * buffer has been DMA'd from adapter.
2538 *
2539 * This ordering ensures that a response buffer is already available for the firmware
2540 * to use once it's done processing the request buffer.
2541 *
2542 * Return Codes:
2543 * DFX_K_SUCCESS - DMA command succeeded
2544 * DFX_K_OUTSTATE - Adapter is NOT in proper state
2545 * DFX_K_HW_TIMEOUT - DMA command timed out
2546 *
2547 * Assumptions:
2548 * Command request buffer has already been filled with desired DMA command.
2549 *
2550 * Side Effects:
2551 * None
2552 */
2555 DFX_board_t *bp
2556 )
2558 {
2562 /* Make sure the adapter is in a state that we can issue the DMA command in */
2571 /* Put response buffer on the command response queue */
2577 /* Bump (and wrap) the producer index and write out to register */
2583 /* Put request buffer on the command request queue */
2589 /* Bump (and wrap) the producer index and write out to register */
2595 /*
2596 * Here we wait for the command request consumer index to be equal
2597 * to the producer, indicating that the adapter has DMAed the request.
2598 */
2601 {
2605 }
2609 /* Bump (and wrap) the completion index and write out to register */
2615 /*
2616 * Here we wait for the command response consumer index to be equal
2617 * to the producer, indicating that the adapter has DMAed the response.
2618 */
2621 {
2625 }
2629 /* Bump (and wrap) the completion index and write out to register */
2635 }
2637 \f
2638 /*
2639 * ========================
2640 * = dfx_hw_port_ctrl_req =
2641 * ========================
2642 *
2643 * Overview:
2644 * Sends PDQ port control command to adapter firmware
2645 *
2646 * Returns:
2647 * Host data register value in host_data if ptr is not NULL
2648 *
2649 * Arguments:
2650 * bp - pointer to board information
2651 * command - port control command
2652 * data_a - port data A register value
2653 * data_b - port data B register value
2654 * host_data - ptr to host data register value
2655 *
2656 * Functional Description:
2657 * Send generic port control command to adapter by writing
2658 * to various PDQ port registers, then polling for completion.
2659 *
2660 * Return Codes:
2661 * DFX_K_SUCCESS - port control command succeeded
2662 * DFX_K_HW_TIMEOUT - port control command timed out
2663 *
2664 * Assumptions:
2665 * None
2666 *
2667 * Side Effects:
2668 * None
2669 */
2673 PI_UINT32 command,
2674 PI_UINT32 data_a,
2675 PI_UINT32 data_b,
2676 PI_UINT32 *host_data
2677 )
2679 {
2683 /* Set Command Error bit in command longword */
2687 /* Issue port command to the adapter */
2693 /* Now wait for command to complete */
2697 else
2701 {
2706 }
2710 /*
2711 * If the address of host_data is non-zero, assume caller has supplied a
2712 * non NULL pointer, and return the contents of the HOST_DATA register in
2713 * it.
2714 */
2719 }
2721 \f
2722 /*
2723 * =====================
2724 * = dfx_hw_adap_reset =
2725 * =====================
2726 *
2727 * Overview:
2728 * Resets adapter
2729 *
2730 * Returns:
2731 * None
2732 *
2733 * Arguments:
2734 * bp - pointer to board information
2735 * type - type of reset to perform
2736 *
2737 * Functional Description:
2738 * Issue soft reset to adapter by writing to PDQ Port Reset
2739 * register. Use incoming reset type to tell adapter what
2740 * kind of reset operation to perform.
2741 *
2742 * Return Codes:
2743 * None
2744 *
2745 * Assumptions:
2746 * This routine merely issues a soft reset to the adapter.
2747 * It is expected that after this routine returns, the caller
2748 * will appropriately poll the Port Status register for the
2749 * adapter to enter the proper state.
2750 *
2751 * Side Effects:
2752 * Internal adapter registers are cleared.
2753 */
2757 PI_UINT32 type
2758 )
2760 {
2761 /* Set Reset type and assert reset */
2766 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
2770 /* Deassert reset */
2774 }
2776 \f
2777 /*
2778 * ========================
2779 * = dfx_hw_adap_state_rd =
2780 * ========================
2781 *
2782 * Overview:
2783 * Returns current adapter state
2784 *
2785 * Returns:
2786 * Adapter state per PDQ Port Specification
2787 *
2788 * Arguments:
2789 * bp - pointer to board information
2790 *
2791 * Functional Description:
2792 * Reads PDQ Port Status register and returns adapter state.
2793 *
2794 * Return Codes:
2795 * None
2796 *
2797 * Assumptions:
2798 * None
2799 *
2800 * Side Effects:
2801 * None
2802 */
2805 DFX_board_t *bp
2806 )
2808 {
2813 }
2815 \f
2816 /*
2817 * =====================
2818 * = dfx_hw_dma_uninit =
2819 * =====================
2820 *
2821 * Overview:
2822 * Brings adapter to DMA_UNAVAILABLE state
2823 *
2824 * Returns:
2825 * Condition code
2826 *
2827 * Arguments:
2828 * bp - pointer to board information
2829 * type - type of reset to perform
2830 *
2831 * Functional Description:
2832 * Bring adapter to DMA_UNAVAILABLE state by performing the following:
2833 * 1. Set reset type bit in Port Data A Register then reset adapter.
2834 * 2. Check that adapter is in DMA_UNAVAILABLE state.
2835 *
2836 * Return Codes:
2837 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state
2838 * DFX_K_HW_TIMEOUT - adapter did not reset properly
2839 *
2840 * Assumptions:
2841 * None
2842 *
2843 * Side Effects:
2844 * Internal adapter registers are cleared.
2845 */
2849 PI_UINT32 type
2850 )
2852 {
2855 /* Set reset type bit and reset adapter */
2859 /* Now wait for adapter to enter DMA_UNAVAILABLE state */
2862 {
2866 }
2870 }
2872 \f
2873 /*
2874 * ================
2875 * = dfx_rcv_init =
2876 * ================
2877 *
2878 * Overview:
2879 * Produces buffers to adapter LLC Host receive descriptor block
2880 *
2881 * Returns:
2882 * None
2883 *
2884 * Arguments:
2885 * bp - pointer to board information
2886 *
2887 * Functional Description:
2888 * This routine can be called during dfx_adap_init() or during an adapter
2889 * reset. It initializes the descriptor block and produces all allocated
2890 * LLC Host queue receive buffers.
2891 *
2892 * Return Codes:
2893 * None
2894 *
2895 * Assumptions:
2896 * The PDQ has been reset and the adapter and driver maintained Type 2
2897 * register indices are cleared.
2898 *
2899 * Side Effects:
2900 * Receive buffers are posted to the adapter LLC queue and the adapter
2901 * is notified.
2902 */
2905 DFX_board_t *bp
2906 )
2908 {
2911 /*
2912 * Since each receive buffer is a single fragment of same length, initialize
2913 * first longword in each receive descriptor for entire LLC Host descriptor
2914 * block. Also initialize second longword in each receive descriptor with
2915 * physical address of receive buffer. We'll always allocate receive
2916 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
2917 * block and produce new receive buffers by simply updating the receive
2918 * producer index.
2919 *
2920 * Assumptions:
2921 * To support all shipping versions of PDQ, the receive buffer size
2922 * must be mod 128 in length and the physical address must be 128 byte
2923 * aligned. In other words, bits 0-6 of the length and address must
2924 * be zero for the following descriptor field entries to be correct on
2925 * all PDQ-based boards. We guaranteed both requirements during
2926 * driver initialization when we allocated memory for the receive buffers.
2927 */
2931 {
2934 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
2936 }
2938 /* Update receive producer and Type 2 register */
2943 }
2945 \f
2946 /*
2947 * =========================
2948 * = dfx_rcv_queue_process =
2949 * =========================
2950 *
2951 * Overview:
2952 * Process received LLC frames.
2953 *
2954 * Returns:
2955 * None
2956 *
2957 * Arguments:
2958 * bp - pointer to board information
2959 *
2960 * Functional Description:
2961 * Received LLC frames are processed until there are no more consumed frames.
2962 * Once all frames are processed, the receive buffers are returned to the
2963 * adapter. Note that this algorithm fixes the length of time that can be spent
2964 * in this routine, because there are a fixed number of receive buffers to
2965 * process and buffers are not produced until this routine exits and returns
2966 * to the ISR.
2967 *
2968 * Return Codes:
2969 * None
2970 *
2971 * Assumptions:
2972 * None
2973 *
2974 * Side Effects:
2975 * None
2976 */
2979 DFX_board_t *bp
2980 )
2982 {
2988 /* Service all consumed LLC receive frames */
2992 {
2993 /* Process any errors */
2999 {
3002 else
3004 }
3005 else
3006 {
3007 /* The frame was received without errors - verify packet length */
3013 else
3014 {
3017 {
3020 }
3021 else
3022 {
3023 /* Receive buffer allocated, pass receive packet up */
3032 /* Update the rcv counters */
3037 }
3038 }
3039 }
3041 /*
3042 * Advance the producer (for recycling) and advance the completion
3043 * (for servicing received frames). Note that it is okay to
3044 * advance the producer without checking that it passes the
3045 * completion index because they are both advanced at the same
3046 * rate.
3047 */
3051 }
3053 }
3055 \f
3056 /*
3057 * =====================
3058 * = dfx_xmt_queue_pkt =
3059 * =====================
3060 *
3061 * Overview:
3062 * Queues packets for transmission
3063 *
3064 * Returns:
3065 * Condition code
3066 *
3067 * Arguments:
3068 * skb - pointer to sk_buff to queue for transmission
3069 * dev - pointer to device information
3070 *
3071 * Functional Description:
3072 * Here we assume that an incoming skb transmit request
3073 * is contained in a single physically contiguous buffer
3074 * in which the virtual address of the start of packet
3075 * (skb->data) can be converted to a physical address
3076 * by using virt_to_bus().
3077 *
3078 * Since the adapter architecture requires a three byte
3079 * packet request header to prepend the start of packet,
3080 * we'll write the three byte field immediately prior to
3081 * the FC byte. This assumption is valid because we've
3082 * ensured that dev->hard_header_len includes three pad
3083 * bytes. By posting a single fragment to the adapter,
3084 * we'll reduce the number of descriptor fetches and
3085 * bus traffic needed to send the request.
3086 *
3087 * Also, we can't free the skb until after it's been DMA'd
3088 * out by the adapter, so we'll queue it in the driver and
3089 * return it in dfx_xmt_done.
3090 *
3091 * Return Codes:
3092 * 0 - driver queued packet, link is unavailable, or skbuff was bad
3093 * 1 - caller should requeue the sk_buff for later transmission
3094 *
3095 * Assumptions:
3096 * First and foremost, we assume the incoming skb pointer
3097 * is NOT NULL and is pointing to a valid sk_buff structure.
3098 *
3099 * The outgoing packet is complete, starting with the
3100 * frame control byte including the last byte of data,
3101 * but NOT including the 4 byte CRC. We'll let the
3102 * adapter hardware generate and append the CRC.
3103 *
3104 * The entire packet is stored in one physically
3105 * contiguous buffer which is not cached and whose
3106 * 32-bit physical address can be determined.
3107 *
3108 * It's vital that this routine is NOT reentered for the
3109 * same board and that the OS is not in another section of
3110 * code (eg. dfx_int_common) for the same board on a
3111 * different thread.
3112 *
3113 * Side Effects:
3114 * None
3115 */
3120 )
3122 {
3128 /*
3129 * Verify that incoming transmit request is OK
3130 *
3131 * Note: The packet size check is consistent with other
3132 * Linux device drivers, although the correct packet
3133 * size should be verified before calling the
3134 * transmit routine.
3135 */
3138 {
3144 }
3145 /*
3146 * See if adapter link is available, if not, free buffer
3147 *
3148 * Note: If the link isn't available, free buffer and return 0
3149 * rather than tell the upper layer to requeue the packet.
3150 * The methodology here is that by the time the link
3151 * becomes available, the packet to be sent will be
3152 * fairly stale. By simply dropping the packet, the
3153 * higher layer protocols will eventually time out
3154 * waiting for response packets which it won't receive.
3155 */
3158 {
3161 else
3162 {
3166 }
3167 }
3169 /* Get the current producer and the next free xmt data descriptor */
3174 /*
3175 * Get pointer to auxiliary queue entry to contain information for this packet.
3176 *
3177 * Note: The current xmt producer index will become the current xmt completion
3178 * index when we complete this packet later on. So, we'll get the
3179 * pointer to the next auxiliary queue entry now before we bump the
3180 * producer index.
3181 */
3185 /* Write the three PRH bytes immediately before the FC byte */
3191 /*
3192 * Write the descriptor with buffer info and bump producer
3193 *
3194 * Note: Since we need to start DMA from the packet request
3195 * header, we'll add 3 bytes to the DMA buffer length,
3196 * and we'll determine the physical address of the
3197 * buffer from the PRH, not skb->data.
3198 *
3199 * Assumptions:
3200 * 1. Packet starts with the frame control (FC) byte
3201 * at skb->data.
3202 * 2. The 4-byte CRC is not appended to the buffer or
3203 * included in the length.
3204 * 3. Packet length (skb->len) is from FC to end of
3205 * data, inclusive.
3206 * 4. The packet length does not exceed the maximum
3207 * FDDI LLC frame length of 4491 bytes.
3208 * 5. The entire packet is contained in a physically
3209 * contiguous, non-cached, locked memory space
3210 * comprised of a single buffer pointed to by
3211 * skb->data.
3212 * 6. The physical address of the start of packet
3213 * can be determined from the virtual address
3214 * by using virt_to_bus() and is only 32-bits
3215 * wide.
3216 */
3218 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len + 3) << PI_XMT_DESCR_V_SEG_LEN));
3221 /*
3222 * Verify that descriptor is actually available
3223 *
3224 * Note: If descriptor isn't available, return 1 which tells
3225 * the upper layer to requeue the packet for later
3226 * transmission.
3227 *
3228 * We need to ensure that the producer never reaches the
3229 * completion, except to indicate that the queue is empty.
3230 */
3235 /*
3236 * Save info for this packet for xmt done indication routine
3237 *
3238 * Normally, we'd save the producer index in the p_xmt_drv_descr
3239 * structure so that we'd have it handy when we complete this
3240 * packet later (in dfx_xmt_done). However, since the current
3241 * transmit architecture guarantees a single fragment for the
3242 * entire packet, we can simply bump the completion index by
3243 * one (1) for each completed packet.
3244 *
3245 * Note: If this assumption changes and we're presented with
3246 * an inconsistent number of transmit fragments for packet
3247 * data, we'll need to modify this code to save the current
3248 * transmit producer index.
3249 */
3253 /* Update Type 2 register */
3258 }
3260 \f
3261 /*
3262 * ================
3263 * = dfx_xmt_done =
3264 * ================
3265 *
3266 * Overview:
3267 * Processes all frames that have been transmitted.
3268 *
3269 * Returns:
3270 * None
3271 *
3272 * Arguments:
3273 * bp - pointer to board information
3274 *
3275 * Functional Description:
3276 * For all consumed transmit descriptors that have not
3277 * yet been completed, we'll free the skb we were holding
3278 * onto using dev_kfree_skb and bump the appropriate
3279 * counters.
3280 *
3281 * Return Codes:
3282 * None
3283 *
3284 * Assumptions:
3285 * The Type 2 register is not updated in this routine. It is
3286 * assumed that it will be updated in the ISR when dfx_xmt_done
3287 * returns.
3288 *
3289 * Side Effects:
3290 * None
3291 */
3294 DFX_board_t *bp
3295 )
3297 {
3301 /* Service all consumed transmit frames */
3305 {
3306 /* Get pointer to the transmit driver descriptor block information */
3310 /* Return skb to operating system */
3314 /* Increment transmit counters */
3318 /*
3319 * Move to start of next packet by updating completion index
3320 *
3321 * Here we assume that a transmit packet request is always
3322 * serviced by posting one fragment. We can therefore
3323 * simplify the completion code by incrementing the
3324 * completion index by one. This code will need to be
3325 * modified if this assumption changes. See comments
3326 * in dfx_xmt_queue_pkt for more details.
3327 */
3330 }
3332 }
3334 \f
3335 /*
3336 * =================
3337 * = dfx_xmt_flush =
3338 * =================
3339 *
3340 * Overview:
3341 * Processes all frames whether they've been transmitted
3342 * or not.
3343 *
3344 * Returns:
3345 * None
3346 *
3347 * Arguments:
3348 * bp - pointer to board information
3349 *
3350 * Functional Description:
3351 * For all produced transmit descriptors that have not
3352 * yet been completed, we'll free the skb we were holding
3353 * onto using dev_kfree_skb and bump the appropriate
3354 * counters. Of course, it's possible that some of
3355 * these transmit requests actually did go out, but we
3356 * won't make that distinction here. Finally, we'll
3357 * update the consumer index to match the producer.
3358 *
3359 * Return Codes:
3360 * None
3361 *
3362 * Assumptions:
3363 * This routine does NOT update the Type 2 register. It
3364 * is assumed that this routine is being called during a
3365 * transmit flush interrupt, or a shutdown or close routine.
3366 *
3367 * Side Effects:
3368 * None
3369 */
3372 DFX_board_t *bp
3373 )
3375 {
3379 /* Flush all outstanding transmit frames */
3382 {
3383 /* Get pointer to the transmit driver descriptor block information */
3387 /* Return skb to operating system */
3391 /* Increment transmit error counter */
3395 /*
3396 * Move to start of next packet by updating completion index
3397 *
3398 * Here we assume that a transmit packet request is always
3399 * serviced by posting one fragment. We can therefore
3400 * simplify the completion code by incrementing the
3401 * completion index by one. This code will need to be
3402 * modified if this assumption changes. See comments
3403 * in dfx_xmt_queue_pkt for more details.
3404 */
3407 }
3409 /* Update the transmit consumer index in the consumer block */
3415 }
3417 \f
3418 /*
3419 * Local variables:
3420 * kernel-compile-command: "gcc -D__KERNEL__ -I/root/linux/include -Wall -Wstrict-prototypes -O2 -pipe -fomit-frame-pointer -fno-strength-reduce -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -DCPU=586 -c defxx.c"
3421 * End:
3422 */