1 /* $Id: viking.S,v 1.2 1997/04/20 21:21:49 ecd Exp $
2 * viking.S: High speed Viking cache/mmu operations
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
7 #include <asm/ptrace.h>
12 #include <asm/pgtsrmmu.h>
13 #include <asm/viking.h>
14 #include <asm/cprefix.h>
16 #define WINDOW_FLUSH(tmp1, tmp2) \
18 98: ld [%g6 + AOFF_task_tss + AOFF_thread_uwinmask], tmp2; \
19 orcc %g0, tmp2, %g0; \
23 99: subcc tmp1, 1, tmp1; \
25 restore %g0, %g0, %g0;
30 .globl viking_flush_cache_all, viking_flush_cache_mm
31 .globl viking_flush_cache_range, viking_flush_cache_page
32 .globl viking_flush_page, viking_mxcc_flush_page
33 .globl viking_flush_page_for_dma, viking_flush_page_to_ram
34 .globl viking_flush_chunk, viking_mxcc_flush_chunk
35 .globl viking_flush_sig_insns
36 .globl viking_flush_tlb_all, viking_flush_tlb_mm
37 .globl viking_flush_tlb_range, viking_flush_tlb_page
41 sethi %hi(C_LABEL(srmmu_map)), %g2
42 or %g2, %lo(C_LABEL(srmmu_map)), %g3
46 and %o0, PAGE_MASK, %o0
63 srl %g3, 12, %g1 ! ppage >> 12
75 clr %o1 ! set counter, 0 - 127
76 sethi %hi(KERNBASE + PAGE_SIZE - 0x80000000), %o3
77 sethi %hi(0x80000000), %o4
78 sethi %hi(VIKING_PTAG_VALID | VIKING_PTAG_DIRTY), %o5
79 sethi %hi(PAGE_SIZE), %o0
80 clr %o2 ! block counter, 0 - 3
83 or %g4, %o4, %g4 ! 0x80000000 | (set << 5)
85 sll %o2, 26, %g5 ! block << 26
88 ldda [%g5] ASI_M_DATAC_TAG, %g2
89 cmp %g3, %g1 ! ptag == ppage?
93 and %g2, %o5, %g3 ! ptag VALID and DIRTY?
98 add %g4, %o3, %g2 ! (KERNBASE + PAGE_SIZE) | (set << 5)
121 sll %o2, 26, %g5 ! block << 26
133 viking_mxcc_flush_page:
134 sethi %hi(C_LABEL(srmmu_map)), %g2
135 or %g2, %lo(C_LABEL(srmmu_map)), %g3
139 and %o0, PAGE_MASK, %o0
155 sethi %hi(PAGE_SIZE), %g4
157 add %g3, %g4, %g3 ! ppage + PAGE_SIZE
168 mov 0x10, %g2 ! set cacheable bit
169 sethi %hi(MXCC_SRCSTREAM), %o2
170 or %o2, %lo(MXCC_SRCSTREAM), %o2
171 sethi %hi(MXCC_DESSTREAM), %o3
172 or %o3, %lo(MXCC_DESSTREAM), %o3
175 sub %g3, MXCC_STREAM_SIZE, %g3
177 stda %g2, [%o2] ASI_M_MXCC
178 stda %g2, [%o3] ASI_M_MXCC
179 andncc %g3, PAGE_MASK, %g0
181 sub %g3, MXCC_STREAM_SIZE, %g3
186 viking_mxcc_flush_chunk:
190 viking_flush_cache_all:
191 viking_flush_cache_mm:
192 viking_flush_cache_range:
193 viking_flush_cache_page:
197 viking_flush_tlb_all:
198 WINDOW_FLUSH(%g4, %g5)
201 sta %g0, [%g1] ASI_M_FLUSH_PROBE
204 mov SRMMU_CTX_REG, %g1
205 ld [%o0 + AOFF_mm_context], %o1
206 lda [%g1] ASI_M_MMUREGS, %g5
209 be viking_flush_tlb_mm_out
211 WINDOW_FLUSH(%g2, %g3)
214 sta %o1, [%g1] ASI_M_MMUREGS
215 sta %g0, [%g2] ASI_M_FLUSH_PROBE
216 viking_flush_tlb_mm_out:
218 sta %g5, [%g1] ASI_M_MMUREGS
220 viking_flush_tlb_range:
221 mov SRMMU_CTX_REG, %g1
222 ld [%o0 + AOFF_mm_context], %o3
223 lda [%g1] ASI_M_MMUREGS, %g5
226 be viking_flush_tlb_range_out
228 WINDOW_FLUSH(%g2, %g3)
230 srl %o1, SRMMU_PGDIR_SHIFT, %o1
231 sta %o3, [%g1] ASI_M_MMUREGS
232 sll %o1, SRMMU_PGDIR_SHIFT, %o1
233 sethi %hi(1 << SRMMU_PGDIR_SHIFT), %o4
235 sta %g0, [%o1] ASI_M_FLUSH_PROBE
240 sta %g0, [%o1] ASI_M_FLUSH_PROBE
241 viking_flush_tlb_range_out:
243 sta %g5, [%g1] ASI_M_MMUREGS
245 viking_flush_tlb_page:
246 ld [%o0 + 0x00], %o0 /* XXX vma->vm_mm GROSS XXX */
247 mov SRMMU_CTX_REG, %g1
248 ld [%o0 + AOFF_mm_context], %o3
249 and %o1, PAGE_MASK, %o1
250 lda [%g1] ASI_M_MMUREGS, %g5
253 be viking_flush_tlb_page_out
255 WINDOW_FLUSH(%g2, %g3)
257 sta %o3, [%g1] ASI_M_MMUREGS
258 sta %g0, [%o1] ASI_M_FLUSH_PROBE
259 viking_flush_tlb_page_out:
261 sta %g5, [%g1] ASI_M_MMUREGS
263 viking_flush_page_to_ram:
264 viking_flush_page_for_dma:
265 viking_flush_sig_insns: