drivers/block/hpt343.c

   1 /*
   2  * linux/drivers/block/hpt343.c         Version 0.23    May 12, 1999
   3  *
   4  * Copyright (C) 1998-99        Andre Hedrick
   5  *                                      (hedrick@astro.dyer.vanderbilt.edu)
   6  *
   7  * 00:12.0 Unknown mass storage controller:
   8  * Triones Technologies, Inc.
   9  * Unknown device 0003 (rev 01)
  10  *
  11  * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
  12  * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
  13  * hde: DMA 2  (0x0000 0x0002) (0x0000 0x0010)
  14  * hdf: DMA 2  (0x0002 0x0012) (0x0010 0x0030)
  15  * hdg: DMA 1  (0x0012 0x0052) (0x0030 0x0070)
  16  * hdh: DMA 1  (0x0052 0x0252) (0x0070 0x00f0)
  17  *
  18  * drive_number
  19  *      = ((HWIF(drive)->channel ? 2 : 0) + (drive->select.b.unit & 0x01));
  20  *      = ((hwif->channel ? 2 : 0) + (drive->select.b.unit & 0x01));
  21  */
  22
  23 #include <linux/config.h>       /* for CONFIG_BLK_DEV_IDEPCI */
  24 #include <linux/types.h>
  25 #include <linux/kernel.h>
  26 #include <linux/delay.h>
  27 #include <linux/timer.h>
  28 #include <linux/mm.h>
  29 #include <linux/ioport.h>
  30 #include <linux/blkdev.h>
  31 #include <linux/hdreg.h>
  32
  33 #include <linux/interrupt.h>
  34 #include <linux/pci.h>
  35 #include <linux/init.h>
  36 #include <linux/ide.h>
  37
  38 #include <asm/io.h>
  39 #include <asm/irq.h>
  40
  41 #include "ide_modes.h"
  42
  43 #ifndef SPLIT_BYTE
  44 #define SPLIT_BYTE(B,H,L)       ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
  45 #endif
  46
  47 #define HPT343_DEBUG_DRIVE_INFO         0
  48 #define HPT343_DISABLE_ALL_DMAING       0
  49 #define HPT343_DMA_DISK_ONLY            0
  50
  51 extern char *ide_xfer_verbose (byte xfer_rate);
  52
  53 static void hpt343_clear_chipset (ide_drive_t *drive)
  54 {
  55         int drive_number        = ((HWIF(drive)->channel ? 2 : 0) + (drive->select.b.unit & 0x01));
  56         unsigned int reg1       = 0, tmp1 = 0;
  57         unsigned int reg2       = 0, tmp2 = 0;
  58
  59         pci_read_config_dword(HWIF(drive)->pci_dev, 0x44, &reg1);
  60         pci_read_config_dword(HWIF(drive)->pci_dev, 0x48, &reg2);
  61         tmp1 = ((0x00 << (3*drive_number)) | (reg1 & ~(7 << (3*drive_number))));
  62         tmp2 = ((0x00 << drive_number) | reg2);
  63         pci_write_config_dword(HWIF(drive)->pci_dev, 0x44, tmp1);
  64         pci_write_config_dword(HWIF(drive)->pci_dev, 0x48, tmp2);
  65 }
  66
  67 static int hpt343_tune_chipset (ide_drive_t *drive, byte speed)
  68 {
  69         int                     err;
  70         byte                    hi_speed, lo_speed;
  71         int drive_number        = ((HWIF(drive)->channel ? 2 : 0) + (drive->select.b.unit & 0x01));
  72         unsigned int reg1       = 0, tmp1 = 0;
  73         unsigned int reg2       = 0, tmp2 = 0;
  74
  75         SPLIT_BYTE(speed, hi_speed, lo_speed);
  76
  77         if (hi_speed & 7) {
  78                 hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
  79         } else {
  80                 lo_speed <<= 5;
  81                 lo_speed >>= 5;
  82         }
  83
  84         pci_read_config_dword(HWIF(drive)->pci_dev, 0x44, &reg1);
  85         pci_read_config_dword(HWIF(drive)->pci_dev, 0x48, &reg2);
  86         tmp1 = ((lo_speed << (3*drive_number)) | (reg1 & ~(7 << (3*drive_number))));
  87         tmp2 = ((hi_speed << drive_number) | reg2);
  88         err = ide_wait_cmd(drive, WIN_SETFEATURES, speed, SETFEATURES_XFER, 0, NULL);
  89         pci_write_config_dword(HWIF(drive)->pci_dev, 0x44, tmp1);
  90         pci_write_config_dword(HWIF(drive)->pci_dev, 0x48, tmp2);
  91
  92 #if HPT343_DEBUG_DRIVE_INFO
  93         printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
  94                 " (0x%02x 0x%02x) 0x%04x\n",
  95                 drive->name, ide_xfer_verbose(speed),
  96                 drive_number, reg1, tmp1, reg2, tmp2,
  97                 hi_speed, lo_speed, err);
  98 #endif /* HPT343_DEBUG_DRIVE_INFO */
  99
 100         return(err);
 101 }
 102
 103 /*
 104  * This allows the configuration of ide_pci chipset registers
 105  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 106  * after the drive is reported by the OS.  Initally for designed for
 107  * HPT343 UDMA chipset by HighPoint|Triones Technologies, Inc.
 108  */
 109 static int config_chipset_for_dma (ide_drive_t *drive)
 110 {
 111         struct hd_driveid *id   = drive->id;
 112         byte speed              = 0x00;
 113
 114 #if HPT343_DISABLE_ALL_DMAING
 115         return ((int) ide_dma_off);
 116 #elif HPT343_DMA_DISK_ONLY
 117         if (drive->media != ide_disk)
 118                 return ((int) ide_dma_off_quietly);
 119 #endif /* HPT343_DISABLE_ALL_DMAING */
 120
 121         if (id->dma_ultra & 0x0004) {
 122                 if (!((id->dma_ultra >> 8) & 4)) {
 123                         drive->id->dma_ultra &= ~0x0F00;
 124                         drive->id->dma_ultra |= 0x0404;
 125                         drive->id->dma_mword &= ~0x0F00;
 126                         drive->id->dma_1word &= ~0x0F00;
 127                 }
 128                 speed = XFER_UDMA_2;
 129         } else if (id->dma_ultra & 0x0002) {
 130                 if (!((id->dma_ultra >> 8) & 2)) {
 131                         drive->id->dma_ultra &= ~0x0F00;
 132                         drive->id->dma_ultra |= 0x0202;
 133                         drive->id->dma_mword &= ~0x0F00;
 134                         drive->id->dma_1word &= ~0x0F00;
 135                 }
 136                 speed = XFER_UDMA_1;
 137         } else if (id->dma_ultra & 0x0001) {
 138                 if (!((id->dma_ultra >> 8) & 1)) {
 139                         drive->id->dma_ultra &= ~0x0F00;
 140                         drive->id->dma_ultra |= 0x0101;
 141                         drive->id->dma_mword &= ~0x0F00;
 142                         drive->id->dma_1word &= ~0x0F00;
 143                 }
 144                 speed = XFER_UDMA_0;
 145         } else if (id->dma_mword & 0x0004) {
 146                 if (!((id->dma_mword >> 8) & 4)) {
 147                         drive->id->dma_mword &= ~0x0F00;
 148                         drive->id->dma_mword |= 0x0404;
 149                         drive->id->dma_1word &= ~0x0F00;
 150                 }
 151                 speed = XFER_MW_DMA_2;
 152         } else if (id->dma_mword & 0x0002) {
 153                 if (!((id->dma_mword >> 8) & 2)) {
 154                         drive->id->dma_mword &= ~0x0F00;
 155                         drive->id->dma_mword |= 0x0202;
 156                         drive->id->dma_1word &= ~0x0F00;
 157                 }
 158                 speed = XFER_MW_DMA_1;
 159         } else if (id->dma_mword & 0x0001) {
 160                 if (!((id->dma_mword >> 8) & 1)) {
 161                         drive->id->dma_mword &= ~0x0F00;
 162                         drive->id->dma_mword |= 0x0101;
 163                         drive->id->dma_1word &= ~0x0F00;
 164                 }
 165                 speed = XFER_MW_DMA_0;
 166         } else if (id->dma_1word & 0x0004) {
 167                 if (!((id->dma_1word >> 8) & 4)) {
 168                         drive->id->dma_1word &= ~0x0F00;
 169                         drive->id->dma_1word |= 0x0404;
 170                         drive->id->dma_mword &= ~0x0F00;
 171                 }
 172                 speed = XFER_SW_DMA_2;
 173         } else if (id->dma_1word & 0x0002) {
 174                 if (!((id->dma_1word >> 8) & 2)) {
 175                         drive->id->dma_1word &= ~0x0F00;
 176                         drive->id->dma_1word |= 0x0202;
 177                         drive->id->dma_mword &= ~0x0F00;
 178                 }
 179                 speed = XFER_SW_DMA_1;
 180         } else if (id->dma_1word & 0x0001) {
 181                 if (!((id->dma_1word >> 8) & 1)) {
 182                         drive->id->dma_1word &= ~0x0F00;
 183                         drive->id->dma_1word |= 0x0101;
 184                         drive->id->dma_mword &= ~0x0F00;
 185                 }
 186                 speed = XFER_SW_DMA_0;
 187         } else {
 188                 return ((int) ide_dma_off_quietly);
 189         }
 190
 191         (void) hpt343_tune_chipset(drive, speed);
 192
 193         return ((int)   ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
 194                         ((id->dma_mword >> 8) & 7) ? ide_dma_on :
 195                         ((id->dma_1word >> 8) & 7) ? ide_dma_on :
 196                                                      ide_dma_off_quietly);
 197 }
 198
 199 static void config_chipset_for_pio (ide_drive_t *drive)
 200 {
 201         unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
 202         unsigned short xfer_pio = drive->id->eide_pio_modes;
 203
 204         byte                    timing, speed, pio;
 205
 206         pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
 207
 208         if (xfer_pio> 4)
 209                 xfer_pio = 0;
 210
 211         if (drive->id->eide_pio_iordy > 0) {
 212                 for (xfer_pio = 5;
 213                         xfer_pio>0 &&
 214                         drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
 215                         xfer_pio--);
 216         } else {
 217                 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
 218                            (drive->id->eide_pio_modes & 2) ? 0x04 :
 219                            (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
 220         }
 221
 222         timing = (xfer_pio >= pio) ? xfer_pio : pio;
 223
 224         switch(timing) {
 225                 case 4: speed = XFER_PIO_4;break;
 226                 case 3: speed = XFER_PIO_3;break;
 227                 case 2: speed = XFER_PIO_2;break;
 228                 case 1: speed = XFER_PIO_1;break;
 229                 default:
 230                         speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
 231                         break;
 232         }
 233
 234         (void) hpt343_tune_chipset(drive, speed);
 235 }
 236
 237 #if 0
 238 static void hpt343_tune_drive (ide_drive_t *drive, byte pio)
 239 {
 240 }
 241 #endif
 242
 243 static int config_drive_xfer_rate (ide_drive_t *drive)
 244 {
 245         struct hd_driveid *id = drive->id;
 246         ide_dma_action_t dma_func = ide_dma_on;
 247
 248         if (id && (id->capability & 1) && HWIF(drive)->autodma) {
 249                 /* Consult the list of known "bad" drives */
 250                 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
 251                         dma_func = ide_dma_off;
 252                         goto fast_ata_pio;
 253                 }
 254                 dma_func = ide_dma_off_quietly;
 255                 if (id->field_valid & 4) {
 256                         if (id->dma_ultra & 0x0007) {
 257                                 /* Force if Capable UltraDMA */
 258                                 dma_func = config_chipset_for_dma(drive);
 259                                 if ((id->field_valid & 2) &&
 260                                     (dma_func != ide_dma_on))
 261                                         goto try_dma_modes;
 262                         }
 263                 } else if (id->field_valid & 2) {
 264 try_dma_modes:
 265                         if ((id->dma_mword & 0x0007) ||
 266                             (id->dma_1word & 0x0007)) {
 267                                 /* Force if Capable regular DMA modes */
 268                                 dma_func = config_chipset_for_dma(drive);
 269                                 if (dma_func != ide_dma_on)
 270                                         goto no_dma_set;
 271                         }
 272                 } else if (ide_dmaproc(ide_dma_good_drive, drive)) {
 273                         if (id->eide_dma_time > 150) {
 274                                 goto no_dma_set;
 275                         }
 276                         /* Consult the list of known "good" drives */
 277                         dma_func = config_chipset_for_dma(drive);
 278                         if (dma_func != ide_dma_on)
 279                                 goto no_dma_set;
 280                 } else {
 281                         goto fast_ata_pio;
 282                 }
 283         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 284 fast_ata_pio:
 285                 dma_func = ide_dma_off_quietly;
 286 no_dma_set:
 287
 288                 config_chipset_for_pio(drive);
 289         }
 290         return HWIF(drive)->dmaproc(dma_func, drive);
 291 }
 292
 293 /*
 294  * hpt343_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
 295  *
 296  * This is specific to the HPT343 UDMA bios-less chipset
 297  * and HPT345 UDMA bios chipset (stamped HPT363)
 298  * by HighPoint|Triones Technologies, Inc.
 299  */
 300
 301 int hpt343_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
 302 {
 303         switch (func) {
 304                 case ide_dma_check:
 305                         hpt343_clear_chipset(drive);
 306                         return config_drive_xfer_rate(drive);
 307 #if 0
 308                 case ide_dma_off:
 309                 case ide_dma_off_quietly:
 310                 case ide_dma_on:
 311                 case ide_dma_check:
 312                         return config_drive_xfer_rate(drive);
 313                 case ide_dma_read:
 314                 case ide_dma_write:
 315                 case ide_dma_begin:
 316                 case ide_dma_end:
 317                 case ide_dma_test_irq:
 318 #endif
 319                 default:
 320                         break;
 321         }
 322         return ide_dmaproc(func, drive);        /* use standard DMA stuff */
 323 }
 324
 325 /*
 326  * If the BIOS does not set the IO base addaress to XX00, 343 will fail.
 327  */
 328 #define HPT343_PCI_INIT_REG             0x80
 329
 330 __initfunc(unsigned int pci_init_hpt343 (struct pci_dev *dev, const char *name))
 331 {
 332         int i;
 333         unsigned short cmd;
 334         unsigned long hpt343IoBase = dev->base_address[4] & PCI_BASE_ADDRESS_IO_MASK;
 335 #if 0
 336         unsigned char misc10 = inb(hpt343IoBase + 0x0010);
 337         unsigned char misc11 = inb(hpt343IoBase + 0x0011);
 338 #endif
 339
 340         pci_write_config_byte(dev, HPT343_PCI_INIT_REG, 0x00);
 341         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 342         pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
 343
 344         dev->base_address[0] = (hpt343IoBase + 0x20);
 345         dev->base_address[1] = (hpt343IoBase + 0x34);
 346         dev->base_address[2] = (hpt343IoBase + 0x28);
 347         dev->base_address[3] = (hpt343IoBase + 0x3c);
 348
 349         for(i=0; i<4; i++)
 350                 dev->base_address[i] |= PCI_BASE_ADDRESS_SPACE_IO;
 351
 352         /*
 353          * Since 20-23 can be assigned and are R/W, we correct them.
 354          */
 355         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, dev->base_address[0]);
 356         pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, dev->base_address[1]);
 357         pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, dev->base_address[2]);
 358         pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, dev->base_address[3]);
 359         pci_write_config_word(dev, PCI_COMMAND, cmd);
 360
 361 #if 0
 362         outb(misc10|0x78, (hpt343IoBase + 0x0010));
 363         outb(misc11, (hpt343IoBase + 0x0011));
 364 #endif
 365
 366 #ifdef DEBUG
 367         printk("%s: 0x%02x 0x%02x\n",
 368                 (pcicmd & PCI_COMMAND_MEMORY) ? "HPT345" : name,
 369                 inb(hpt343IoBase + 0x0010),
 370                 inb(hpt343IoBase + 0x0011));
 371 #endif
 372
 373         if (cmd & PCI_COMMAND_MEMORY) {
 374                 if (dev->rom_address) {
 375                         pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->rom_address | PCI_ROM_ADDRESS_ENABLE);
 376                         printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n", dev->rom_address);
 377                 }
 378         } else {
 379                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
 380         }
 381         return dev->irq;
 382 }
 383
 384 __initfunc(void ide_init_hpt343 (ide_hwif_t *hwif))
 385 {
 386         if (hwif->dma_base) {
 387                 unsigned short pcicmd = 0;
 388
 389                 pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd);
 390                 hwif->autodma = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0;
 391                 hwif->dmaproc = &hpt343_dmaproc;
 392         }
 393 }