include/asm-sparc/pgtsrmmu.h

   1 /* $Id: pgtsrmmu.h,v 1.31 2000/07/16 21:48:52 anton Exp $
   2  * pgtsrmmu.h:  SRMMU page table defines and code.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6
   7 #ifndef _SPARC_PGTSRMMU_H
   8 #define _SPARC_PGTSRMMU_H
   9
  10 #include <asm/page.h>
  11
  12 /* PMD_SHIFT determines the size of the area a second-level page table can map */
  13 #define SRMMU_PMD_SHIFT         18
  14 #define SRMMU_PMD_SIZE          (1UL << SRMMU_PMD_SHIFT)
  15 #define SRMMU_PMD_MASK          (~(SRMMU_PMD_SIZE-1))
  16 #define SRMMU_PMD_ALIGN(addr)   (((addr)+SRMMU_PMD_SIZE-1)&SRMMU_PMD_MASK)
  17
  18 /* PGDIR_SHIFT determines what a third-level page table entry can map */
  19 #define SRMMU_PGDIR_SHIFT       24
  20 #define SRMMU_PGDIR_SIZE        (1UL << SRMMU_PGDIR_SHIFT)
  21 #define SRMMU_PGDIR_MASK        (~(SRMMU_PGDIR_SIZE-1))
  22 #define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
  23
  24 #define SRMMU_PTRS_PER_PTE      64
  25 #define SRMMU_PTRS_PER_PMD      64
  26 #define SRMMU_PTRS_PER_PGD      256
  27
  28 #define SRMMU_PTE_TABLE_SIZE    0x100 /* 64 entries, 4 bytes a piece */
  29 #define SRMMU_PMD_TABLE_SIZE    0x100 /* 64 entries, 4 bytes a piece */
  30 #define SRMMU_PGD_TABLE_SIZE    0x400 /* 256 entries, 4 bytes a piece */
  31
  32 /* Definition of the values in the ET field of PTD's and PTE's */
  33 #define SRMMU_ET_MASK         0x3
  34 #define SRMMU_ET_INVALID      0x0
  35 #define SRMMU_ET_PTD          0x1
  36 #define SRMMU_ET_PTE          0x2
  37 #define SRMMU_ET_REPTE        0x3 /* AIEEE, SuperSparc II reverse endian page! */
  38
  39 /* Physical page extraction from PTP's and PTE's. */
  40 #define SRMMU_CTX_PMASK    0xfffffff0
  41 #define SRMMU_PTD_PMASK    0xfffffff0
  42 #define SRMMU_PTE_PMASK    0xffffff00
  43
  44 /* The pte non-page bits.  Some notes:
  45  * 1) cache, dirty, valid, and ref are frobbable
  46  *    for both supervisor and user pages.
  47  * 2) exec and write will only give the desired effect
  48  *    on user pages
  49  * 3) use priv and priv_readonly for changing the
  50  *    characteristics of supervisor ptes
  51  */
  52 #define SRMMU_CACHE        0x80
  53 #define SRMMU_DIRTY        0x40
  54 #define SRMMU_REF          0x20
  55 #define SRMMU_EXEC         0x08
  56 #define SRMMU_WRITE        0x04
  57 #define SRMMU_VALID        0x02 /* SRMMU_ET_PTE */
  58 #define SRMMU_PRIV         0x1c
  59 #define SRMMU_PRIV_RDONLY  0x18
  60
  61 #define SRMMU_CHG_MASK    (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
  62
  63 /* Some day I will implement true fine grained access bits for
  64  * user pages because the SRMMU gives us the capabilities to
  65  * enforce all the protection levels that vma's can have.
  66  * XXX But for now...
  67  */
  68 #define SRMMU_PAGE_NONE    __pgprot(SRMMU_VALID | SRMMU_CACHE | \
  69                                     SRMMU_PRIV | SRMMU_REF)
  70 #define SRMMU_PAGE_SHARED  __pgprot(SRMMU_VALID | SRMMU_CACHE | \
  71                                     SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
  72 #define SRMMU_PAGE_COPY    __pgprot(SRMMU_VALID | SRMMU_CACHE | \
  73                                     SRMMU_EXEC | SRMMU_REF)
  74 #define SRMMU_PAGE_RDONLY  __pgprot(SRMMU_VALID | SRMMU_CACHE | \
  75                                     SRMMU_EXEC | SRMMU_REF)
  76 #define SRMMU_PAGE_KERNEL  __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
  77                                     SRMMU_DIRTY | SRMMU_REF)
  78
  79 /* SRMMU Register addresses in ASI 0x4.  These are valid for all
  80  * current SRMMU implementations that exist.
  81  */
  82 #define SRMMU_CTRL_REG           0x00000000
  83 #define SRMMU_CTXTBL_PTR         0x00000100
  84 #define SRMMU_CTX_REG            0x00000200
  85 #define SRMMU_FAULT_STATUS       0x00000300
  86 #define SRMMU_FAULT_ADDR         0x00000400
  87
  88 #define WINDOW_FLUSH(tmp1, tmp2)                                        \
  89         mov     0, tmp1;                                                \
  90 98:     ld      [%g6 + AOFF_task_thread + AOFF_thread_uwinmask], tmp2;  \
  91         orcc    %g0, tmp2, %g0;                                         \
  92         add     tmp1, 1, tmp1;                                          \
  93         bne     98b;                                                    \
  94          save   %sp, -64, %sp;                                          \
  95 99:     subcc   tmp1, 1, tmp1;                                          \
  96         bne     99b;                                                    \
  97          restore %g0, %g0, %g0;
  98
  99 #ifndef __ASSEMBLY__
 100
 101 /* Accessing the MMU control register. */
 102 extern __inline__ unsigned int srmmu_get_mmureg(void)
 103 {
 104         unsigned int retval;
 105         __asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
 106                              "=r" (retval) :
 107                              "i" (ASI_M_MMUREGS));
 108         return retval;
 109 }
 110
 111 extern __inline__ void srmmu_set_mmureg(unsigned long regval)
 112 {
 113         __asm__ __volatile__("sta %0, [%%g0] %1\n\t" : :
 114                              "r" (regval), "i" (ASI_M_MMUREGS) : "memory");
 115
 116 }
 117
 118 extern __inline__ void srmmu_set_ctable_ptr(unsigned long paddr)
 119 {
 120         paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
 121         __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
 122                              "r" (paddr), "r" (SRMMU_CTXTBL_PTR),
 123                              "i" (ASI_M_MMUREGS) :
 124                              "memory");
 125 }
 126
 127 extern __inline__ unsigned long srmmu_get_ctable_ptr(void)
 128 {
 129         unsigned int retval;
 130
 131         __asm__ __volatile__("lda [%1] %2, %0\n\t" :
 132                              "=r" (retval) :
 133                              "r" (SRMMU_CTXTBL_PTR),
 134                              "i" (ASI_M_MMUREGS));
 135         return (retval & SRMMU_CTX_PMASK) << 4;
 136 }
 137
 138 extern __inline__ void srmmu_set_context(int context)
 139 {
 140         __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
 141                              "r" (context), "r" (SRMMU_CTX_REG),
 142                              "i" (ASI_M_MMUREGS) : "memory");
 143 }
 144
 145 extern __inline__ int srmmu_get_context(void)
 146 {
 147         register int retval;
 148         __asm__ __volatile__("lda [%1] %2, %0\n\t" :
 149                              "=r" (retval) :
 150                              "r" (SRMMU_CTX_REG),
 151                              "i" (ASI_M_MMUREGS));
 152         return retval;
 153 }
 154
 155 extern __inline__ unsigned int srmmu_get_fstatus(void)
 156 {
 157         unsigned int retval;
 158
 159         __asm__ __volatile__("lda [%1] %2, %0\n\t" :
 160                              "=r" (retval) :
 161                              "r" (SRMMU_FAULT_STATUS), "i" (ASI_M_MMUREGS));
 162         return retval;
 163 }
 164
 165 extern __inline__ unsigned int srmmu_get_faddr(void)
 166 {
 167         unsigned int retval;
 168
 169         __asm__ __volatile__("lda [%1] %2, %0\n\t" :
 170                              "=r" (retval) :
 171                              "r" (SRMMU_FAULT_ADDR), "i" (ASI_M_MMUREGS));
 172         return retval;
 173 }
 174
 175 /* This is guaranteed on all SRMMU's. */
 176 extern __inline__ void srmmu_flush_whole_tlb(void)
 177 {
 178         __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
 179                              "r" (0x400),        /* Flush entire TLB!! */
 180                              "i" (ASI_M_FLUSH_PROBE) : "memory");
 181
 182 }
 183
 184 /* These flush types are not available on all chips... */
 185 extern __inline__ void srmmu_flush_tlb_ctx(void)
 186 {
 187         __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
 188                              "r" (0x300),        /* Flush TLB ctx.. */
 189                              "i" (ASI_M_FLUSH_PROBE) : "memory");
 190
 191 }
 192
 193 extern __inline__ void srmmu_flush_tlb_region(unsigned long addr)
 194 {
 195         addr &= SRMMU_PGDIR_MASK;
 196         __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
 197                              "r" (addr | 0x200), /* Flush TLB region.. */
 198                              "i" (ASI_M_FLUSH_PROBE) : "memory");
 199
 200 }
 201
 202
 203 extern __inline__ void srmmu_flush_tlb_segment(unsigned long addr)
 204 {
 205         addr &= SRMMU_PMD_MASK;
 206         __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
 207                              "r" (addr | 0x100), /* Flush TLB segment.. */
 208                              "i" (ASI_M_FLUSH_PROBE) : "memory");
 209
 210 }
 211
 212 extern __inline__ void srmmu_flush_tlb_page(unsigned long page)
 213 {
 214         page &= PAGE_MASK;
 215         __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
 216                              "r" (page),        /* Flush TLB page.. */
 217                              "i" (ASI_M_FLUSH_PROBE) : "memory");
 218
 219 }
 220
 221 extern __inline__ unsigned long srmmu_hwprobe(unsigned long vaddr)
 222 {
 223         unsigned long retval;
 224
 225         vaddr &= PAGE_MASK;
 226         __asm__ __volatile__("lda [%1] %2, %0\n\t" :
 227                              "=r" (retval) :
 228                              "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
 229
 230         return retval;
 231 }
 232
 233 extern __inline__ int
 234 srmmu_get_pte (unsigned long addr)
 235 {
 236         register unsigned long entry;
 237
 238         __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" :
 239                                 "=r" (entry):
 240                                 "r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE));
 241         return entry;
 242 }
 243
 244 extern unsigned long (*srmmu_read_physical)(unsigned long paddr);
 245 extern void (*srmmu_write_physical)(unsigned long paddr, unsigned long word);
 246
 247 #endif /* !(__ASSEMBLY__) */
 248
 249 #endif /* !(_SPARC_PGTSRMMU_H) */