drivers/ieee1394/ohci1394.h

   1 /*
   2  * ohci1394.h - driver for OHCI 1394 boards
   3  * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
   4  *                        Gord Peters <GordPeters@smarttech.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #ifndef _OHCI1394_H
  22 #define _OHCI1394_H
  23
  24 #include "ieee1394_types.h"
  25
  26 #define IEEE1394_USE_BOTTOM_HALVES 0
  27
  28 #define OHCI1394_DRIVER_NAME      "ohci1394"
  29
  30 #ifndef PCI_DEVICE_ID_TI_OHCI1394_LV22
  31 #define PCI_DEVICE_ID_TI_OHCI1394_LV22 0x8009
  32 #endif
  33
  34 #ifndef PCI_DEVICE_ID_TI_OHCI1394_LV23
  35 #define PCI_DEVICE_ID_TI_OHCI1394_LV23 0x8019
  36 #endif
  37
  38 #ifndef PCI_DEVICE_ID_TI_OHCI1394_LV26
  39 #define PCI_DEVICE_ID_TI_OHCI1394_LV26 0x8020
  40 #endif
  41
  42 #ifndef PCI_DEVICE_ID_VIA_OHCI1394
  43 #define PCI_DEVICE_ID_VIA_OHCI1394 0x3044
  44 #endif
  45
  46 #ifndef PCI_VENDOR_ID_SONY
  47 #define PCI_VENDOR_ID_SONY 0x104d
  48 #endif
  49
  50 #ifndef PCI_DEVICE_ID_SONY_CXD3222
  51 #define PCI_DEVICE_ID_SONY_CXD3222 0x8039
  52 #endif
  53
  54 #ifndef PCI_DEVICE_ID_NEC_1394
  55 #define PCI_DEVICE_ID_NEC_1394 0x00cd
  56 #endif
  57
  58 #ifndef PCI_DEVICE_ID_NEC_UPD72862
  59 #define PCI_DEVICE_ID_NEC_UPD72862      0x0063
  60 #endif
  61
  62 #ifndef PCI_DEVICE_ID_NEC_UPD72870
  63 #define PCI_DEVICE_ID_NEC_UPD72870      0x00cd
  64 #endif
  65
  66 #ifndef PCI_DEVICE_ID_NEC_UPD72871
  67 #define PCI_DEVICE_ID_NEC_UPD72871      0x00ce
  68 #endif
  69
  70 #ifndef PCI_DEVICE_ID_APPLE_UNI_N_FW
  71 #define PCI_DEVICE_ID_APPLE_UNI_N_FW    0x0018
  72 #endif
  73
  74 #ifndef PCI_DEVICE_ID_ALI_OHCI1394_M5251
  75 #define PCI_DEVICE_ID_ALI_OHCI1394_M5251 0x5251
  76 #endif
  77
  78 #ifndef PCI_VENDOR_ID_LUCENT
  79 #define PCI_VENDOR_ID_LUCENT 0x11c1
  80 #endif
  81
  82 #ifndef PCI_DEVICE_ID_LUCENT_FW323
  83 #define PCI_DEVICE_ID_LUCENT_FW323 0x5811
  84 #endif
  85
  86 #define MAX_OHCI1394_CARDS        4
  87
  88 #define OHCI1394_MAX_AT_REQ_RETRIES       0x2
  89 #define OHCI1394_MAX_AT_RESP_RETRIES      0x2
  90 #define OHCI1394_MAX_PHYS_RESP_RETRIES    0x8
  91 #define OHCI1394_MAX_SELF_ID_ERRORS       16
  92
  93 #define AR_REQ_NUM_DESC                   4 /* number of AR req descriptors */
  94 #define AR_REQ_BUF_SIZE           PAGE_SIZE /* size of AR req buffers */
  95 #define AR_REQ_SPLIT_BUF_SIZE     PAGE_SIZE /* split packet buffer */
  96
  97 #define AR_RESP_NUM_DESC                  4 /* number of AR resp descriptors */
  98 #define AR_RESP_BUF_SIZE          PAGE_SIZE /* size of AR resp buffers */
  99 #define AR_RESP_SPLIT_BUF_SIZE    PAGE_SIZE /* split packet buffer */
 100
 101 #define IR_NUM_DESC                      16 /* number of IR descriptors */
 102 #define IR_BUF_SIZE               PAGE_SIZE /* 4096 bytes/buffer */
 103 #define IR_SPLIT_BUF_SIZE         PAGE_SIZE /* split packet buffer */
 104
 105 #define AT_REQ_NUM_DESC                  32 /* number of AT req descriptors */
 106 #define AT_RESP_NUM_DESC                 32 /* number of AT resp descriptors */
 107
 108 struct dma_cmd {
 109         u32 control;
 110         u32 address;
 111         u32 branchAddress;
 112         u32 status;
 113 };
 114
 115 /*
 116  * FIXME:
 117  * It is important that a single at_dma_prg does not cross a page boundary
 118  * The proper way to do it would be to do the check dynamically as the
 119  * programs are inserted into the AT fifo.
 120  */
 121 struct at_dma_prg {
 122         struct dma_cmd begin;
 123         quadlet_t data[4];
 124         struct dma_cmd end;
 125         quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
 126 };
 127
 128 /* DMA receive context */
 129 struct dma_rcv_ctx {
 130         void *ohci;
 131         int ctx;
 132         unsigned int num_desc;
 133         unsigned int buf_size;
 134         unsigned int split_buf_size;
 135
 136         /* dma block descriptors */
 137         struct dma_cmd **prg_cpu;
 138         dma_addr_t *prg_bus;
 139
 140         /* dma buffers */
 141         quadlet_t **buf_cpu;
 142         dma_addr_t *buf_bus;
 143
 144         unsigned int buf_ind;
 145         unsigned int buf_offset;
 146         quadlet_t *spb;
 147         spinlock_t lock;
 148         struct tq_struct task;
 149         int ctrlClear;
 150         int ctrlSet;
 151         int cmdPtr;
 152 };
 153
 154 /* DMA transmit context */
 155 struct dma_trm_ctx {
 156         void *ohci;
 157         int ctx;
 158         unsigned int num_desc;
 159
 160         /* dma block descriptors */
 161         struct at_dma_prg **prg_cpu;
 162         dma_addr_t *prg_bus;
 163
 164         unsigned int prg_ind;
 165         unsigned int sent_ind;
 166         int free_prgs;
 167         quadlet_t *branchAddrPtr;
 168
 169         /* list of packets inserted in the AT FIFO */
 170         struct hpsb_packet *fifo_first;
 171         struct hpsb_packet *fifo_last;
 172
 173         /* list of pending packets to be inserted in the AT FIFO */
 174         struct hpsb_packet *pending_first;
 175         struct hpsb_packet *pending_last;
 176
 177         spinlock_t lock;
 178         struct tq_struct task;
 179         int ctrlClear;
 180         int ctrlSet;
 181         int cmdPtr;
 182 };
 183
 184 /* video device template */
 185 struct video_template {
 186         void (*irq_handler) (int card, quadlet_t isoRecvEvent,
 187                              quadlet_t isoXmitEvent);
 188 };
 189
 190
 191 struct ti_ohci {
 192         int id; /* sequential card number */
 193
 194         struct pci_dev *dev;
 195
 196         u32 state;
 197
 198         /* remapped memory spaces */
 199         void *registers;
 200
 201         /* dma buffer for self-id packets */
 202         quadlet_t *selfid_buf_cpu;
 203         dma_addr_t selfid_buf_bus;
 204
 205         /* buffer for csr config rom */
 206         quadlet_t *csr_config_rom_cpu;
 207         dma_addr_t csr_config_rom_bus;
 208
 209         unsigned int max_packet_size;
 210
 211         /* async receive */
 212         struct dma_rcv_ctx *ar_resp_context;
 213         struct dma_rcv_ctx *ar_req_context;
 214
 215         /* async transmit */
 216         struct dma_trm_ctx *at_resp_context;
 217         struct dma_trm_ctx *at_req_context;
 218
 219         /* iso receive */
 220         struct dma_rcv_ctx *ir_context;
 221         u64 IR_channel_usage;
 222         spinlock_t IR_channel_lock;
 223         int nb_iso_rcv_ctx;
 224
 225         /* iso transmit */
 226         int nb_iso_xmit_ctx;
 227
 228         /* IEEE-1394 part follows */
 229         struct hpsb_host *host;
 230
 231         int phyid, isroot;
 232
 233         spinlock_t phy_reg_lock;
 234
 235         int self_id_errors;
 236         int NumBusResets;
 237
 238         /* video device */
 239         struct video_template *video_tmpl;
 240 };
 241
 242 inline static int cross_bound(unsigned long addr, unsigned int size)
 243 {
 244         int cross=0;
 245         if (size>PAGE_SIZE) {
 246                 cross = size/PAGE_SIZE;
 247                 size -= cross*PAGE_SIZE;
 248         }
 249         if ((PAGE_SIZE-addr%PAGE_SIZE)<size)
 250                 cross++;
 251         return cross;
 252 }
 253
 254 /*
 255  * Register read and write helper functions.
 256  */
 257 inline static void reg_write(const struct ti_ohci *ohci, int offset, u32 data)
 258 {
 259         writel(data, ohci->registers + offset);
 260 }
 261
 262 inline static u32 reg_read(const struct ti_ohci *ohci, int offset)
 263 {
 264         return readl(ohci->registers + offset);
 265 }
 266
 267 /* This structure is not properly initialized ... it is taken from
 268    the lynx_csr_rom written by Andreas ... Some fields in the root
 269    directory and the module dependent info needs to be modified
 270    I do not have the proper doc */
 271 quadlet_t ohci_csr_rom[] = {
 272         /* bus info block */
 273         0x04040000, /* info/CRC length, CRC */
 274         0x31333934, /* 1394 magic number */
 275         0xf07da002, /* cyc_clk_acc = 125us, max_rec = 1024 */
 276         0x00000000, /* vendor ID, chip ID high (written from card info) */
 277         0x00000000, /* chip ID low (written from card info) */
 278         /* root directory - FIXME */
 279         0x00090000, /* CRC length, CRC */
 280         0x03080028, /* vendor ID (Texas Instr.) */
 281         0x81000009, /* offset to textual ID */
 282         0x0c000200, /* node capabilities */
 283         0x8d00000e, /* offset to unique ID */
 284         0xc7000010, /* offset to module independent info */
 285         0x04000000, /* module hardware version */
 286         0x81000026, /* offset to textual ID */
 287         0x09000000, /* node hardware version */
 288         0x81000026, /* offset to textual ID */
 289         /* module vendor ID textual */
 290         0x00080000, /* CRC length, CRC */
 291         0x00000000,
 292         0x00000000,
 293         0x54455841, /* "Texas Instruments" */
 294         0x5320494e,
 295         0x53545255,
 296         0x4d454e54,
 297         0x53000000,
 298         /* node unique ID leaf */
 299         0x00020000, /* CRC length, CRC */
 300         0x08002856, /* vendor ID, chip ID high */
 301         0x0000083E, /* chip ID low */
 302         /* module dependent info - FIXME */
 303         0x00060000, /* CRC length, CRC */
 304         0xb8000006, /* ??? offset to module textual ID */
 305         0x81000004, /* ??? textual descriptor */
 306         0x00000000, /* SRAM size */
 307         0x00000000, /* AUXRAM size */
 308         0x00000000, /* AUX device */
 309         /* module textual ID */
 310         0x00050000, /* CRC length, CRC */
 311         0x00000000,
 312         0x00000000,
 313         0x54534231, /* "TSB12LV22" */
 314         0x324c5632,
 315         0x32000000,
 316         /* part number */
 317         0x00060000, /* CRC length, CRC */
 318         0x00000000,
 319         0x00000000,
 320         0x39383036, /* "9806000-0001" */
 321         0x3030342d,
 322         0x30303431,
 323         0x20000001,
 324         /* module hardware version textual */
 325         0x00050000, /* CRC length, CRC */
 326         0x00000000,
 327         0x00000000,
 328         0x5453424b, /* "TSBKOHCI403" */
 329         0x4f484349,
 330         0x34303300,
 331         /* node hardware version textual */
 332         0x00050000, /* CRC length, CRC */
 333         0x00000000,
 334         0x00000000,
 335         0x54534234, /* "TSB41LV03" */
 336         0x314c5630,
 337         0x33000000
 338 };
 339
 340
 341 /* 2 KiloBytes of register space */
 342 #define OHCI1394_REGISTER_SIZE                0x800
 343
 344 /* register map */
 345 #define OHCI1394_Version                      0x000
 346 #define OHCI1394_GUID_ROM                     0x004
 347 #define OHCI1394_ATRetries                    0x008
 348 #define OHCI1394_CSRData                      0x00C
 349 #define OHCI1394_CSRCompareData               0x010
 350 #define OHCI1394_CSRControl                   0x014
 351 #define OHCI1394_ConfigROMhdr                 0x018
 352 #define OHCI1394_BusID                        0x01C
 353 #define OHCI1394_BusOptions                   0x020
 354 #define OHCI1394_GUIDHi                       0x024
 355 #define OHCI1394_GUIDLo                       0x028
 356 #define OHCI1394_ConfigROMmap                 0x034
 357 #define OHCI1394_PostedWriteAddressLo         0x038
 358 #define OHCI1394_PostedWriteAddressHi         0x03C
 359 #define OHCI1394_VendorID                     0x040
 360 #define OHCI1394_HCControlSet                 0x050
 361 #define OHCI1394_HCControlClear               0x054
 362 #define OHCI1394_SelfIDBuffer                 0x064
 363 #define OHCI1394_SelfIDCount                  0x068
 364 #define OHCI1394_IRMultiChanMaskHiSet         0x070
 365 #define OHCI1394_IRMultiChanMaskHiClear       0x074
 366 #define OHCI1394_IRMultiChanMaskLoSet         0x078
 367 #define OHCI1394_IRMultiChanMaskLoClear       0x07C
 368 #define OHCI1394_IntEventSet                  0x080
 369 #define OHCI1394_IntEventClear                0x084
 370 #define OHCI1394_IntMaskSet                   0x088
 371 #define OHCI1394_IntMaskClear                 0x08C
 372 #define OHCI1394_IsoXmitIntEventSet           0x090
 373 #define OHCI1394_IsoXmitIntEventClear         0x094
 374 #define OHCI1394_IsoXmitIntMaskSet            0x098
 375 #define OHCI1394_IsoXmitIntMaskClear          0x09C
 376 #define OHCI1394_IsoRecvIntEventSet           0x0A0
 377 #define OHCI1394_IsoRecvIntEventClear         0x0A4
 378 #define OHCI1394_IsoRecvIntMaskSet            0x0A8
 379 #define OHCI1394_IsoRecvIntMaskClear          0x0AC
 380 #define OHCI1394_FairnessControl              0x0DC
 381 #define OHCI1394_LinkControlSet               0x0E0
 382 #define OHCI1394_LinkControlClear             0x0E4
 383 #define OHCI1394_NodeID                       0x0E8
 384 #define OHCI1394_PhyControl                   0x0EC
 385 #define OHCI1394_IsochronousCycleTimer        0x0F0
 386 #define OHCI1394_AsReqFilterHiSet             0x100
 387 #define OHCI1394_AsReqFilterHiClear           0x104
 388 #define OHCI1394_AsReqFilterLoSet             0x108
 389 #define OHCI1394_AsReqFilterLoClear           0x10C
 390 #define OHCI1394_PhyReqFilterHiSet            0x110
 391 #define OHCI1394_PhyReqFilterHiClear          0x114
 392 #define OHCI1394_PhyReqFilterLoSet            0x118
 393 #define OHCI1394_PhyReqFilterLoClear          0x11C
 394 #define OHCI1394_PhyUpperBound                0x120
 395 #define OHCI1394_AsReqTrContextControlSet     0x180
 396 #define OHCI1394_AsReqTrContextControlClear   0x184
 397 #define OHCI1394_AsReqTrCommandPtr            0x18C
 398 #define OHCI1394_AsRspTrContextControlSet     0x1A0
 399 #define OHCI1394_AsRspTrContextControlClear   0x1A4
 400 #define OHCI1394_AsRspTrCommandPtr            0x1AC
 401 #define OHCI1394_AsReqRcvContextControlSet    0x1C0
 402 #define OHCI1394_AsReqRcvContextControlClear  0x1C4
 403 #define OHCI1394_AsReqRcvCommandPtr           0x1CC
 404 #define OHCI1394_AsRspRcvContextControlSet    0x1E0
 405 #define OHCI1394_AsRspRcvContextControlClear  0x1E4
 406 #define OHCI1394_AsRspRcvCommandPtr           0x1EC
 407
 408 /* Isochronous transmit registers */
 409 /* Add (32 * n) for context n */
 410 #define OHCI1394_IsoXmitContextControlSet     0x200
 411 #define OHCI1394_IsoXmitContextControlClear   0x204
 412 #define OHCI1394_IsoXmitCommandPtr            0x20C
 413
 414 /* Isochronous receive registers */
 415 /* Add (32 * n) for context n */
 416 #define OHCI1394_IsoRcvContextControlSet      0x400
 417 #define OHCI1394_IsoRcvContextControlClear    0x404
 418 #define OHCI1394_IsoRcvCommandPtr             0x40C
 419 #define OHCI1394_IsoRcvContextMatch           0x410
 420
 421 /* Interrupts Mask/Events */
 422
 423 #define OHCI1394_reqTxComplete           0x00000001
 424 #define OHCI1394_respTxComplete          0x00000002
 425 #define OHCI1394_ARRQ                    0x00000004
 426 #define OHCI1394_ARRS                    0x00000008
 427 #define OHCI1394_RQPkt                   0x00000010
 428 #define OHCI1394_RSPkt                   0x00000020
 429 #define OHCI1394_isochTx                 0x00000040
 430 #define OHCI1394_isochRx                 0x00000080
 431 #define OHCI1394_postedWriteErr          0x00000100
 432 #define OHCI1394_lockRespErr             0x00000200
 433 #define OHCI1394_selfIDComplete          0x00010000
 434 #define OHCI1394_busReset                0x00020000
 435 #define OHCI1394_phy                     0x00080000
 436 #define OHCI1394_cycleSynch              0x00100000
 437 #define OHCI1394_cycle64Seconds          0x00200000
 438 #define OHCI1394_cycleLost               0x00400000
 439 #define OHCI1394_cycleInconsistent       0x00800000
 440 #define OHCI1394_unrecoverableError      0x01000000
 441 #define OHCI1394_cycleTooLong            0x02000000
 442 #define OHCI1394_phyRegRcvd              0x04000000
 443 #define OHCI1394_masterIntEnable         0x80000000
 444
 445 #define OUTPUT_MORE                      0x00000000
 446 #define OUTPUT_MORE_IMMEDIATE            0x02000000
 447 #define OUTPUT_LAST                      0x103c0000
 448 #define OUTPUT_LAST_IMMEDIATE            0x123c0000
 449
 450 #define DMA_SPEED_100                    0x0
 451 #define DMA_SPEED_200                    0x1
 452 #define DMA_SPEED_400                    0x2
 453
 454 void ohci1394_stop_context(struct ti_ohci *ohci, int reg, char *msg);
 455 struct ti_ohci *ohci1394_get_struct(int card_num);
 456 int ohci1394_register_video(struct ti_ohci *ohci,
 457                             struct video_template *tmpl);
 458 void ohci1394_unregister_video(struct ti_ohci *ohci,
 459                                struct video_template *tmpl);
 460
 461 #endif
 462