arch/parisc/kernel/pci.c

   1 /* $Id: pci.c,v 1.6 2000/01/29 00:12:05 grundler Exp $
   2  *
   3  * This file is subject to the terms and conditions of the GNU General Public
   4  * License.  See the file "COPYING" in the main directory of this archive
   5  * for more details.
   6  *
   7  * Copyright (C) 1997, 1998 Ralf Baechle
   8  * Copyright (C) 1999 SuSE GmbH
   9  * Copyright (C) 1999 Hewlett-Packard Company
  10  * Copyright (C) 1999, 2000 Grant Grundler
  11  */
  12 #include <linux/config.h>
  13 #include <linux/types.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>         /* for __init and __devinit */
  16 #include <linux/pci.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/string.h>       /* for memcpy() */
  19
  20 #include <asm/system.h>
  21
  22 #ifdef CONFIG_PCI
  23
  24 #undef DEBUG_RESOURCES
  25
  26 #ifdef DEBUG_RESOURCES
  27 #define DBG_RES(x...)   printk(x)
  28 #else
  29 #define DBG_RES(x...)
  30 #endif
  31
  32 /* To be used as: mdelay(pci_post_reset_delay);
  33 **
  34 ** post_reset is the time the kernel should stall to prevent anyone from
  35 ** accessing the PCI bus once #RESET is de-asserted.
  36 ** PCI spec somewhere says 1 second but with multi-PCI bus systems,
  37 ** this makes the boot time much longer than necessary.
  38 ** 20ms seems to work for all the HP PCI implementations to date.
  39 */
  40 int pci_post_reset_delay = 50;
  41
  42 struct pci_port_ops *pci_port;
  43 struct pci_bios_ops *pci_bios;
  44
  45 struct pci_hba_data *hba_list = NULL;
  46 int hba_count = 0;
  47
  48 /*
  49 ** parisc_pci_hba used by pci_port->in/out() ops to lookup bus data.
  50 */
  51 #define PCI_HBA_MAX 32
  52 static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX];
  53
  54
  55 /********************************************************************
  56 **
  57 ** I/O port space support
  58 **
  59 *********************************************************************/
  60
  61 #define PCI_PORT_HBA(a) ((a)>>16)
  62 #define PCI_PORT_ADDR(a) ((a) & 0xffffUL)
  63
  64 /* KLUGE : inb needs to be defined differently for PCI devices than
  65 ** for other bus interfaces. Doing this at runtime sucks but is the
  66 ** only way one driver binary can support devices on different bus types.
  67 **
  68 */
  69
  70 #define PCI_PORT_IN(type, size) \
  71 u##size in##type (int addr) \
  72 { \
  73         int b = PCI_PORT_HBA(addr); \
  74         u##size d = (u##size) -1; \
  75         ASSERT(pci_port); /* make sure services are defined */ \
  76         ASSERT(parisc_pci_hba[b]); /* make sure ioaddr are "fixed up" */ \
  77         if (parisc_pci_hba[b] == NULL) { \
  78                 printk(KERN_WARNING "\nPCI Host Bus Adapter %d not registered. in" #size "(0x%x) returning -1\n", b, addr); \
  79         } else { \
  80                 d = pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \
  81         } \
  82         return d; \
  83 }
  84
  85 PCI_PORT_IN(b,  8)
  86 PCI_PORT_IN(w, 16)
  87 PCI_PORT_IN(l, 32)
  88
  89
  90 #define PCI_PORT_OUT(type, size) \
  91 void out##type (u##size d, int addr) \
  92 { \
  93         int b = PCI_PORT_HBA(addr); \
  94         ASSERT(pci_port); \
  95         pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \
  96 }
  97
  98 PCI_PORT_OUT(b,  8)
  99 PCI_PORT_OUT(w, 16)
 100 PCI_PORT_OUT(l, 32)
 101
 102
 103
 104 /*
 105  * BIOS32 replacement.
 106  */
 107 void pcibios_init(void)
 108 {
 109         ASSERT(pci_bios != NULL);
 110
 111         if (pci_bios)
 112         {
 113                 if (pci_bios->init) {
 114                         (*pci_bios->init)();
 115                 } else {
 116                         printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
 117                 }
 118         }
 119 }
 120
 121
 122 /* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */
 123 void pcibios_fixup_bus(struct pci_bus *bus)
 124 {
 125         ASSERT(pci_bios != NULL);
 126
 127         /* If this is a bridge, get the current bases */
 128         if (bus->self) {
 129                 pci_read_bridge_bases(bus);
 130         }
 131
 132         if (pci_bios) {
 133                 if (pci_bios->fixup_bus) {
 134                         (*pci_bios->fixup_bus)(bus);
 135                 } else {
 136                         printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n");
 137                 }
 138         }
 139 }
 140
 141
 142 char *pcibios_setup(char *str)
 143 {
 144         return str;
 145 }
 146
 147 #endif /* defined(CONFIG_PCI) */
 148
 149
 150
 151 /* -------------------------------------------------------------------
 152 ** linux-2.4: NEW STUFF
 153 ** --------------------
 154 */
 155
 156 /*
 157 ** Used in drivers/pci/quirks.c
 158 */
 159 struct pci_fixup pcibios_fixups[] = { {0} };
 160
 161
 162 /*
 163 ** called by drivers/pci/setup.c:pdev_fixup_irq()
 164 */
 165 void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
 166 {
 167 /*
 168 ** updates IRQ_LINE cfg register to reflect PCI-PCI bridge skewing.
 169 **
 170 ** Calling path for Alpha is:
 171 **  alpha/kernel/pci.c:common_init_pci(swizzle_func, pci_map_irq_func )
 172 **      drivers/pci/setup.c:pci_fixup_irqs()
 173 **          drivers/pci/setup.c:pci_fixup_irq() (for each PCI device)
 174 **              invoke swizzle and map functions
 175 **              alpha/kernel/pci.c:pcibios_update_irq()
 176 **
 177 ** Don't need this for PA legacy PDC systems.
 178 **
 179 ** On PAT PDC systems, We only support one "swizzle" for any number
 180 ** of PCI-PCI bridges deep. That's how bit3 PCI expansion chassis
 181 ** are implemented. The IRQ lines are "skewed" for all devices but
 182 ** *NOT* routed through the PCI-PCI bridge. Ie any device "0" will
 183 ** share an IRQ line. Legacy PDC is expecting this IRQ line routing
 184 ** as well.
 185 **
 186 ** Unfortunately, PCI spec allows the IRQ lines to be routed
 187 ** around the PCI bridge as long as the IRQ lines are skewed
 188 ** based on the device number...<sigh>...
 189 **
 190 ** Lastly, dino.c might be able to use pci_fixup_irq() to
 191 ** support RS-232 and PS/2 children. Not sure how but it's
 192 ** something to think about.
 193 */
 194 }
 195
 196
 197 /* ------------------------------------
 198 **
 199 ** Program one BAR in PCI config space.
 200 **
 201 ** ------------------------------------
 202 ** PAT PDC systems need this routine. PA legacy PDC does not.
 203 **
 204 ** Used by alpha/arm:
 205 ** alpha/kernel/pci.c:common_init_pci()
 206 ** (or arm/kernel/pci.c:pcibios_init())
 207 **    drivers/pci/setup.c:pci_assign_unassigned_resources()
 208 **        drivers/pci/setup.c:pdev_assign_unassigned_resources()
 209 **            arch/<foo>/kernel/pci.c:pcibios_update_resource()
 210 **
 211 ** When BAR's are configured by linux, this routine
 212 ** will update configuration space with the "normalized"
 213 ** address. "root" indicates where the range starts and res
 214 ** is some portion of that range.
 215 **
 216 ** For all PA-RISC systems except V-class, root->start would be zero.
 217 **
 218 ** PAT PDC can tell us which MMIO ranges are available or already in use.
 219 ** I/O port space and such are not memory mapped anyway for PA-Risc.
 220 */
 221 void __devinit
 222 pcibios_update_resource(
 223         struct pci_dev *dev,
 224         struct resource *root,
 225         struct resource *res,
 226         int barnum
 227         )
 228 {
 229         int where;
 230         u32 barval = 0;
 231
 232         DBG_RES("pcibios_update_resource(%s, ..., %d) [%lx,%lx]/%x\n",
 233                 dev->slot_name,
 234                 barnum, res->start, res->end, (int) res->flags);
 235
 236         if (barnum >= PCI_BRIDGE_RESOURCES) {
 237                 /* handled in pbus_set_ranges_data() */
 238                 return;
 239         }
 240
 241         if (barnum == PCI_ROM_RESOURCE) {
 242                 where = PCI_ROM_ADDRESS;
 243         } else {
 244                 /* 0-5  standard PCI "regions" */
 245                 where = PCI_BASE_ADDRESS_0 + (barnum * 4);
 246         }
 247
 248         if (res->flags & IORESOURCE_IO) {
 249                 barval = PCI_PORT_ADDR(res->start);
 250         } else if (res->flags & IORESOURCE_MEM) {
 251                 /* This should work for VCLASS too */
 252                 barval = res->start & 0xffffffffUL;
 253         } else {
 254                 panic("pcibios_update_resource() WTF? flags not IO or MEM");
 255         }
 256
 257         pci_write_config_dword(dev, where, barval);
 258
 259 /* XXX FIXME - Elroy does support 64-bit (dual cycle) addressing.
 260 ** But at least one device (Symbios 53c896) which has 64-bit BAR
 261 ** doesn't actually work right with dual cycle addresses.
 262 ** So ignore the whole mess for now.
 263 */
 264
 265         if ((res->flags & (PCI_BASE_ADDRESS_SPACE
 266                            | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
 267             == (PCI_BASE_ADDRESS_SPACE_MEMORY
 268                 | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
 269                 pci_write_config_dword(dev, where+4, 0);
 270                 printk(KERN_WARNING "PCI: dev %s type 64-bit\n", dev->name);
 271         }
 272 }
 273
 274 /*
 275 ** Called by pci_set_master() - a driver interface.
 276 **
 277 ** Legacy PDC guarantees to set:
 278 **      Map Memory BAR's into PA IO space.
 279 **      Map Expansion ROM BAR into one common PA IO space per bus.
 280 **      Map IO BAR's into PCI IO space.
 281 **      Command (see below)
 282 **      Cache Line Size
 283 **      Latency Timer
 284 **      Interrupt Line
 285 **      PPB: secondary latency timer, io/mmio base/limit,
 286 **              bus numbers, bridge control
 287 **
 288 */
 289 void
 290 pcibios_set_master(struct pci_dev *dev)
 291 {
 292         u8 lat;
 293         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 294         if (lat >= 16) return;
 295
 296         /*
 297         ** HP generally has fewer devices on the bus than other architectures.
 298         */
 299         printk("PCIBIOS: Setting latency timer of %s to 128\n", dev->slot_name);
 300         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
 301 }
 302
 303
 304 /*
 305 ** called by drivers/pci/setup-res.c:pbus_set_ranges().
 306 */
 307 void pcibios_fixup_pbus_ranges(
 308         struct pci_bus *bus,
 309         struct pbus_set_ranges_data *ranges
 310         )
 311 {
 312         /*
 313         ** I/O space may see busnumbers here. Something
 314         ** in the form of 0xbbxxxx where bb is the bus num
 315         ** and xxxx is the I/O port space address.
 316         ** Remaining address translation are done in the
 317         ** PCI Host adapter specific code - ie dino_out8.
 318         */
 319         ranges->io_start = PCI_PORT_ADDR(ranges->io_start);
 320         ranges->io_end   = PCI_PORT_ADDR(ranges->io_end);
 321
 322         DBG_RES("pcibios_fixup_pbus_ranges(%02x, [%lx,%lx %lx,%lx])\n", bus->number,
 323                 ranges->io_start, ranges->io_end,
 324                 ranges->mem_start, ranges->mem_end);
 325 }
 326
 327 #define MAX(val1, val2)   ((val1) > (val2) ? (val1) : (val2))
 328
 329
 330 /*
 331 ** pcibios align resources() is called everytime generic PCI code
 332 ** wants to generate a new address. The process of looking for
 333 ** an available address, each candidate is first "aligned" and
 334 ** then checked if the resource is available until a match is found.
 335 **
 336 ** Since we are just checking candidates, don't use any fields other
 337 ** than res->start.
 338 */
 339 void __devinit
 340 pcibios_align_resource(void *data, struct resource *res, unsigned long size)
 341 {
 342         unsigned long mask, align;
 343
 344         DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx)\n",
 345                 ((struct pci_dev *) data)->slot_name,
 346                 res->parent, res->start, res->end, (int) res->flags, size);
 347
 348         /* has resource already been aligned/assigned? */
 349         if (res->parent)
 350                 return;
 351
 352         /* If it's not IO, then it's gotta be MEM */
 353         align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
 354
 355         /* Align to largest of MIN or input size */
 356         mask = MAX(size, align) - 1;
 357         res->start += mask;
 358         res->start &= ~mask;
 359
 360         /*
 361         ** WARNING : caller is expected to update "end" field.
 362         ** We can't since it might really represent the *size*.
 363         ** The difference is "end = start + size" vs "end += size".
 364         */
 365 }
 366
 367
 368 #define ROUND_UP(x, a)          (((x) + (a) - 1) & ~((a) - 1))
 369
 370 void __devinit
 371 pcibios_size_bridge(struct pci_bus *bus, struct pbus_set_ranges_data *outer)
 372 {
 373         struct pbus_set_ranges_data inner;
 374         struct pci_dev *dev;
 375         struct pci_dev *bridge = bus->self;
 376         struct list_head *ln;
 377
 378         /* set reasonable default "window" for pcibios_align_resource */
 379         inner.io_start  = inner.io_end  = 0;
 380         inner.mem_start = inner.mem_end = 0;
 381
 382         /* Collect information about how our direct children are layed out. */
 383         for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
 384                 int i;
 385                 dev = pci_dev_b(ln);
 386
 387                 /* Skip bridges here - we'll catch them below */
 388                 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
 389                         continue;
 390
 391                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 392                         struct resource res;
 393                         unsigned long size;
 394
 395                         if (dev->resource[i].flags == 0)
 396                                 continue;
 397
 398                         memcpy(&res, &dev->resource[i], sizeof(res));
 399                         size = res.end - res.start + 1;
 400
 401                         if (res.flags & IORESOURCE_IO) {
 402                                 res.start = inner.io_end;
 403                                 pcibios_align_resource(dev, &res, size);
 404                                 inner.io_end += res.start + size;
 405                         } else if (res.flags & IORESOURCE_MEM) {
 406                                 res.start = inner.mem_end;
 407                                 pcibios_align_resource(dev, &res, size);
 408                                 inner.mem_end = res.start + size;
 409                         }
 410
 411                 DBG_RES("    %s  inner size %lx/%x IO %lx MEM %lx\n",
 412                         dev->slot_name,
 413                         size, res.flags, inner.io_end, inner.mem_end);
 414                 }
 415         }
 416
 417         /* And for all of the subordinate busses. */
 418         for (ln=bus->children.next; ln != &bus->children; ln=ln->next)
 419                 pcibios_size_bridge(pci_bus_b(ln), &inner);
 420
 421         /* turn the ending locations into sizes (subtract start) */
 422         inner.io_end -= inner.io_start - 1;
 423         inner.mem_end -= inner.mem_start - 1;
 424
 425         /* Align the sizes up by bridge rules */
 426         inner.io_end = ROUND_UP(inner.io_end, 4*1024) - 1;
 427         inner.mem_end = ROUND_UP(inner.mem_end, 1*1024*1024) - 1;
 428
 429         /* PPB - PCI bridge Device will normaller also have "outer" != NULL. */
 430         if (bridge) {
 431                 /* Adjust the bus' allocation requirements */
 432                 /* PPB's pci device Bridge resources */
 433
 434                 bus->resource[0] = &bridge->resource[PCI_BRIDGE_RESOURCES];
 435                 bus->resource[1] = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
 436
 437                 bus->resource[0]->start = bus->resource[1]->start  = 0;
 438                 bus->resource[0]->parent= bus->resource[1]->parent = NULL;
 439
 440                 bus->resource[0]->end    = inner.io_end;
 441                 bus->resource[0]->flags  = IORESOURCE_IO;
 442
 443                 bus->resource[1]->end    = inner.mem_end;
 444                 bus->resource[1]->flags  = IORESOURCE_MEM;
 445         }
 446
 447         /* adjust parent's resource requirements */
 448         if (outer) {
 449                 outer->io_end = ROUND_UP(outer->io_end, 4*1024);
 450                 outer->io_end += inner.io_end;
 451
 452                 outer->mem_end = ROUND_UP(outer->mem_end, 1*1024*1024);
 453                 outer->mem_end += inner.mem_end;
 454         }
 455 }
 456
 457 #undef ROUND_UP
 458
 459
 460 int __devinit
 461 pcibios_enable_device(struct pci_dev *dev)
 462 {
 463         u16 cmd, old_cmd;
 464         int idx;
 465
 466         /*
 467         ** The various platform PDC's (aka "BIOS" for PCs) don't
 468         ** enable all the same bits. We just make sure they are here.
 469         */
 470         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 471         old_cmd = cmd;
 472
 473         /*
 474         ** See if any resources have been allocated
 475         */
 476         for (idx=0; idx<6; idx++) {
 477                 struct resource *r = &dev->resource[idx];
 478                 if (r->flags & IORESOURCE_IO)
 479                         cmd |= PCI_COMMAND_IO;
 480                 if (r->flags & IORESOURCE_MEM)
 481                         cmd |= PCI_COMMAND_MEMORY;
 482         }
 483
 484         /*
 485         ** System error and Parity Error reporting are enabled by default.
 486         ** Devices that do NOT want those behaviors should clear them
 487         ** (eg PCI graphics, possibly networking).
 488         ** Interfaces like SCSI certainly should not. We want the
 489         ** system to crash if a system or parity error is detected.
 490         ** At least until the device driver can recover from such an error.
 491         */
 492         cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
 493
 494         if (cmd != old_cmd) {
 495                 printk("PCIBIOS: Enabling device %s (%04x -> %04x)\n",
 496                         dev->slot_name, old_cmd, cmd);
 497                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 498         }
 499
 500         return 0;
 501 }
 502
 503
 504 void __devinit
 505 pcibios_assign_unassigned_resources(struct pci_bus *bus)
 506 {
 507         struct list_head *ln;
 508
 509         for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next)
 510         {
 511                 pdev_assign_unassigned_resources(pci_dev_b(ln));
 512         }
 513
 514         /* And for all of the sub-busses.  */
 515         for (ln=bus->children.next; ln != &bus->children; ln=ln->next)
 516                 pcibios_assign_unassigned_resources(pci_bus_b(ln));
 517
 518 }
 519
 520 /*
 521 ** PARISC specific (unfortunately)
 522 */
 523 void pcibios_register_hba(struct pci_hba_data *hba)
 524 {
 525         hba->next = hba_list;
 526         hba_list = hba;
 527
 528         ASSERT(hba_count < PCI_HBA_MAX);
 529
 530         /*
 531         ** pci_port->in/out() uses parisc_pci_hba to lookup parameter.
 532         */
 533         parisc_pci_hba[hba_count] = hba;
 534         hba->hba_num = hba_count++;
 535 }